| #
db5be31c |
| 09-Jun-2020 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1108: add support to set and get spi clock
Change-Id: I96891a4adb53bbb84e27cc0ac5eddf3c613c1baa
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| #
8094aeb8 |
| 08-Jan-2019 |
Jon Lin <jon.lin@rock-chips.com> |
clk: rockchip: rv1108: add NANDC and SFC clk init
Currently RV1108 run in 1.2G GPLL.
NANDC need 1200 / 8 div = 150MHz.
SFC need 1200 / 12 div = 100MHz.
Change-Id: Ia3f401b0cf13587209d0d68d76a9891dd
clk: rockchip: rv1108: add NANDC and SFC clk init
Currently RV1108 run in 1.2G GPLL.
NANDC need 1200 / 8 div = 150MHz.
SFC need 1200 / 12 div = 100MHz.
Change-Id: Ia3f401b0cf13587209d0d68d76a9891dd3bcf990
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
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| #
98ebaf0e |
| 30-Nov-2018 |
vicent.chi <vicent.chi@rock-chips.com> |
CRU: rv1108 add emmc clk get and set
Change-Id: I8cbfda46d2f7e84f11dbcca844d00c87559d0aa0
Signed-off-by: vicent.chi <vicent.chi@rock-chips.com>
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| #
680c4834 |
| 06-Jun-2018 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1108: support i2c clk get and set rate
Change-Id: Iff7e9191e66e0eff828b9ea51cb952ee7139457f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| #
5cb579f1 |
| 31-May-2018 |
Elaine Zhang <zhangqing@rock-chips.com> |
rockchip: clk: rv1108: Add some frequency setting interfaces
support PLL freq setting,
support bus and peri clk freq setting,
support aclk vio and dclk vop freq setting.
Change-Id: I894552c1e1bb1bd
rockchip: clk: rv1108: Add some frequency setting interfaces
support PLL freq setting,
support bus and peri clk freq setting,
support aclk vio and dclk vop freq setting.
Change-Id: I894552c1e1bb1bd13a143e200edf289234a53c1d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
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| #
95b95808 |
| 01-Feb-2018 |
Zhihuan He <huan.he@rock-chips.com> |
rockchip: add rv1108 sdram driver
add rv1108 sdram driver so we can set up sdram in SPL
Change-Id: Iecc6e896921b68ec97bf7d890a61a4ff75d6876b
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
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| #
befbd723 |
| 20-Sep-2017 |
David Wu <david.wu@rock-chips.com> |
rockchip: clk: Add rv1108 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Change-Id: I1f
rockchip: clk: Add rv1108 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Change-Id: I1ff152b72a75680601f22c5b621de8b2198a6778
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
(cherry picked from commit 2e4ce50d1aca35d13944f48a7e15d0b63e86eb38)
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| #
156d64fa |
| 08-Jun-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-rockchip
Here is additional rk3368 and rk3399 support, rv1108 support,
refactoring HDMI video (brought in from Anatolij's tree to resolve
conflicts), some mkimage fixe
Merge git://git.denx.de/u-boot-rockchip
Here is additional rk3368 and rk3399 support, rv1108 support,
refactoring HDMI video (brought in from Anatolij's tree to resolve
conflicts), some mkimage fixes and a few other things.
show more ...
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| #
bae2f282 |
| 01-Jun-2017 |
Andy Yan <andy.yan@rock-chips.com> |
rockchip: clk: Add rv1108 clock driver
Add clock driver support for Rockchip rv1108 soc
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
|