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Searched refs:OSC_HZ (Results 1 – 25 of 46) sorted by relevance

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/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rv1106.c92 rate = OSC_HZ; in rv1106_peri_get_clk()
104 rate = OSC_HZ; in rv1106_peri_get_clk()
114 rate = OSC_HZ; in rv1106_peri_get_clk()
126 rate = OSC_HZ; in rv1106_peri_get_clk()
136 rate = OSC_HZ; in rv1106_peri_get_clk()
144 rate = OSC_HZ; in rv1106_peri_get_clk()
154 rate = OSC_HZ; in rv1106_peri_get_clk()
274 rate = OSC_HZ; in rv1106_i2c_get_clk()
305 rate = OSC_HZ; in rv1106_i2c_get_clk()
338 return OSC_HZ; in rv1106_crypto_get_clk()
[all …]
H A Dclk_rv1126b.c87 rate = OSC_HZ; in rv1126b_peri_get_clk()
95 rate = OSC_HZ; in rv1126b_peri_get_clk()
223 rate = OSC_HZ; in rv1126b_i2c_get_clk()
233 rate = OSC_HZ; in rv1126b_i2c_get_clk()
255 if (rate == OSC_HZ) in rv1126b_i2c_set_clk()
263 if (rate == OSC_HZ) in rv1126b_i2c_set_clk()
296 rate = OSC_HZ; in rv1126b_crypto_get_clk()
369 prate = OSC_HZ; in rv1126b_mmc_get_clk()
383 prate = OSC_HZ; in rv1126b_mmc_get_clk()
397 prate = OSC_HZ; in rv1126b_mmc_get_clk()
[all …]
H A Dclk_rv1103b.c101 prate = OSC_HZ; in rv1103b_peri_get_clk()
151 if (!(OSC_HZ % rate)) { in rv1103b_peri_set_clk()
153 div = DIV_ROUND_UP(OSC_HZ, rate); in rv1103b_peri_set_clk()
198 rate = OSC_HZ; in rv1103b_i2c_get_clk()
289 prate = OSC_HZ; in rv1103b_mmc_get_clk()
301 prate = OSC_HZ; in rv1103b_mmc_get_clk()
313 prate = OSC_HZ; in rv1103b_mmc_get_clk()
325 prate = OSC_HZ; in rv1103b_mmc_get_clk()
339 if ((OSC_HZ % rate) == 0) { in rv1103b_mmc_set_clk()
341 prate = OSC_HZ; in rv1103b_mmc_set_clk()
[all …]
H A Dclk_rk3562.c363 rate = OSC_HZ; in rk3562_i2c_get_rate()
384 rate = OSC_HZ; in rk3562_i2c_get_rate()
404 } else if (rate == OSC_HZ) { in rk3562_i2c_set_rate()
467 return OSC_HZ; in rk3562_uart_get_rate()
517 return OSC_HZ; in rk3562_uart_get_rate()
533 } else if (rate == OSC_HZ) { in rk3562_uart_set_rate()
595 } else if (rate == OSC_HZ) { in rk3562_uart_set_rate()
636 rate = OSC_HZ; in rk3562_pwm_get_rate()
665 rate = OSC_HZ; in rk3562_pwm_get_rate()
681 } else if (rate == OSC_HZ) { in rk3562_pwm_set_rate()
[all …]
H A Dclk_rk3588.c168 rate = OSC_HZ; in rk3588_center_get_clk()
181 rate = OSC_HZ; in rk3588_center_get_clk()
194 rate = OSC_HZ; in rk3588_center_get_clk()
207 rate = OSC_HZ; in rk3588_center_get_clk()
319 rate = OSC_HZ; in rk3588_top_get_clk()
522 return OSC_HZ; in rk3588_spi_get_clk()
606 return OSC_HZ; in rk3588_pwm_get_clk()
665 prate = OSC_HZ; in rk3588_adc_get_clk()
676 prate = OSC_HZ; in rk3588_adc_get_clk()
693 if (!(OSC_HZ % rate)) { in rk3588_adc_set_clk()
[all …]
H A Dclk_rk3576.c197 rate = OSC_HZ; in rk3576_bus_get_clk()
208 rate = OSC_HZ; in rk3576_bus_get_clk()
313 rate = OSC_HZ; in rk3576_top_get_clk()
325 rate = OSC_HZ; in rk3576_top_get_clk()
462 rate = OSC_HZ; in rk3576_i2c_get_clk()
567 return OSC_HZ; in rk3576_spi_get_clk()
649 return OSC_HZ; in rk3576_pwm_get_clk()
703 prate = OSC_HZ; in rk3576_adc_get_clk()
711 prate = OSC_HZ; in rk3576_adc_get_clk()
726 if (!(OSC_HZ % rate)) { in rk3576_adc_set_clk()
[all …]
H A Dclk_rk3506.c506 prate = OSC_HZ; in rk3506_sdmmc_get_rate()
525 if (OSC_HZ % rate == 0) { in rk3506_sdmmc_set_rate()
527 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3506_sdmmc_set_rate()
559 prate = OSC_HZ; in rk3506_saradc_get_rate()
584 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3506_saradc_set_rate()
613 return DIV_TO_RATE(OSC_HZ, div); in rk3506_tsadc_get_rate()
624 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3506_tsadc_set_rate()
630 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3506_tsadc_set_rate()
815 prate = OSC_HZ; in rk3506_spi_get_rate()
834 if (OSC_HZ % rate == 0) { in rk3506_spi_set_rate()
[all …]
H A Dclk_rk3568.c222 return OSC_HZ * m / n; in rk3568_rtc32k_get_pmuclk()
234 rational_best_approximation(rate, OSC_HZ, in rk3568_rtc32k_set_pmuclk()
295 parent = OSC_HZ; in rk3568_pwm_get_pmuclk()
314 if (rate == OSC_HZ) { in rk3568_pwm_set_pmuclk()
752 rate = OSC_HZ; in rk3568_bus_get_clk()
765 rate = OSC_HZ; in rk3568_bus_get_clk()
833 rate = OSC_HZ; in rk3568_perimid_get_clk()
845 rate = OSC_HZ; in rk3568_perimid_get_clk()
912 rate = OSC_HZ; in rk3568_top_get_clk()
924 rate = OSC_HZ; in rk3568_top_get_clk()
[all …]
H A Dclk_rv1108.c33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
35 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
36 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
72 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
137 freq = OSC_HZ; in rkclk_pll_get_rate()
197 return DIV_TO_RATE(OSC_HZ, div); in rv1108_saradc_get_clk()
204 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rv1108_saradc_set_clk()
521 mmc_clk = DIV_TO_RATE(OSC_HZ, div) / 2; in rv1108_mmc_get_clk()
545 pll_rate = OSC_HZ; in rv1108_mmc_set_clk()
H A Dclk_rk3528.c621 rate = OSC_HZ; in rk3528_i2c_get_clk()
734 rate = OSC_HZ; in rk3528_spi_get_clk()
805 rate = OSC_HZ; in rk3528_pwm_get_clk()
871 return DIV_TO_RATE(OSC_HZ, div); in rk3528_adc_get_clk()
900 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3528_adc_set_clk()
923 prate = OSC_HZ; in rk3528_sdmmc_get_clk()
934 if (OSC_HZ % rate == 0) { in rk3528_sdmmc_set_clk()
935 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3528_sdmmc_set_clk()
970 parent = OSC_HZ; in rk3528_sfc_get_clk()
980 if (OSC_HZ % rate == 0) { in rk3528_sfc_set_clk()
[all …]
H A Dclk_rk3036.c51 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
53 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
54 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
69 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
225 return OSC_HZ; in rkclk_pll_get_rate()
274 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; in rockchip_mmc_get_clk()
290 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rockchip_mmc_set_clk()
H A Dclk_rk3188.c94 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
95 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
111 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
262 return OSC_HZ; in rkclk_pll_get_rate()
398 return DIV_TO_RATE(OSC_HZ, div); in rk3188_saradc_get_clk()
405 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3188_saradc_set_clk()
H A Dclk_pll.c38 #define OSC_HZ (24UL * MHZ) macro
375 ulong rate, p_rate = OSC_HZ / KHZ; in rk3036_pll_get_rate()
389 return OSC_HZ; in rk3036_pll_get_rate()
576 return OSC_HZ; in rk3588_pll_get_rate()
591 rate = OSC_HZ / p; in rk3588_pll_get_rate()
598 frac_rate64 = OSC_HZ * k; in rk3588_pll_get_rate()
605 u64 frac_rate64 = OSC_HZ * k; in rk3588_pll_get_rate()
H A Dclk_rk3308.c331 return DIV_TO_RATE(OSC_HZ, div) / 2; in rk3308_mmc_get_clk()
363 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk3308_mmc_set_clk()
389 return DIV_TO_RATE(OSC_HZ, div); in rk3308_saradc_get_clk()
398 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in rk3308_saradc_set_clk()
417 return DIV_TO_RATE(OSC_HZ, div); in rk3308_tsadc_get_clk()
426 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in rk3308_tsadc_set_clk()
536 parent = OSC_HZ; in rk3308_vop_get_clk()
596 if (best_rate != hz && hz == OSC_HZ) { in rk3308_vop_set_clk()
871 return OSC_HZ * m / n; in rk3308_rtc32k_get_clk()
880 rational_best_approximation(hz, OSC_HZ, in rk3308_rtc32k_set_clk()
H A Dclk_rk3066.c96 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
97 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
113 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
264 return OSC_HZ; in rkclk_pll_get_rate()
H A Dclk_rk3288.c213 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
214 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
241 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
286 return OSC_HZ; in rkclk_pll_get_rate()
358 uint ref_khz = OSC_HZ / 1000, nr, nf = 0; in pll_para_config()
745 src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate; in rockchip_mmc_get_clk()
760 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rockchip_mmc_set_clk()
954 return DIV_TO_RATE(OSC_HZ, div); in rockchip_saradc_get_clk()
961 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rockchip_saradc_set_clk()
986 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rockchip_tsadc_set_clk()
H A Dclk_rk3368.c55 #define OSC_HZ (24 * 1000 * 1000) macro
107 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
108 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
144 uint ref_khz = OSC_HZ / 1000, nr, nf = 0; in pll_para_config()
234 return OSC_HZ; in rkclk_pll_get_rate()
254 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
318 pll_rate = OSC_HZ; in rk3368_mmc_get_clk()
571 return DIV_TO_RATE(OSC_HZ, div); in rk3368_saradc_get_clk()
578 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3368_saradc_set_clk()
H A Dclk_rk3399.c50 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
350 return OSC_HZ; in rkclk_pll_get_rate()
369 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
447 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_para_config()
821 return DIV_TO_RATE(OSC_HZ, div); in rk3399_mmc_get_clk()
841 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk3399_mmc_set_clk()
868 src_clk_div = DIV_ROUND_UP(OSC_HZ, set_rate); in rk3399_mmc_set_clk()
966 return DIV_TO_RATE(OSC_HZ, div); in rk3399_saradc_get_clk()
973 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3399_saradc_set_clk()
991 return DIV_TO_RATE(OSC_HZ, div); in rk3399_tsadc_get_clk()
[all …]
H A Dclk_px30.c110 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_clk_set_by_auto()
228 vco_hz = OSC_HZ / 1000 * rate->fbdiv / rate->refdiv * 1000; in rkclk_set_pll()
281 return OSC_HZ; in rkclk_pll_get_rate()
575 return DIV_TO_RATE(OSC_HZ, div) / 2; in px30_mmc_get_clk()
607 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in px30_mmc_set_clk()
711 return DIV_TO_RATE(OSC_HZ, div); in px30_saradc_get_clk()
719 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in px30_saradc_set_clk()
737 return DIV_TO_RATE(OSC_HZ, div); in px30_tsadc_get_clk()
745 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in px30_tsadc_set_clk()
1042 return DIV_TO_RATE(OSC_HZ, div); in px30_otp_get_clk()
[all …]
H A Dclk_rv1126.c191 return OSC_HZ * m / n; in rv1126_rtc32k_get_pmuclk()
203 rational_best_approximation(rate, OSC_HZ, in rv1126_rtc32k_set_pmuclk()
272 return OSC_HZ; in rv1126_pwm_get_pmuclk()
279 return OSC_HZ; in rv1126_pwm_get_pmuclk()
296 if (rate == OSC_HZ) { in rv1126_pwm_set_pmuclk()
314 if (rate == OSC_HZ) { in rv1126_pwm_set_pmuclk()
889 return OSC_HZ; in rv1126_pwm_get_clk()
899 if (rate == OSC_HZ) { in rv1126_pwm_set_clk()
923 return DIV_TO_RATE(OSC_HZ, div); in rv1126_saradc_get_clk()
931 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rv1126_saradc_set_clk()
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3188.h9 #define OSC_HZ (24 * 1000 * 1000) macro
H A Dcru_rk3066.h9 #define OSC_HZ (24 * 1000 * 1000) macro
H A Dcru_rk3399.h80 #define OSC_HZ (24*MHz) macro
H A Dcru_rk3128.h13 #define OSC_HZ (24 * MHz) macro
H A Dcru_rk322x.h12 #define OSC_HZ (24 * MHz) macro

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