| 46e2c853 | 02-Apr-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
uniphier: define PLAT_XLAT_TABLES_DYNAMIC only for BL2
This is not used in BL31 or Bl32 for this platform.
Pass it to BL2_CPPFLAGS instead of defining it for all BL images.
This will produce sligh
uniphier: define PLAT_XLAT_TABLES_DYNAMIC only for BL2
This is not used in BL31 or Bl32 for this platform.
Pass it to BL2_CPPFLAGS instead of defining it for all BL images.
This will produce slightly smaller BL31 and Bl32.
Change-Id: I66ec5179f8dc5b112e65547335e7dd0a0f4074cd Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| 1dc17569 | 01-Apr-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
plat: remove redundant =1 from -D option
As GCC manual says, -D option defines a macro as 1, if =<value> is omitted.
-D <name> Predefine <name> as a macro, with definition 1.
The same appl
plat: remove redundant =1 from -D option
As GCC manual says, -D option defines a macro as 1, if =<value> is omitted.
-D <name> Predefine <name> as a macro, with definition 1.
The same applied with Clang, too.
In the context of -D option, =1 is always redundant.
Change-Id: I487489a1ea3eb51e734741619c1e65dab1420bc4 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| 9cefb4b1 | 01-Apr-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Pass more -D options to BL*_CPPFLAGS instead of BL*_CFLAGS
Commit d5e97a1d2c79 ("Build: define IMAGE_AT_EL1 or IMAGE_AT_EL3 globally for C files") does not have commit 848a7e8ce1d9 ("Build: introduc
Pass more -D options to BL*_CPPFLAGS instead of BL*_CFLAGS
Commit d5e97a1d2c79 ("Build: define IMAGE_AT_EL1 or IMAGE_AT_EL3 globally for C files") does not have commit 848a7e8ce1d9 ("Build: introduce per-BL CPPFLAGS and ASFLAGS") as an ancestor because they were pulled almost at the same time.
This is a follow-up conversion to be consistent with commit 11a3c5ee7325 ("plat: pass -D option to BL*_CPPFLAGS instead of BL*_CFLAGS").
With this change, the command line option, IMAGE_AT_EL3, will be passed to .S files as well.
I remove the definition in include/lib/cpus/aarch64/cpu_macros.S
Otherwise, the following error would happen.
include/lib/cpus/aarch64/cpu_macros.S:29:0: error: "IMAGE_AT_EL3" redefined [-Werror]
Change-Id: I943c8f22356483c2ae3c57b515c69243a8fa6889 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| 664e15c2 | 26-Mar-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
uniphier: support read-only xlat tables
BL2 for this platform uses mmap_add_dynamic_region(), but BL31 and BL32 (TSP) only use static mapping. So, BL31 and BL32 can make the tables read-only after e
uniphier: support read-only xlat tables
BL2 for this platform uses mmap_add_dynamic_region(), but BL31 and BL32 (TSP) only use static mapping. So, BL31 and BL32 can make the tables read-only after enabling MMU.
Enable ALLOW_RO_XLAT_TABLES by default.
Change-Id: Ib59c44697163629119888bb6abd47fa144f09ba3 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| dd53cfe1 | 03-Feb-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
uniphier: prepare uniphier_soc_info() for next SoC
The revision register address will be changed in the next SoC.
The LSI revision is needed in order to know where the revision register is located,
uniphier: prepare uniphier_soc_info() for next SoC
The revision register address will be changed in the next SoC.
The LSI revision is needed in order to know where the revision register is located, but you need to read out the revision register for that. This is impossible.
We need to know the revision register address by other means. Use BL_CODE_BASE, where the base address of the TF image that is currently running. If it is bigger than 0x80000000 (i.e. the DRAM base is 0x80000000), we assume it is a legacy SoC.
Change-Id: I9d7f4325fe2085a8a1ab5310025e5948da611256 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| 8eaffdf7 | 03-Feb-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
uniphier: make on-chip SRAM region configurable
The on-chip SRAM region will be changed in the next SoC. Make it configurable. Also, split the mmap code into a new helper function so that it can be
uniphier: make on-chip SRAM region configurable
The on-chip SRAM region will be changed in the next SoC. Make it configurable. Also, split the mmap code into a new helper function so that it can be re-used for another boot mode.
Change-Id: I89f40432bf852a58ebc9be5d9dec4136b8dc010b Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|