1/* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <assert_macros.S> 10#include <context.h> 11 12#if CTX_INCLUDE_EL2_REGS 13 .global el2_sysregs_context_save 14 .global el2_sysregs_context_restore 15#endif 16 17 .global el1_sysregs_context_save 18 .global el1_sysregs_context_restore 19#if CTX_INCLUDE_FPREGS 20 .global fpregs_context_save 21 .global fpregs_context_restore 22#endif 23 .global save_gp_pmcr_pauth_regs 24 .global restore_gp_pmcr_pauth_regs 25 .global el3_exit 26 27#if CTX_INCLUDE_EL2_REGS 28 29/* ----------------------------------------------------- 30 * The following function strictly follows the AArch64 31 * PCS to use x9-x17 (temporary caller-saved registers) 32 * to save EL2 system register context. It assumes that 33 * 'x0' is pointing to a 'el2_sys_regs' structure where 34 * the register context will be saved. 35 * 36 * The following registers are not added. 37 * AMEVCNTVOFF0<n>_EL2 38 * AMEVCNTVOFF1<n>_EL2 39 * ICH_AP0R<n>_EL2 40 * ICH_AP1R<n>_EL2 41 * ICH_LR<n>_EL2 42 * ----------------------------------------------------- 43 */ 44 45func el2_sysregs_context_save 46 mrs x9, actlr_el2 47 mrs x10, afsr0_el2 48 stp x9, x10, [x0, #CTX_ACTLR_EL2] 49 50 mrs x11, afsr1_el2 51 mrs x12, amair_el2 52 stp x11, x12, [x0, #CTX_AFSR1_EL2] 53 54 mrs x13, cnthctl_el2 55 mrs x14, cnthp_ctl_el2 56 stp x13, x14, [x0, #CTX_CNTHCTL_EL2] 57 58 mrs x15, cnthp_cval_el2 59 mrs x16, cnthp_tval_el2 60 stp x15, x16, [x0, #CTX_CNTHP_CVAL_EL2] 61 62 mrs x17, cntvoff_el2 63 mrs x9, cptr_el2 64 stp x17, x9, [x0, #CTX_CNTVOFF_EL2] 65 66 mrs x10, dbgvcr32_el2 67 mrs x11, elr_el2 68 stp x10, x11, [x0, #CTX_DBGVCR32_EL2] 69 70 mrs x14, esr_el2 71 mrs x15, far_el2 72 stp x14, x15, [x0, #CTX_ESR_EL2] 73 74 mrs x16, fpexc32_el2 75 mrs x17, hacr_el2 76 stp x16, x17, [x0, #CTX_FPEXC32_EL2] 77 78 mrs x9, hcr_el2 79 mrs x10, hpfar_el2 80 stp x9, x10, [x0, #CTX_HCR_EL2] 81 82 mrs x11, hstr_el2 83 mrs x12, ICC_SRE_EL2 84 stp x11, x12, [x0, #CTX_HSTR_EL2] 85 86 mrs x13, ICH_HCR_EL2 87 mrs x14, ICH_VMCR_EL2 88 stp x13, x14, [x0, #CTX_ICH_HCR_EL2] 89 90 mrs x15, mair_el2 91 mrs x16, mdcr_el2 92 stp x15, x16, [x0, #CTX_MAIR_EL2] 93 94 mrs x17, PMSCR_EL2 95 mrs x9, sctlr_el2 96 stp x17, x9, [x0, #CTX_PMSCR_EL2] 97 98 mrs x10, spsr_el2 99 mrs x11, sp_el2 100 stp x10, x11, [x0, #CTX_SPSR_EL2] 101 102 mrs x12, tcr_el2 103 mrs x13, tpidr_el2 104 stp x12, x13, [x0, #CTX_TCR_EL2] 105 106 mrs x14, ttbr0_el2 107 mrs x15, vbar_el2 108 stp x14, x15, [x0, #CTX_TTBR0_EL2] 109 110 mrs x16, vmpidr_el2 111 mrs x17, vpidr_el2 112 stp x16, x17, [x0, #CTX_VMPIDR_EL2] 113 114 mrs x9, vtcr_el2 115 mrs x10, vttbr_el2 116 stp x9, x10, [x0, #CTX_VTCR_EL2] 117 118#if CTX_INCLUDE_MTE_REGS 119 mrs x11, TFSR_EL2 120 str x11, [x0, #CTX_TFSR_EL2] 121#endif 122 123#if ENABLE_MPAM_FOR_LOWER_ELS 124 mrs x9, MPAM2_EL2 125 mrs x10, MPAMHCR_EL2 126 stp x9, x10, [x0, #CTX_MPAM2_EL2] 127 128 mrs x11, MPAMVPM0_EL2 129 mrs x12, MPAMVPM1_EL2 130 stp x11, x12, [x0, #CTX_MPAMVPM0_EL2] 131 132 mrs x13, MPAMVPM2_EL2 133 mrs x14, MPAMVPM3_EL2 134 stp x13, x14, [x0, #CTX_MPAMVPM2_EL2] 135 136 mrs x15, MPAMVPM4_EL2 137 mrs x16, MPAMVPM5_EL2 138 stp x15, x16, [x0, #CTX_MPAMVPM4_EL2] 139 140 mrs x17, MPAMVPM6_EL2 141 mrs x9, MPAMVPM7_EL2 142 stp x17, x9, [x0, #CTX_MPAMVPM6_EL2] 143 144 mrs x10, MPAMVPMV_EL2 145 str x10, [x0, #CTX_MPAMVPMV_EL2] 146#endif 147 148 149#if ARM_ARCH_AT_LEAST(8, 6) 150 mrs x11, HAFGRTR_EL2 151 mrs x12, HDFGRTR_EL2 152 stp x11, x12, [x0, #CTX_HAFGRTR_EL2] 153 154 mrs x13, HDFGWTR_EL2 155 mrs x14, HFGITR_EL2 156 stp x13, x14, [x0, #CTX_HDFGWTR_EL2] 157 158 mrs x15, HFGRTR_EL2 159 mrs x16, HFGWTR_EL2 160 stp x15, x16, [x0, #CTX_HFGRTR_EL2] 161 162 mrs x17, CNTPOFF_EL2 163 str x17, [x0, #CTX_CNTPOFF_EL2] 164#endif 165 166#if ARM_ARCH_AT_LEAST(8, 4) 167 mrs x9, cnthps_ctl_el2 168 mrs x10, cnthps_cval_el2 169 stp x9, x10, [x0, #CTX_CNTHPS_CTL_EL2] 170 171 mrs x11, cnthps_tval_el2 172 mrs x12, cnthvs_ctl_el2 173 stp x11, x12, [x0, #CTX_CNTHPS_TVAL_EL2] 174 175 mrs x13, cnthvs_cval_el2 176 mrs x14, cnthvs_tval_el2 177 stp x13, x14, [x0, #CTX_CNTHVS_CVAL_EL2] 178 179 mrs x15, cnthv_ctl_el2 180 mrs x16, cnthv_cval_el2 181 stp x15, x16, [x0, #CTX_CNTHV_CTL_EL2] 182 183 mrs x17, cnthv_tval_el2 184 mrs x9, contextidr_el2 185 stp x17, x9, [x0, #CTX_CNTHV_TVAL_EL2] 186 187 mrs x10, sder32_el2 188 str x10, [x0, #CTX_SDER32_EL2] 189 190 mrs x11, ttbr1_el2 191 str x11, [x0, #CTX_TTBR1_EL2] 192 193 mrs x12, vdisr_el2 194 str x12, [x0, #CTX_VDISR_EL2] 195 196 mrs x13, vncr_el2 197 str x13, [x0, #CTX_VNCR_EL2] 198 199 mrs x14, vsesr_el2 200 str x14, [x0, #CTX_VSESR_EL2] 201 202 mrs x15, vstcr_el2 203 str x15, [x0, #CTX_VSTCR_EL2] 204 205 mrs x16, vsttbr_el2 206 str x16, [x0, #CTX_VSTTBR_EL2] 207 208 mrs x17, TRFCR_EL2 209 str x17, [x0, #CTX_TRFCR_EL2] 210#endif 211 212#if ARM_ARCH_AT_LEAST(8, 5) 213 mrs x9, scxtnum_el2 214 str x9, [x0, #CTX_SCXTNUM_EL2] 215#endif 216 217 ret 218endfunc el2_sysregs_context_save 219 220/* ----------------------------------------------------- 221 * The following function strictly follows the AArch64 222 * PCS to use x9-x17 (temporary caller-saved registers) 223 * to restore EL2 system register context. It assumes 224 * that 'x0' is pointing to a 'el2_sys_regs' structure 225 * from where the register context will be restored 226 227 * The following registers are not restored 228 * AMEVCNTVOFF0<n>_EL2 229 * AMEVCNTVOFF1<n>_EL2 230 * ICH_AP0R<n>_EL2 231 * ICH_AP1R<n>_EL2 232 * ICH_LR<n>_EL2 233 * ----------------------------------------------------- 234 */ 235func el2_sysregs_context_restore 236 237#if ERRATA_SPECULATIVE_AT 238/* Clear EPD0 and EPD1 bit and M bit to disable PTW */ 239 mrs x9, hcr_el2 240 tst x9, #HCR_E2H_BIT 241 bne 1f 242 mrs x9, tcr_el2 243 orr x9, x9, #TCR_EPD0_BIT 244 orr x9, x9, #TCR_EPD1_BIT 245 msr tcr_el2, x9 2461: mrs x9, sctlr_el2 247 bic x9, x9, #SCTLR_M_BIT 248 msr sctlr_el2, x9 249 isb 250#endif 251 252 ldp x9, x10, [x0, #CTX_ACTLR_EL2] 253 msr actlr_el2, x9 254 msr afsr0_el2, x10 255 256 ldp x11, x12, [x0, #CTX_AFSR1_EL2] 257 msr afsr1_el2, x11 258 msr amair_el2, x12 259 260 ldp x13, x14, [x0, #CTX_CNTHCTL_EL2] 261 msr cnthctl_el2, x13 262 msr cnthp_ctl_el2, x14 263 264 ldp x15, x16, [x0, #CTX_CNTHP_CVAL_EL2] 265 msr cnthp_cval_el2, x15 266 msr cnthp_tval_el2, x16 267 268 ldp x17, x9, [x0, #CTX_CNTVOFF_EL2] 269 msr cntvoff_el2, x17 270 msr cptr_el2, x9 271 272 ldp x10, x11, [x0, #CTX_DBGVCR32_EL2] 273 msr dbgvcr32_el2, x10 274 msr elr_el2, x11 275 276 ldp x14, x15, [x0, #CTX_ESR_EL2] 277 msr esr_el2, x14 278 msr far_el2, x15 279 280 ldp x16, x17, [x0, #CTX_FPEXC32_EL2] 281 msr fpexc32_el2, x16 282 msr hacr_el2, x17 283 284 ldp x9, x10, [x0, #CTX_HCR_EL2] 285 msr hcr_el2, x9 286 msr hpfar_el2, x10 287 288 ldp x11, x12, [x0, #CTX_HSTR_EL2] 289 msr hstr_el2, x11 290 msr ICC_SRE_EL2, x12 291 292 ldp x13, x14, [x0, #CTX_ICH_HCR_EL2] 293 msr ICH_HCR_EL2, x13 294 msr ICH_VMCR_EL2, x14 295 296 ldp x15, x16, [x0, #CTX_MAIR_EL2] 297 msr mair_el2, x15 298 msr mdcr_el2, x16 299 300 ldr x17, [x0, #CTX_PMSCR_EL2] 301 msr PMSCR_EL2, x17 302 303 ldp x10, x11, [x0, #CTX_SPSR_EL2] 304 msr spsr_el2, x10 305 msr sp_el2, x11 306 307 ldr x12, [x0, #CTX_TPIDR_EL2] 308 msr tpidr_el2, x12 309 310 ldp x14, x15, [x0, #CTX_TTBR0_EL2] 311 msr ttbr0_el2, x14 312 msr vbar_el2, x15 313 314 ldp x16, x17, [x0, #CTX_VMPIDR_EL2] 315 msr vmpidr_el2, x16 316 msr vpidr_el2, x17 317 318 ldp x9, x10, [x0, #CTX_VTCR_EL2] 319 msr vtcr_el2, x9 320 msr vttbr_el2, x10 321 322#if CTX_INCLUDE_MTE_REGS 323 ldr x11, [x0, #CTX_TFSR_EL2] 324 msr TFSR_EL2, x11 325#endif 326 327#if ENABLE_MPAM_FOR_LOWER_ELS 328 ldp x9, x10, [x0, #CTX_MPAM2_EL2] 329 msr MPAM2_EL2, x9 330 msr MPAMHCR_EL2, x10 331 332 ldp x11, x12, [x0, #CTX_MPAMVPM0_EL2] 333 msr MPAMVPM0_EL2, x11 334 msr MPAMVPM1_EL2, x12 335 336 ldp x13, x14, [x0, #CTX_MPAMVPM2_EL2] 337 msr MPAMVPM2_EL2, x13 338 msr MPAMVPM3_EL2, x14 339 340 ldp x15, x16, [x0, #CTX_MPAMVPM4_EL2] 341 msr MPAMVPM4_EL2, x15 342 msr MPAMVPM5_EL2, x16 343 344 ldp x17, x9, [x0, #CTX_MPAMVPM6_EL2] 345 msr MPAMVPM6_EL2, x17 346 msr MPAMVPM7_EL2, x9 347 348 ldr x10, [x0, #CTX_MPAMVPMV_EL2] 349 msr MPAMVPMV_EL2, x10 350#endif 351 352#if ARM_ARCH_AT_LEAST(8, 6) 353 ldp x11, x12, [x0, #CTX_HAFGRTR_EL2] 354 msr HAFGRTR_EL2, x11 355 msr HDFGRTR_EL2, x12 356 357 ldp x13, x14, [x0, #CTX_HDFGWTR_EL2] 358 msr HDFGWTR_EL2, x13 359 msr HFGITR_EL2, x14 360 361 ldp x15, x16, [x0, #CTX_HFGRTR_EL2] 362 msr HFGRTR_EL2, x15 363 msr HFGWTR_EL2, x16 364 365 ldr x17, [x0, #CTX_CNTPOFF_EL2] 366 msr CNTPOFF_EL2, x17 367#endif 368 369#if ARM_ARCH_AT_LEAST(8, 4) 370 ldp x9, x10, [x0, #CTX_CNTHPS_CTL_EL2] 371 msr cnthps_ctl_el2, x9 372 msr cnthps_cval_el2, x10 373 374 ldp x11, x12, [x0, #CTX_CNTHPS_TVAL_EL2] 375 msr cnthps_tval_el2, x11 376 msr cnthvs_ctl_el2, x12 377 378 ldp x13, x14, [x0, #CTX_CNTHVS_CVAL_EL2] 379 msr cnthvs_cval_el2, x13 380 msr cnthvs_tval_el2, x14 381 382 ldp x15, x16, [x0, #CTX_CNTHV_CTL_EL2] 383 msr cnthv_ctl_el2, x15 384 msr cnthv_cval_el2, x16 385 386 ldp x17, x9, [x0, #CTX_CNTHV_TVAL_EL2] 387 msr cnthv_tval_el2, x17 388 msr contextidr_el2, x9 389 390 ldr x10, [x0, #CTX_SDER32_EL2] 391 msr sder32_el2, x10 392 393 ldr x11, [x0, #CTX_TTBR1_EL2] 394 msr ttbr1_el2, x11 395 396 ldr x12, [x0, #CTX_VDISR_EL2] 397 msr vdisr_el2, x12 398 399 ldr x13, [x0, #CTX_VNCR_EL2] 400 msr vncr_el2, x13 401 402 ldr x14, [x0, #CTX_VSESR_EL2] 403 msr vsesr_el2, x14 404 405 ldr x15, [x0, #CTX_VSTCR_EL2] 406 msr vstcr_el2, x15 407 408 ldr x16, [x0, #CTX_VSTTBR_EL2] 409 msr vsttbr_el2, x16 410 411 ldr x17, [x0, #CTX_TRFCR_EL2] 412 msr TRFCR_EL2, x17 413#endif 414 415#if ARM_ARCH_AT_LEAST(8, 5) 416 ldr x9, [x0, #CTX_SCXTNUM_EL2] 417 msr scxtnum_el2, x9 418#endif 419 420#if ERRATA_SPECULATIVE_AT 421/* 422 * Make sure all registers are stored successfully except 423 * SCTLR_EL2 and TCR_EL2 424 */ 425 isb 426#endif 427 428 ldr x9, [x0, #CTX_SCTLR_EL2] 429 msr sctlr_el2, x9 430 ldr x9, [x0, #CTX_TCR_EL2] 431 msr tcr_el2, x9 432 433 ret 434endfunc el2_sysregs_context_restore 435 436#endif /* CTX_INCLUDE_EL2_REGS */ 437 438/* ------------------------------------------------------------------ 439 * The following function strictly follows the AArch64 PCS to use 440 * x9-x17 (temporary caller-saved registers) to save EL1 system 441 * register context. It assumes that 'x0' is pointing to a 442 * 'el1_sys_regs' structure where the register context will be saved. 443 * ------------------------------------------------------------------ 444 */ 445func el1_sysregs_context_save 446 447 mrs x9, spsr_el1 448 mrs x10, elr_el1 449 stp x9, x10, [x0, #CTX_SPSR_EL1] 450 451 mrs x15, sctlr_el1 452 mrs x16, actlr_el1 453 stp x15, x16, [x0, #CTX_SCTLR_EL1] 454 455 mrs x17, cpacr_el1 456 mrs x9, csselr_el1 457 stp x17, x9, [x0, #CTX_CPACR_EL1] 458 459 mrs x10, sp_el1 460 mrs x11, esr_el1 461 stp x10, x11, [x0, #CTX_SP_EL1] 462 463 mrs x12, ttbr0_el1 464 mrs x13, ttbr1_el1 465 stp x12, x13, [x0, #CTX_TTBR0_EL1] 466 467 mrs x14, mair_el1 468 mrs x15, amair_el1 469 stp x14, x15, [x0, #CTX_MAIR_EL1] 470 471 mrs x16, tcr_el1 472 mrs x17, tpidr_el1 473 stp x16, x17, [x0, #CTX_TCR_EL1] 474 475 mrs x9, tpidr_el0 476 mrs x10, tpidrro_el0 477 stp x9, x10, [x0, #CTX_TPIDR_EL0] 478 479 mrs x13, par_el1 480 mrs x14, far_el1 481 stp x13, x14, [x0, #CTX_PAR_EL1] 482 483 mrs x15, afsr0_el1 484 mrs x16, afsr1_el1 485 stp x15, x16, [x0, #CTX_AFSR0_EL1] 486 487 mrs x17, contextidr_el1 488 mrs x9, vbar_el1 489 stp x17, x9, [x0, #CTX_CONTEXTIDR_EL1] 490 491 /* Save AArch32 system registers if the build has instructed so */ 492#if CTX_INCLUDE_AARCH32_REGS 493 mrs x11, spsr_abt 494 mrs x12, spsr_und 495 stp x11, x12, [x0, #CTX_SPSR_ABT] 496 497 mrs x13, spsr_irq 498 mrs x14, spsr_fiq 499 stp x13, x14, [x0, #CTX_SPSR_IRQ] 500 501 mrs x15, dacr32_el2 502 mrs x16, ifsr32_el2 503 stp x15, x16, [x0, #CTX_DACR32_EL2] 504#endif 505 506 /* Save NS timer registers if the build has instructed so */ 507#if NS_TIMER_SWITCH 508 mrs x10, cntp_ctl_el0 509 mrs x11, cntp_cval_el0 510 stp x10, x11, [x0, #CTX_CNTP_CTL_EL0] 511 512 mrs x12, cntv_ctl_el0 513 mrs x13, cntv_cval_el0 514 stp x12, x13, [x0, #CTX_CNTV_CTL_EL0] 515 516 mrs x14, cntkctl_el1 517 str x14, [x0, #CTX_CNTKCTL_EL1] 518#endif 519 520 /* Save MTE system registers if the build has instructed so */ 521#if CTX_INCLUDE_MTE_REGS 522 mrs x15, TFSRE0_EL1 523 mrs x16, TFSR_EL1 524 stp x15, x16, [x0, #CTX_TFSRE0_EL1] 525 526 mrs x9, RGSR_EL1 527 mrs x10, GCR_EL1 528 stp x9, x10, [x0, #CTX_RGSR_EL1] 529#endif 530 531 ret 532endfunc el1_sysregs_context_save 533 534/* ------------------------------------------------------------------ 535 * The following function strictly follows the AArch64 PCS to use 536 * x9-x17 (temporary caller-saved registers) to restore EL1 system 537 * register context. It assumes that 'x0' is pointing to a 538 * 'el1_sys_regs' structure from where the register context will be 539 * restored 540 * ------------------------------------------------------------------ 541 */ 542func el1_sysregs_context_restore 543 544#if ERRATA_SPECULATIVE_AT 545 mrs x9, tcr_el1 546 orr x9, x9, #TCR_EPD0_BIT 547 orr x9, x9, #TCR_EPD1_BIT 548 msr tcr_el1, x9 549 mrs x9, sctlr_el1 550 bic x9, x9, #SCTLR_M_BIT 551 msr sctlr_el1, x9 552 isb 553#endif 554 555 ldp x9, x10, [x0, #CTX_SPSR_EL1] 556 msr spsr_el1, x9 557 msr elr_el1, x10 558 559 ldr x16, [x0, #CTX_ACTLR_EL1] 560 msr actlr_el1, x16 561 562 ldp x17, x9, [x0, #CTX_CPACR_EL1] 563 msr cpacr_el1, x17 564 msr csselr_el1, x9 565 566 ldp x10, x11, [x0, #CTX_SP_EL1] 567 msr sp_el1, x10 568 msr esr_el1, x11 569 570 ldp x12, x13, [x0, #CTX_TTBR0_EL1] 571 msr ttbr0_el1, x12 572 msr ttbr1_el1, x13 573 574 ldp x14, x15, [x0, #CTX_MAIR_EL1] 575 msr mair_el1, x14 576 msr amair_el1, x15 577 578 ldr x16,[x0, #CTX_TPIDR_EL1] 579 msr tpidr_el1, x16 580 581 ldp x9, x10, [x0, #CTX_TPIDR_EL0] 582 msr tpidr_el0, x9 583 msr tpidrro_el0, x10 584 585 ldp x13, x14, [x0, #CTX_PAR_EL1] 586 msr par_el1, x13 587 msr far_el1, x14 588 589 ldp x15, x16, [x0, #CTX_AFSR0_EL1] 590 msr afsr0_el1, x15 591 msr afsr1_el1, x16 592 593 ldp x17, x9, [x0, #CTX_CONTEXTIDR_EL1] 594 msr contextidr_el1, x17 595 msr vbar_el1, x9 596 597 /* Restore AArch32 system registers if the build has instructed so */ 598#if CTX_INCLUDE_AARCH32_REGS 599 ldp x11, x12, [x0, #CTX_SPSR_ABT] 600 msr spsr_abt, x11 601 msr spsr_und, x12 602 603 ldp x13, x14, [x0, #CTX_SPSR_IRQ] 604 msr spsr_irq, x13 605 msr spsr_fiq, x14 606 607 ldp x15, x16, [x0, #CTX_DACR32_EL2] 608 msr dacr32_el2, x15 609 msr ifsr32_el2, x16 610#endif 611 /* Restore NS timer registers if the build has instructed so */ 612#if NS_TIMER_SWITCH 613 ldp x10, x11, [x0, #CTX_CNTP_CTL_EL0] 614 msr cntp_ctl_el0, x10 615 msr cntp_cval_el0, x11 616 617 ldp x12, x13, [x0, #CTX_CNTV_CTL_EL0] 618 msr cntv_ctl_el0, x12 619 msr cntv_cval_el0, x13 620 621 ldr x14, [x0, #CTX_CNTKCTL_EL1] 622 msr cntkctl_el1, x14 623#endif 624 /* Restore MTE system registers if the build has instructed so */ 625#if CTX_INCLUDE_MTE_REGS 626 ldp x11, x12, [x0, #CTX_TFSRE0_EL1] 627 msr TFSRE0_EL1, x11 628 msr TFSR_EL1, x12 629 630 ldp x13, x14, [x0, #CTX_RGSR_EL1] 631 msr RGSR_EL1, x13 632 msr GCR_EL1, x14 633#endif 634 635#if ERRATA_SPECULATIVE_AT 636/* 637 * Make sure all registers are stored successfully except 638 * SCTLR_EL1 and TCR_EL1 639 */ 640 isb 641#endif 642 643 ldr x9, [x0, #CTX_SCTLR_EL1] 644 msr sctlr_el1, x9 645 ldr x9, [x0, #CTX_TCR_EL1] 646 msr tcr_el1, x9 647 648 /* No explict ISB required here as ERET covers it */ 649 ret 650endfunc el1_sysregs_context_restore 651 652/* ------------------------------------------------------------------ 653 * The following function follows the aapcs_64 strictly to use 654 * x9-x17 (temporary caller-saved registers according to AArch64 PCS) 655 * to save floating point register context. It assumes that 'x0' is 656 * pointing to a 'fp_regs' structure where the register context will 657 * be saved. 658 * 659 * Access to VFP registers will trap if CPTR_EL3.TFP is set. 660 * However currently we don't use VFP registers nor set traps in 661 * Trusted Firmware, and assume it's cleared. 662 * 663 * TODO: Revisit when VFP is used in secure world 664 * ------------------------------------------------------------------ 665 */ 666#if CTX_INCLUDE_FPREGS 667func fpregs_context_save 668 stp q0, q1, [x0, #CTX_FP_Q0] 669 stp q2, q3, [x0, #CTX_FP_Q2] 670 stp q4, q5, [x0, #CTX_FP_Q4] 671 stp q6, q7, [x0, #CTX_FP_Q6] 672 stp q8, q9, [x0, #CTX_FP_Q8] 673 stp q10, q11, [x0, #CTX_FP_Q10] 674 stp q12, q13, [x0, #CTX_FP_Q12] 675 stp q14, q15, [x0, #CTX_FP_Q14] 676 stp q16, q17, [x0, #CTX_FP_Q16] 677 stp q18, q19, [x0, #CTX_FP_Q18] 678 stp q20, q21, [x0, #CTX_FP_Q20] 679 stp q22, q23, [x0, #CTX_FP_Q22] 680 stp q24, q25, [x0, #CTX_FP_Q24] 681 stp q26, q27, [x0, #CTX_FP_Q26] 682 stp q28, q29, [x0, #CTX_FP_Q28] 683 stp q30, q31, [x0, #CTX_FP_Q30] 684 685 mrs x9, fpsr 686 str x9, [x0, #CTX_FP_FPSR] 687 688 mrs x10, fpcr 689 str x10, [x0, #CTX_FP_FPCR] 690 691#if CTX_INCLUDE_AARCH32_REGS 692 mrs x11, fpexc32_el2 693 str x11, [x0, #CTX_FP_FPEXC32_EL2] 694#endif 695 ret 696endfunc fpregs_context_save 697 698/* ------------------------------------------------------------------ 699 * The following function follows the aapcs_64 strictly to use x9-x17 700 * (temporary caller-saved registers according to AArch64 PCS) to 701 * restore floating point register context. It assumes that 'x0' is 702 * pointing to a 'fp_regs' structure from where the register context 703 * will be restored. 704 * 705 * Access to VFP registers will trap if CPTR_EL3.TFP is set. 706 * However currently we don't use VFP registers nor set traps in 707 * Trusted Firmware, and assume it's cleared. 708 * 709 * TODO: Revisit when VFP is used in secure world 710 * ------------------------------------------------------------------ 711 */ 712func fpregs_context_restore 713 ldp q0, q1, [x0, #CTX_FP_Q0] 714 ldp q2, q3, [x0, #CTX_FP_Q2] 715 ldp q4, q5, [x0, #CTX_FP_Q4] 716 ldp q6, q7, [x0, #CTX_FP_Q6] 717 ldp q8, q9, [x0, #CTX_FP_Q8] 718 ldp q10, q11, [x0, #CTX_FP_Q10] 719 ldp q12, q13, [x0, #CTX_FP_Q12] 720 ldp q14, q15, [x0, #CTX_FP_Q14] 721 ldp q16, q17, [x0, #CTX_FP_Q16] 722 ldp q18, q19, [x0, #CTX_FP_Q18] 723 ldp q20, q21, [x0, #CTX_FP_Q20] 724 ldp q22, q23, [x0, #CTX_FP_Q22] 725 ldp q24, q25, [x0, #CTX_FP_Q24] 726 ldp q26, q27, [x0, #CTX_FP_Q26] 727 ldp q28, q29, [x0, #CTX_FP_Q28] 728 ldp q30, q31, [x0, #CTX_FP_Q30] 729 730 ldr x9, [x0, #CTX_FP_FPSR] 731 msr fpsr, x9 732 733 ldr x10, [x0, #CTX_FP_FPCR] 734 msr fpcr, x10 735 736#if CTX_INCLUDE_AARCH32_REGS 737 ldr x11, [x0, #CTX_FP_FPEXC32_EL2] 738 msr fpexc32_el2, x11 739#endif 740 /* 741 * No explict ISB required here as ERET to 742 * switch to secure EL1 or non-secure world 743 * covers it 744 */ 745 746 ret 747endfunc fpregs_context_restore 748#endif /* CTX_INCLUDE_FPREGS */ 749 750/* ------------------------------------------------------------------ 751 * The following function is used to save and restore all the general 752 * purpose and ARMv8.3-PAuth (if enabled) registers. 753 * It also checks if Secure Cycle Counter is not disabled in MDCR_EL3 754 * when ARMv8.5-PMU is implemented, and if called from Non-secure 755 * state saves PMCR_EL0 and disables Cycle Counter. 756 * 757 * Ideally we would only save and restore the callee saved registers 758 * when a world switch occurs but that type of implementation is more 759 * complex. So currently we will always save and restore these 760 * registers on entry and exit of EL3. 761 * These are not macros to ensure their invocation fits within the 32 762 * instructions per exception vector. 763 * clobbers: x18 764 * ------------------------------------------------------------------ 765 */ 766func save_gp_pmcr_pauth_regs 767 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 768 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 769 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 770 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 771 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 772 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 773 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 774 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 775 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 776 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 777 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 778 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 779 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 780 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 781 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 782 mrs x18, sp_el0 783 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 784 785 /* ---------------------------------------------------------- 786 * Check if earlier initialization MDCR_EL3.SCCD to 1 failed, 787 * meaning that ARMv8-PMU is not implemented and PMCR_EL0 788 * should be saved in non-secure context. 789 * ---------------------------------------------------------- 790 */ 791 mrs x9, mdcr_el3 792 tst x9, #MDCR_SCCD_BIT 793 bne 1f 794 795 /* Secure Cycle Counter is not disabled */ 796 mrs x9, pmcr_el0 797 798 /* Check caller's security state */ 799 mrs x10, scr_el3 800 tst x10, #SCR_NS_BIT 801 beq 2f 802 803 /* Save PMCR_EL0 if called from Non-secure state */ 804 str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] 805 806 /* Disable cycle counter when event counting is prohibited */ 8072: orr x9, x9, #PMCR_EL0_DP_BIT 808 msr pmcr_el0, x9 809 isb 8101: 811#if CTX_INCLUDE_PAUTH_REGS 812 /* ---------------------------------------------------------- 813 * Save the ARMv8.3-PAuth keys as they are not banked 814 * by exception level 815 * ---------------------------------------------------------- 816 */ 817 add x19, sp, #CTX_PAUTH_REGS_OFFSET 818 819 mrs x20, APIAKeyLo_EL1 /* x21:x20 = APIAKey */ 820 mrs x21, APIAKeyHi_EL1 821 mrs x22, APIBKeyLo_EL1 /* x23:x22 = APIBKey */ 822 mrs x23, APIBKeyHi_EL1 823 mrs x24, APDAKeyLo_EL1 /* x25:x24 = APDAKey */ 824 mrs x25, APDAKeyHi_EL1 825 mrs x26, APDBKeyLo_EL1 /* x27:x26 = APDBKey */ 826 mrs x27, APDBKeyHi_EL1 827 mrs x28, APGAKeyLo_EL1 /* x29:x28 = APGAKey */ 828 mrs x29, APGAKeyHi_EL1 829 830 stp x20, x21, [x19, #CTX_PACIAKEY_LO] 831 stp x22, x23, [x19, #CTX_PACIBKEY_LO] 832 stp x24, x25, [x19, #CTX_PACDAKEY_LO] 833 stp x26, x27, [x19, #CTX_PACDBKEY_LO] 834 stp x28, x29, [x19, #CTX_PACGAKEY_LO] 835#endif /* CTX_INCLUDE_PAUTH_REGS */ 836 837 ret 838endfunc save_gp_pmcr_pauth_regs 839 840/* ------------------------------------------------------------------ 841 * This function restores ARMv8.3-PAuth (if enabled) and all general 842 * purpose registers except x30 from the CPU context. 843 * x30 register must be explicitly restored by the caller. 844 * ------------------------------------------------------------------ 845 */ 846func restore_gp_pmcr_pauth_regs 847#if CTX_INCLUDE_PAUTH_REGS 848 /* Restore the ARMv8.3 PAuth keys */ 849 add x10, sp, #CTX_PAUTH_REGS_OFFSET 850 851 ldp x0, x1, [x10, #CTX_PACIAKEY_LO] /* x1:x0 = APIAKey */ 852 ldp x2, x3, [x10, #CTX_PACIBKEY_LO] /* x3:x2 = APIBKey */ 853 ldp x4, x5, [x10, #CTX_PACDAKEY_LO] /* x5:x4 = APDAKey */ 854 ldp x6, x7, [x10, #CTX_PACDBKEY_LO] /* x7:x6 = APDBKey */ 855 ldp x8, x9, [x10, #CTX_PACGAKEY_LO] /* x9:x8 = APGAKey */ 856 857 msr APIAKeyLo_EL1, x0 858 msr APIAKeyHi_EL1, x1 859 msr APIBKeyLo_EL1, x2 860 msr APIBKeyHi_EL1, x3 861 msr APDAKeyLo_EL1, x4 862 msr APDAKeyHi_EL1, x5 863 msr APDBKeyLo_EL1, x6 864 msr APDBKeyHi_EL1, x7 865 msr APGAKeyLo_EL1, x8 866 msr APGAKeyHi_EL1, x9 867#endif /* CTX_INCLUDE_PAUTH_REGS */ 868 869 /* ---------------------------------------------------------- 870 * Restore PMCR_EL0 when returning to Non-secure state if 871 * Secure Cycle Counter is not disabled in MDCR_EL3 when 872 * ARMv8.5-PMU is implemented. 873 * ---------------------------------------------------------- 874 */ 875 mrs x0, scr_el3 876 tst x0, #SCR_NS_BIT 877 beq 2f 878 879 /* ---------------------------------------------------------- 880 * Back to Non-secure state. 881 * Check if earlier initialization MDCR_EL3.SCCD to 1 failed, 882 * meaning that ARMv8-PMU is not implemented and PMCR_EL0 883 * should be restored from non-secure context. 884 * ---------------------------------------------------------- 885 */ 886 mrs x0, mdcr_el3 887 tst x0, #MDCR_SCCD_BIT 888 bne 2f 889 ldr x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] 890 msr pmcr_el0, x0 8912: 892 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 893 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 894 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 895 ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 896 ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 897 ldp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 898 ldp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 899 ldp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 900 ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 901 ldp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 902 ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 903 ldp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 904 ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 905 ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 906 ldr x28, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 907 msr sp_el0, x28 908 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 909 ret 910endfunc restore_gp_pmcr_pauth_regs 911 912/* ------------------------------------------------------------------ 913 * This routine assumes that the SP_EL3 is pointing to a valid 914 * context structure from where the gp regs and other special 915 * registers can be retrieved. 916 * ------------------------------------------------------------------ 917 */ 918func el3_exit 919#if ENABLE_ASSERTIONS 920 /* el3_exit assumes SP_EL0 on entry */ 921 mrs x17, spsel 922 cmp x17, #MODE_SP_EL0 923 ASM_ASSERT(eq) 924#endif 925 926 /* ---------------------------------------------------------- 927 * Save the current SP_EL0 i.e. the EL3 runtime stack which 928 * will be used for handling the next SMC. 929 * Then switch to SP_EL3. 930 * ---------------------------------------------------------- 931 */ 932 mov x17, sp 933 msr spsel, #MODE_SP_ELX 934 str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 935 936 /* ---------------------------------------------------------- 937 * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET 938 * ---------------------------------------------------------- 939 */ 940 ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 941 ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 942 msr scr_el3, x18 943 msr spsr_el3, x16 944 msr elr_el3, x17 945 946#if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 947 /* ---------------------------------------------------------- 948 * Restore mitigation state as it was on entry to EL3 949 * ---------------------------------------------------------- 950 */ 951 ldr x17, [sp, #CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_DISABLE] 952 cbz x17, 1f 953 blr x17 9541: 955#endif 956 /* ---------------------------------------------------------- 957 * Restore general purpose (including x30), PMCR_EL0 and 958 * ARMv8.3-PAuth registers. 959 * Exit EL3 via ERET to a lower exception level. 960 * ---------------------------------------------------------- 961 */ 962 bl restore_gp_pmcr_pauth_regs 963 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 964 965#if IMAGE_BL31 && RAS_EXTENSION 966 /* ---------------------------------------------------------- 967 * Issue Error Synchronization Barrier to synchronize SErrors 968 * before exiting EL3. We're running with EAs unmasked, so 969 * any synchronized errors would be taken immediately; 970 * therefore no need to inspect DISR_EL1 register. 971 * ---------------------------------------------------------- 972 */ 973 esb 974#endif 975 exception_return 976 977endfunc el3_exit 978