1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLAT_ARM_H 7 #define PLAT_ARM_H 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 12 #include <drivers/arm/tzc_common.h> 13 #include <lib/bakery_lock.h> 14 #include <lib/cassert.h> 15 #include <lib/el3_runtime/cpu_data.h> 16 #include <lib/spinlock.h> 17 #include <lib/utils_def.h> 18 #include <lib/xlat_tables/xlat_tables_compat.h> 19 20 /******************************************************************************* 21 * Forward declarations 22 ******************************************************************************/ 23 struct meminfo; 24 struct image_info; 25 struct bl_params; 26 27 typedef struct arm_tzc_regions_info { 28 unsigned long long base; 29 unsigned long long end; 30 unsigned int sec_attr; 31 unsigned int nsaid_permissions; 32 } arm_tzc_regions_info_t; 33 34 /******************************************************************************* 35 * Default mapping definition of the TrustZone Controller for ARM standard 36 * platforms. 37 * Configure: 38 * - Region 0 with no access; 39 * - Region 1 with secure access only; 40 * - the remaining DRAM regions access from the given Non-Secure masters. 41 ******************************************************************************/ 42 #if SPM_MM 43 #define ARM_TZC_REGIONS_DEF \ 44 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ 45 TZC_REGION_S_RDWR, 0}, \ 46 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 47 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 48 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 49 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 50 {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \ 51 PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ 52 PLAT_ARM_TZC_NS_DEV_ACCESS} 53 54 #else 55 #define ARM_TZC_REGIONS_DEF \ 56 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ 57 TZC_REGION_S_RDWR, 0}, \ 58 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 59 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 60 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 61 PLAT_ARM_TZC_NS_DEV_ACCESS} 62 #endif 63 64 #define ARM_CASSERT_MMAP \ 65 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ 66 assert_plat_arm_mmap_mismatch); \ 67 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ 68 <= MAX_MMAP_REGIONS, \ 69 assert_max_mmap_regions); 70 71 void arm_setup_romlib(void); 72 73 #if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) 74 /* 75 * Use this macro to instantiate lock before it is used in below 76 * arm_lock_xxx() macros 77 */ 78 #define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) 79 #define ARM_LOCK_GET_INSTANCE (&arm_lock) 80 81 #if !HW_ASSISTED_COHERENCY 82 #define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock) 83 #else 84 #define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock 85 #endif 86 #define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock) 87 88 /* 89 * These are wrapper macros to the Coherent Memory Bakery Lock API. 90 */ 91 #define arm_lock_init() bakery_lock_init(&arm_lock) 92 #define arm_lock_get() bakery_lock_get(&arm_lock) 93 #define arm_lock_release() bakery_lock_release(&arm_lock) 94 95 #else 96 97 /* 98 * Empty macros for all other BL stages other than BL31 and BL32 99 */ 100 #define ARM_INSTANTIATE_LOCK static int arm_lock __unused 101 #define ARM_LOCK_GET_INSTANCE 0 102 #define arm_lock_init() 103 #define arm_lock_get() 104 #define arm_lock_release() 105 106 #endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */ 107 108 #if ARM_RECOM_STATE_ID_ENC 109 /* 110 * Macros used to parse state information from State-ID if it is using the 111 * recommended encoding for State-ID. 112 */ 113 #define ARM_LOCAL_PSTATE_WIDTH 4 114 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) 115 116 /* Macros to construct the composite power state */ 117 118 /* Make composite power state parameter till power level 0 */ 119 #if PSCI_EXTENDED_STATE_ID 120 121 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 122 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 123 #else 124 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 125 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 126 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 127 ((type) << PSTATE_TYPE_SHIFT)) 128 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 129 130 /* Make composite power state parameter till power level 1 */ 131 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 132 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ 133 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 134 135 /* Make composite power state parameter till power level 2 */ 136 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 137 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ 138 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 139 140 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 141 142 /* ARM State switch error codes */ 143 #define STATE_SW_E_PARAM (-2) 144 #define STATE_SW_E_DENIED (-3) 145 146 /* plat_get_rotpk_info() flags */ 147 #define ARM_ROTPK_REGS_ID 1 148 #define ARM_ROTPK_DEVEL_RSA_ID 2 149 #define ARM_ROTPK_DEVEL_ECDSA_ID 3 150 151 /* Defines used to retrieve ARM SOC revision */ 152 #define ARM_SOC_CONTINUATION_CODE U(0x4) 153 #define ARM_SOC_IDENTIFICATION_CODE U(0x3B) 154 #define ARM_SOC_CONTINUATION_SHIFT U(24) 155 #define ARM_SOC_IDENTIFICATION_SHIFT U(16) 156 157 /* IO storage utility functions */ 158 int arm_io_setup(void); 159 160 /* Security utility functions */ 161 void arm_tzc400_setup(uintptr_t tzc_base, 162 const arm_tzc_regions_info_t *tzc_regions); 163 struct tzc_dmc500_driver_data; 164 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, 165 const arm_tzc_regions_info_t *tzc_regions); 166 167 /* Console utility functions */ 168 void arm_console_boot_init(void); 169 void arm_console_boot_end(void); 170 void arm_console_runtime_init(void); 171 void arm_console_runtime_end(void); 172 173 /* Systimer utility function */ 174 void arm_configure_sys_timer(void); 175 176 /* PM utility functions */ 177 int arm_validate_power_state(unsigned int power_state, 178 psci_power_state_t *req_state); 179 int arm_validate_psci_entrypoint(uintptr_t entrypoint); 180 int arm_validate_ns_entrypoint(uintptr_t entrypoint); 181 void arm_system_pwr_domain_save(void); 182 void arm_system_pwr_domain_resume(void); 183 int arm_psci_read_mem_protect(int *enabled); 184 int arm_nor_psci_write_mem_protect(int val); 185 void arm_nor_psci_do_static_mem_protect(void); 186 void arm_nor_psci_do_dyn_mem_protect(void); 187 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); 188 189 /* Topology utility function */ 190 int arm_check_mpidr(u_register_t mpidr); 191 192 /* BL1 utility functions */ 193 void arm_bl1_early_platform_setup(void); 194 void arm_bl1_platform_setup(void); 195 void arm_bl1_plat_arch_setup(void); 196 197 /* BL2 utility functions */ 198 void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, struct meminfo *mem_layout); 199 void arm_bl2_platform_setup(void); 200 void arm_bl2_plat_arch_setup(void); 201 uint32_t arm_get_spsr_for_bl32_entry(void); 202 uint32_t arm_get_spsr_for_bl33_entry(void); 203 int arm_bl2_plat_handle_post_image_load(unsigned int image_id); 204 int arm_bl2_handle_post_image_load(unsigned int image_id); 205 struct bl_params *arm_get_next_bl_params(void); 206 207 /* BL2 at EL3 functions */ 208 void arm_bl2_el3_early_platform_setup(void); 209 void arm_bl2_el3_plat_arch_setup(void); 210 211 /* BL2U utility functions */ 212 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, 213 void *plat_info); 214 void arm_bl2u_platform_setup(void); 215 void arm_bl2u_plat_arch_setup(void); 216 217 /* BL31 utility functions */ 218 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 219 uintptr_t hw_config, void *plat_params_from_bl2); 220 void arm_bl31_platform_setup(void); 221 void arm_bl31_plat_runtime_setup(void); 222 void arm_bl31_plat_arch_setup(void); 223 224 /* TSP utility functions */ 225 void arm_tsp_early_platform_setup(void); 226 227 /* SP_MIN utility functions */ 228 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, 229 uintptr_t hw_config, void *plat_params_from_bl2); 230 void arm_sp_min_plat_runtime_setup(void); 231 void arm_sp_min_plat_arch_setup(void); 232 233 /* FIP TOC validity check */ 234 bool arm_io_is_toc_valid(void); 235 236 /* Utility functions for Dynamic Config */ 237 void arm_bl2_dyn_cfg_init(void); 238 void arm_bl1_set_mbedtls_heap(void); 239 int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); 240 241 #if MEASURED_BOOT 242 /* Measured boot related functions */ 243 void arm_bl1_set_bl2_hash(image_desc_t *image_desc); 244 #endif 245 246 /* 247 * Free the memory storing initialization code only used during an images boot 248 * time so it can be reclaimed for runtime data 249 */ 250 void arm_free_init_memory(void); 251 252 /* 253 * Make the higher level translation tables read-only 254 */ 255 void arm_xlat_make_tables_readonly(void); 256 257 /* 258 * Mandatory functions required in ARM standard platforms 259 */ 260 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); 261 void plat_arm_gic_driver_init(void); 262 void plat_arm_gic_init(void); 263 void plat_arm_gic_cpuif_enable(void); 264 void plat_arm_gic_cpuif_disable(void); 265 void plat_arm_gic_redistif_on(void); 266 void plat_arm_gic_redistif_off(void); 267 void plat_arm_gic_pcpu_init(void); 268 void plat_arm_gic_save(void); 269 void plat_arm_gic_resume(void); 270 void plat_arm_security_setup(void); 271 void plat_arm_pwrc_setup(void); 272 void plat_arm_interconnect_init(void); 273 void plat_arm_interconnect_enter_coherency(void); 274 void plat_arm_interconnect_exit_coherency(void); 275 void plat_arm_program_trusted_mailbox(uintptr_t address); 276 bool plat_arm_bl1_fwu_needed(void); 277 __dead2 void plat_arm_error_handler(int err); 278 279 /* 280 * Optional functions in ARM standard platforms 281 */ 282 void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames); 283 int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, 284 unsigned int *flags); 285 int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len, 286 unsigned int *flags); 287 int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len, 288 unsigned int *flags); 289 int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len, 290 unsigned int *flags); 291 292 #if ARM_PLAT_MT 293 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); 294 #endif 295 296 /* 297 * This function is called after loading SCP_BL2 image and it is used to perform 298 * any platform-specific actions required to handle the SCP firmware. 299 */ 300 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); 301 302 /* 303 * Optional functions required in ARM standard platforms 304 */ 305 void plat_arm_io_setup(void); 306 int plat_arm_get_alt_image_source( 307 unsigned int image_id, 308 uintptr_t *dev_handle, 309 uintptr_t *image_spec); 310 unsigned int plat_arm_calc_core_pos(u_register_t mpidr); 311 const mmap_region_t *plat_arm_get_mmap(void); 312 313 /* Allow platform to override psci_pm_ops during runtime */ 314 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); 315 316 /* Execution state switch in ARM platforms */ 317 int arm_execution_state_switch(unsigned int smc_fid, 318 uint32_t pc_hi, 319 uint32_t pc_lo, 320 uint32_t cookie_hi, 321 uint32_t cookie_lo, 322 void *handle); 323 324 /* Optional functions for SP_MIN */ 325 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 326 u_register_t arg2, u_register_t arg3); 327 328 /* global variables */ 329 extern plat_psci_ops_t plat_arm_psci_pm_ops; 330 extern const mmap_region_t plat_arm_mmap[]; 331 extern const unsigned int arm_pm_idle_states[]; 332 333 /* secure watchdog */ 334 void plat_arm_secure_wdt_start(void); 335 void plat_arm_secure_wdt_stop(void); 336 337 /* Get SOC-ID of ARM platform */ 338 uint32_t plat_arm_get_soc_id(void); 339 340 #endif /* PLAT_ARM_H */ 341