gicv2: Fix support for systems without secure interrupts

Accessing the interrupt_props array only happens inside a loop over
interrupt_props_num, so the GICv2 driver can cope with no secure
interrup

gicv2: Fix support for systems without secure interrupts

Accessing the interrupt_props array only happens inside a loop over
interrupt_props_num, so the GICv2 driver can cope with no secure
interrupts. As in fact we have already some asserts in place that
respect that, lets change the final place where we insist on a non-NULL
pointer to relax that.
This enables GICv2 platforms which have no need for a secure interrupt.

This only covers the non-deprecated code paths.

Also we remove a now redundant assert().

Change-Id: Id100ea978643d8558335ad28649d55743fe9bd4c
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge pull request #1313 from jonathanwright-ARM/jw/MISRA-switch-statements

Fix switch statements to comply with MISRA rules

drivers: fix switch statements to comply with MISRA rules

Ensure (where possible) that switch statements in drivers comply with
MISRA rules 16.1 - 16.7.

Change-Id: I7a91e04b02af80fbc4673a52293386c0

drivers: fix switch statements to comply with MISRA rules

Ensure (where possible) that switch statements in drivers comply with
MISRA rules 16.1 - 16.7.

Change-Id: I7a91e04b02af80fbc4673a52293386c0f81a0f7a
Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>

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GIC: Fix setting interrupt configuration

- Interrupt configuration is a 2-bit field, so the field shift has to
be double that of the bit number.

- Interrupt configuration (level- or edge-tr

GIC: Fix setting interrupt configuration

- Interrupt configuration is a 2-bit field, so the field shift has to
be double that of the bit number.

- Interrupt configuration (level- or edge-trigger) is specified in the
MSB of the field, not LSB.

Fixes applied to both GICv2 and GICv3 drivers.

Fixes ARM-software/tf-issues#570

Change-Id: Ia6ae6ed9ba9fb0e3eb0f921a833af48e365ba359
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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[PATCH 1/2] qemu: Support MULTI_CONSOLE_API

Include missing plat_helpers.S into pl011_console.S, to build successfully
when MULTI_CONSOLE_API is enabled.

Signed-off-by: Michalis Pappas <mpappas@fas

[PATCH 1/2] qemu: Support MULTI_CONSOLE_API

Include missing plat_helpers.S into pl011_console.S, to build successfully
when MULTI_CONSOLE_API is enabled.

Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>

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Emit warnings when using deprecated GIC init

Emit runtime warnings when intializing the GIC drivers using the
deprecated method of defining integer interrupt arrays in the GIC driver
data structures

Emit warnings when using deprecated GIC init

Emit runtime warnings when intializing the GIC drivers using the
deprecated method of defining integer interrupt arrays in the GIC driver
data structures; interrupt_prop_t arrays should be used instead. This
helps platforms detect that they have migration work to do. Previously,
no warning was emitted in this case. This affects both the GICv2 and GICv3
drivers.

Also use the __deprecated attribute to emit a build time warning if these
deprecated fields are used. These warnings are suppressed in the GIC
driver compatibility functions but will be visible if platforms use them.

Change-Id: I6b6b8f6c3b4920c448b6dcb82fc18442cfdf6c7a
Signed-off-by: Dan Handley <dan.handley@arm.com>

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Fix MISRA rule 8.4 Part 1

Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined

Fixed for:
make DEBUG=1 PLAT=fvp LOG_LEVEL=50 al

Fix MISRA rule 8.4 Part 1

Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined

Fixed for:
make DEBUG=1 PLAT=fvp LOG_LEVEL=50 all

Change-Id: I7c2ad3f5c015411c202605851240d5347e4cc8c7
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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Fix MISRA rule 8.4 in common code

Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined.

Change-Id: I26e042cb251a6f9590afa1340fda

Fix MISRA rule 8.4 in common code

Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined.

Change-Id: I26e042cb251a6f9590afa1340fdac73e42f23979
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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Resolve TZC400 build issue when DEBUG=1 and ENABLE_ASSERTIONS=0

Previously the definition of `_tzc_read_peripheral_id()` was wrapped
in ENABLE_ASSERTIONS build flag. This causes build issue for TZC4

Resolve TZC400 build issue when DEBUG=1 and ENABLE_ASSERTIONS=0

Previously the definition of `_tzc_read_peripheral_id()` was wrapped
in ENABLE_ASSERTIONS build flag. This causes build issue for TZC400 driver
when DEBUG=1 and ENABLE_ASSERTIONS=0. This patch fixes the same by
moving the definitions outside the ENABLE_ASSERTIONS build flag.

Change-Id: Ic1cad69f02ce65ac34aefd39eaa96d5781043152
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Remove URLs from comments

This fixes all defects according to MISRA Rule 3.1: "The character
sequences /* and // shall not be used within a comment". This affects
all URLs in comments, so they have

Remove URLs from comments

This fixes all defects according to MISRA Rule 3.1: "The character
sequences /* and // shall not be used within a comment". This affects
all URLs in comments, so they have been removed:

- The link in `sdei_state.c` can also be found in the documentation file
`docs/sdei.rst`.

- The bug that the file `io_fip.c` talks about doesn't affect the
currently supported version of GCC, so it doesn't make sense to keep
the comment. Note that the version of GCC officially supported is the
one that comes with Linaro Release 17.10, which is GCC 6.2.

- The link in `tzc400.c` was broken, and it didn't correctly direct to
the Technical Reference Manual it should. The link has been replaced
by the title of the document, which is more convenient when looking
for the document.

Change-Id: I89f60c25f635fd4c008a5d3a14028f814c147bbe
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1236 from dbasehore/gic-save-restore

RK3399 GIC save/restore

GICv3: Fix Dist restore for when the GIC is reset

If the GIC loses power during suspend, which the restore code was
written for, exit early in the post restore power sequence. This
prevents an asser

GICv3: Fix Dist restore for when the GIC is reset

If the GIC loses power during suspend, which the restore code was
written for, exit early in the post restore power sequence. This
prevents an assert from tripping, and the power sequence isn't needed
in this case anyways.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>

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drivers: arm: pl011: Update PL011 driver to support MULTI_CONSOLE_API

This patch updates the ARM PL011 console driver to support the new
console API. The driver will continue to support the old API

drivers: arm: pl011: Update PL011 driver to support MULTI_CONSOLE_API

This patch updates the ARM PL011 console driver to support the new
console API. The driver will continue to support the old API as well by
checking the MULTI_CONSOLE_API compile-time flag.

Change-Id: Ic34e4158addbb0c5fae500c9cff899c05a4f4206
Signed-off-by: Julius Werner <jwerner@chromium.org>

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Merge pull request #1145 from etienne-lms/rfc-armv7-2

Support ARMv7 architectures

GIC: Fix Group 0 enabling

At present, the GIC drivers enable Group 0 interrupts only if there are
Secure SPIs listed in the interrupt properties/list. This means that,
even if there are Group 0 SGIs

GIC: Fix Group 0 enabling

At present, the GIC drivers enable Group 0 interrupts only if there are
Secure SPIs listed in the interrupt properties/list. This means that,
even if there are Group 0 SGIs/PPIs configured, the group remained
disabled in the absence of a Group 0 SPI.

Modify both GICv2 and GICv3 SGI/PPI configuration to enable Group 0 when
corresponding SGIs/PPIs are present.

Change-Id: Id123e8aaee0c22b476eebe3800340906d83bbc6d
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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GICv2: Fix populating PE target data

This patch brings in the following fixes:

- The per-PE target data initialized during power up needs to be
flushed so as to be visible to other PEs.

-

GICv2: Fix populating PE target data

This patch brings in the following fixes:

- The per-PE target data initialized during power up needs to be
flushed so as to be visible to other PEs.

- Setup per-PE target data for the primary PE as well. At present,
this was only setup for secondary PEs when they were powered on.

Change-Id: Ibe3a57c14864e37b2326dd7ab321a5c7bf80e8af
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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ARMv7: GICv2 driver can manage GICv1 with security extension

Some SoCs integrate a GIC in version 1 that is currently not supported
by the trusted firmware. This change hijacks GICv2 driver to handl

ARMv7: GICv2 driver can manage GICv1 with security extension

Some SoCs integrate a GIC in version 1 that is currently not supported
by the trusted firmware. This change hijacks GICv2 driver to handle the
GICv1 as GICv1 is compatible enough with GICv2 as far as the platform
does not attempt to play with virtualization support or some GICv2
specific power features.

Note that current trusted firmware does not use these GICv2 features
that are not available in GICv1 Security Extension.

Change-Id: Ic2cb3055f1319a83455571d6d918661da583f179
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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GIC: Allow specifying interrupt properties

The GIC driver initialization currently allows an array of interrupts to
be configured as secure. Future use cases would require more interrupt
configurati

GIC: Allow specifying interrupt properties

The GIC driver initialization currently allows an array of interrupts to
be configured as secure. Future use cases would require more interrupt
configuration other than just security, such as priority.

This patch introduces a new interrupt property array as part of both
GICv2 and GICv3 driver data. The platform can populate the array with
interrupt numbers and respective properties. The corresponding driver
initialization iterates through the array, and applies interrupt
configuration as required.

This capability, and the current way of supplying array (or arrays, in
case of GICv3) of secure interrupts, are however mutually exclusive.
Henceforth, the platform should supply either:

- A list of interrupts to be mapped as secure (the current way).
Platforms that do this will continue working as they were. With this
patch, this scheme is deprecated.

- A list of interrupt properties (properties include interrupt group).
Individual interrupt properties are specified via. descriptors of
type 'interrupt_prop_desc_t', which can be populated with the macro
INTR_PROP_DESC().

A run time assert checks that the platform doesn't specify both.

Henceforth the old scheme of providing list of secure interrupts is
deprecated. When built with ERROR_DEPRECATED=1, GIC drivers will require
that the interrupt properties are supplied instead of an array of secure
interrupts.

Add a section to firmware design about configuring secure interrupts.

Fixes ARM-software/tf-issues#262

Change-Id: I8eec29e72eb69dbb6bce77879febf32c95376942
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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GIC: Add helpers to set interrupt configuration

The helpers perform read-modify-write on GIC*_ICFGR registers, but don't
serialise callers. Any serialisation must be taken care of by the
callers.

C

GIC: Add helpers to set interrupt configuration

The helpers perform read-modify-write on GIC*_ICFGR registers, but don't
serialise callers. Any serialisation must be taken care of by the
callers.

Change-Id: I71995f82ff2c7f70d37af0ede30d6ee18682fd3f
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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GIC: Add API to set priority mask

API documentation updated.

Change-Id: I40feec1fe67a960d035061b54dd55610bc34ce1d
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

GIC: Add API to set/clear interrupt pending

API documentation updated.

Change-Id: I14e33cfc7dfa93257c82d76fae186b17a1b6d266
Co-authored-by: Yousuf A <yousuf.sait@arm.com>
Signed-off-by: Jeenu Viswa

GIC: Add API to set/clear interrupt pending

API documentation updated.

Change-Id: I14e33cfc7dfa93257c82d76fae186b17a1b6d266
Co-authored-by: Yousuf A <yousuf.sait@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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GIC: Add API to set interrupt routing

SPIs can be routed to either a specific PE, or to any one of all
available PEs.

API documentation updated.

Change-Id: I28675f634568aaf4ea1aa8aa7ebf25b419a963e

GIC: Add API to set interrupt routing

SPIs can be routed to either a specific PE, or to any one of all
available PEs.

API documentation updated.

Change-Id: I28675f634568aaf4ea1aa8aa7ebf25b419a963ed
Co-authored-by: Yousuf A <yousuf.sait@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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GIC: Add API to raise secure SGI

API documentation updated.

Change-Id: I129725059299af6cc612bafa8d74817f779d7c4f
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

GIC: Add APIs to set interrupt type and query support

The back end GIC driver converts and assigns the interrupt type to
suitable group.

For GICv2, a build option GICV2_G0_FOR_EL3 is introduced, wh

GIC: Add APIs to set interrupt type and query support

The back end GIC driver converts and assigns the interrupt type to
suitable group.

For GICv2, a build option GICV2_G0_FOR_EL3 is introduced, which
determines to which type Group 0 interrupts maps to.

- When the build option is set 0 (the default), Group 0 interrupts are
meant for Secure EL1. This is presently the case.

- Otherwise, Group 0 interrupts are meant for EL3. This means the SPD
will have to synchronously hand over the interrupt to Secure EL1.

The query API allows the platform to query whether the platform supports
interrupts of a given type.

API documentation updated.

Change-Id: I60fdb4053ffe0bd006b3b20914914ebd311fc858
Co-authored-by: Yousuf A <yousuf.sait@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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GIC: Add API to set interrupt priority

API documentation updated.

Change-Id: Ib700eb1b8ca65503aeed0ac4ce0e7b934df67ff9
Co-authored-by: Yousuf A <yousuf.sait@arm.com>
Signed-off-by: Jeenu Viswambhar

GIC: Add API to set interrupt priority

API documentation updated.

Change-Id: Ib700eb1b8ca65503aeed0ac4ce0e7b934df67ff9
Co-authored-by: Yousuf A <yousuf.sait@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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