fix(gicv3): add an isb between the ICC_SRE_EL2 and ICC_SRE_EL1 writes

While ICC_SRE_EL2.SRE is 0, ICC_SRE_EL1.SRE is RAZ/WI. Except for an
isb between the two writes, there is nothing to guarantee t

fix(gicv3): add an isb between the ICC_SRE_EL2 and ICC_SRE_EL1 writes

While ICC_SRE_EL2.SRE is 0, ICC_SRE_EL1.SRE is RAZ/WI. Except for an
isb between the two writes, there is nothing to guarantee that the
ICC_SRE_EL2.SRE write has taken effect by the time the ICC_SRE_EL1.SRE
write occurs. Add the isb to guarantee that the write is successful.

Change-Id: Ib84193f49e67ed0a64d6e2c6c71fb99b5b58a211
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(gic): fix coverity issue INTEGER_OVERFLOW

Avoid unsigned underflow when spi_id_min is below the base.
Make all shifts in the CHIPR value composition 64-bit, to
avoid flagging overflow.

Change-I

fix(gic): fix coverity issue INTEGER_OVERFLOW

Avoid unsigned underflow when spi_id_min is below the base.
Make all shifts in the CHIPR value composition 64-bit, to
avoid flagging overflow.

Change-Id: I376809fc110ff45dd0682b4bcf8dab43cf03d300
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(scmi): fix coverity issue INTEGER_OVERFLOW

Fixes the following coverity issue -

CID 457917: (#1 of 1): Overflowed constant (INTEGER_OVERFLOW)
overflow_const: Expression lvl - 1U, where lvl is k

fix(scmi): fix coverity issue INTEGER_OVERFLOW

Fixes the following coverity issue -

CID 457917: (#1 of 1): Overflowed constant (INTEGER_OVERFLOW)
overflow_const: Expression lvl - 1U, where lvl is known to be equal
to 0, underflows the type of lvl - 1U, which is type unsigned int.

Change-Id: Id965c4b95159793944b3ef4658fd92e881d53c59
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(scmi): support graceful system power set

Add conditional compiler to control the flags in css_scp_suspend and
css_scp_system_off. This enable each platform can decide to use
graceful or forcefu

feat(scmi): support graceful system power set

Add conditional compiler to control the flags in css_scp_suspend and
css_scp_system_off. This enable each platform can decide to use
graceful or forceful flag in SCMI system power set command per
their use cases.

Upstream-Status: Pending
Change-Id: I99129a680927b9401385fca6094b476126e2f8c7
Signed-off-by: Jun Wu <jun.wu@arm.com>

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fix(dsu): fix illegal address Coverity finding

Based on -
https://scan4.scan.coverity.com/#/project-view/68818/11439?selectedIssue=425813
https://scan4.scan.coverity.com/#/project-view/68818/11439?s

fix(dsu): fix illegal address Coverity finding

Based on -
https://scan4.scan.coverity.com/#/project-view/68818/11439?selectedIssue=425813
https://scan4.scan.coverity.com/#/project-view/68818/11439?selectedIssue=425812
CID 425812: (#1 of 1): Illegal address computation (OVERRUN)

This patch avoids the OVERRUN/illegal address Coverity finding.

Change-Id: I8b2521c9f1f1e8c815c5a2940f98464bbb59e111
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(dsu): enable PMU registers access at EL1

- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
co

feat(dsu): enable PMU registers access at EL1

- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
counting in the secure state.

Change-Id: If3eb6e997330ae86f45760e0e862c003861f3d66
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>

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feat(gicv3): add GIC-720AE model id

Add GIC-720AE model id to power up its Redistributor in BL31 GIC
initialization.
No use case so far for multichip support on GIC-720AE.

Change-Id: Id6ca8144b0c02

feat(gicv3): add GIC-720AE model id

Add GIC-720AE model id to power up its Redistributor in BL31 GIC
initialization.
No use case so far for multichip support on GIC-720AE.

Change-Id: Id6ca8144b0c02557ba7569a536cece37e4c1fe98
Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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fix(gicv3): avoid incrementing global gicr_frames pointer

commit 75170704c9119a4947 (refactor(gicv3): clarify redistributor base
address usage with USE_GIC_DRIVER=3) introduced changes to walk the
r

fix(gicv3): avoid incrementing global gicr_frames pointer

commit 75170704c9119a4947 (refactor(gicv3): clarify redistributor base
address usage with USE_GIC_DRIVER=3) introduced changes to walk the
redistributor frames by incrementing the global `gicr_frames` pointer.
This leaves the pointer advanced after the first miss, so subsequent
CPUs do not start from the beginning of the array. Such behaviour is
incorrect in the presence of CPU hotplug or out-of-order CPU_ON
operations, where each CPU must be able to probe the full set of
redistributor frames independently.

Fix this by using a local iterator instead of modifying the global
`gicr_frames` pointer, preserving the array state for all CPUs.

While here, fix a typo in a comment and replace the `do…while`
loop with a safer `while` loop to avoid probing the zero terminator in
case a platform erroneously passes an empty array.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I6d6f73fb172c48f8e50b29ec2232648be3a6a6a0

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Merge changes from topic "xlnx_misra_fix_gen_gicv3" into integration

* changes:
fix(gicv3): typecast operands to match data type
fix(gicv3): add missing curly braces
fix(gicv3): fix misra viol

Merge changes from topic "xlnx_misra_fix_gen_gicv3" into integration

* changes:
fix(gicv3): typecast operands to match data type
fix(gicv3): add missing curly braces
fix(gicv3): fix misra violation 12.1
fix(gicv3): match function definition and declaration
fix(gicv3): typecast operands to match data type

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Merge changes from topic "xlnx_misra_fix_gen_arm" into integration

* changes:
fix(arm-drivers): add missing curly braces
fix(arm): typecast operands to match data type
fix(arm-drivers): declar

Merge changes from topic "xlnx_misra_fix_gen_arm" into integration

* changes:
fix(arm-drivers): add missing curly braces
fix(arm): typecast operands to match data type
fix(arm-drivers): declare unused parameters as void

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Merge changes from topic "Add-i.MX94/95-suport" into integration

* changes:
docs(maintainers): add i.MX9 to maintained paths
feat(imx94): add initial support for imx94
feat(imx95): add optee s

Merge changes from topic "Add-i.MX94/95-suport" into integration

* changes:
docs(maintainers): add i.MX9 to maintained paths
feat(imx94): add initial support for imx94
feat(imx95): add optee support
feat(imx95): support trusty os
feat(imx95): implement a semaphore for GIC quiescing
feat(imx95): add initial support for i.MX95
feat(imx9): add necessary ele api call support
feat(imx9): add imx9 common code base
refactor(imx): drop the __dead2 attribute
fix(imx): add static attribute for platform specific gic struct
feat(gic): change gic_cpuif_enable/disable to weak
feat(scmi): add i.MX9 SCMI vendor CPU protocol
feat(scmi): add base protocol agent API
feat(scmi): update version to 3.0
build(changelog): update for imx94/95 support

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Merge "fix(dcc): typecast operands to match data type" into integration

fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against 0

fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Icd480587b74c0e0a818498b680666ed43e94fef8
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(gicv3): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.Enclosed statement body w

fix(gicv3): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.Enclosed statement body within the curly
braces.

Change-Id: I657780b0e322a0aff990390a8dfc1af56dfd5c1d
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(gicv3): fix misra violation 12.1

This corrects the MISRA violation C2012-12.1:
When an expression contains multiple operators, use compound
assignment operator or curley braces to avoid unexpect

fix(gicv3): fix misra violation 12.1

This corrects the MISRA violation C2012-12.1:
When an expression contains multiple operators, use compound
assignment operator or curley braces to avoid unexpected behavior
due to operator precedence and which improves the readibility and
maintainability.

Change-Id: I8d09f136faae2869fc1ef2d6eb46de035b7e6a1e
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(gicv3): match function definition and declaration

This corrects the MISRA violation C2012-8.3:
change the type/qualifer of function parameter as per the functional
decleration. unction declerati

fix(gicv3): match function definition and declaration

This corrects the MISRA violation C2012-8.3:
change the type/qualifer of function parameter as per the functional
decleration. unction decleration and definition should be match to
avoid conflicts.

Change-Id: Ic6cff6719a38dffe78e4756d3bb7cf32512c5344
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a di

fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Id802961c24a57eea7dd928e2278d015a8747a4c5
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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feat(gic): change gic_cpuif_enable/disable to weak

For some platform like NXP i.MX94/95, the gic cpu interface
enable & disable need some special handling except the generic
gic_cpuif_enable/disable

feat(gic): change gic_cpuif_enable/disable to weak

For some platform like NXP i.MX94/95, the gic cpu interface
enable & disable need some special handling except the generic
gic_cpuif_enable/disable API. To allow these platform to reuse
the generic gic driver support, need to mark these two APIs as weak
to allow platforms to provide platform specific implementation.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I742fcb60bef20b051363f1fa86c6254e2f463129

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feat(scmi): add i.MX9 SCMI vendor CPU protocol

Add i.MX9 SCMI vendor specific CPU protocol

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.c

feat(scmi): add i.MX9 SCMI vendor CPU protocol

Add i.MX9 SCMI vendor specific CPU protocol

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Icc81bf9f4a32c08e4a3c358b1cf561ca4345a431

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feat(scmi): add base protocol agent API

Support protocol attributes and discover agents

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3879f703ec61

feat(scmi): add base protocol agent API

Support protocol attributes and discover agents

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3879f703ec6160bd794f48e3c41718ecce0ec88a

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Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration

* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
ref

Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration

* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
refactor(versal-net): use the generic GIC driver

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fix(console): create unique variable name

This corrects the MISRA violation C2012-5.7:
A tag name shall be a unique identifier.
Renamed the variable to ensure uniqueness.

Change-Id: I96e61caa8c6c7f

fix(console): create unique variable name

This corrects the MISRA violation C2012-5.7:
A tag name shall be a unique identifier.
Renamed the variable to ensure uniqueness.

Change-Id: I96e61caa8c6c7ff64759363afd24fc224d449f86
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3

The GICv3 driver has 2 methods of discovering the redistributors:
a) via setting gicr_base - done at boot and assumes

refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3

The GICv3 driver has 2 methods of discovering the redistributors:
a) via setting gicr_base - done at boot and assumes all GICR frames are
contiguous. This is the original method.

b) via gicv3_rdistif_probe() - called from platform code and requires
gicr_base == 0. It relaxes the requirement for frames to be
contiguous, like in a multichip configuration, and defers the
discovery to core bringup. This was introduced later.

Configurations possible with option a) are also possible with option b)
with only slightly different behaviour. USE_GIC_DRIVER=3 inherited
option b) from plat_gicv3_base.c and as such option a) is unusable.
However, it is unclear from code how this should be used. Clarify this
by requiring platforms initialise with gic_set_gicr_frames() and
adding relevant comments.

Also rename plat_arm_override_gicr_frames() to gic_set_gicr_frames() as
this is not plat arm specific and a part of the generic GIC driver.

Change-Id: I61d77211f8e65dc54cf9904069b500d26a06b5a5
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(arm-drivers): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.Enclosed statement

fix(arm-drivers): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.Enclosed statement body within the curly
braces.

Change-Id: I0e2ef3c2210816d1da09671157f23d42e493e356
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(arm-drivers): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Chan

fix(arm-drivers): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: I10c42f7b1ec5264a19feb7d666c2661bfdb45975
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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