1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <context.h> 12 #include <context_mgmt.h> 13 #include <interrupt_mgmt.h> 14 #include <platform.h> 15 #include <platform_def.h> 16 #include <pubsub_events.h> 17 #include <smcc_helpers.h> 18 #include <spe.h> 19 #include <string.h> 20 #include <utils.h> 21 22 23 /******************************************************************************* 24 * Context management library initialisation routine. This library is used by 25 * runtime services to share pointers to 'cpu_context' structures for the secure 26 * and non-secure states. Management of the structures and their associated 27 * memory is not done by the context management library e.g. the PSCI service 28 * manages the cpu context used for entry from and exit to the non-secure state. 29 * The Secure payload dispatcher service manages the context(s) corresponding to 30 * the secure state. It also uses this library to get access to the non-secure 31 * state cpu context pointers. 32 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 33 * which will used for programming an entry into a lower EL. The same context 34 * will used to save state upon exception entry from that EL. 35 ******************************************************************************/ 36 void cm_init(void) 37 { 38 /* 39 * The context management library has only global data to intialize, but 40 * that will be done when the BSS is zeroed out 41 */ 42 } 43 44 /******************************************************************************* 45 * The following function initializes the cpu_context 'ctx' for 46 * first use, and sets the initial entrypoint state as specified by the 47 * entry_point_info structure. 48 * 49 * The security state to initialize is determined by the SECURE attribute 50 * of the entry_point_info. The function returns a pointer to the initialized 51 * context and sets this as the next context to return to. 52 * 53 * The EE and ST attributes are used to configure the endianess and secure 54 * timer availability for the new execution context. 55 * 56 * To prepare the register state for entry call cm_prepare_el3_exit() and 57 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 58 * cm_e1_sysreg_context_restore(). 59 ******************************************************************************/ 60 static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 61 { 62 unsigned int security_state; 63 uint32_t scr_el3, pmcr_el0; 64 el3_state_t *state; 65 gp_regs_t *gp_regs; 66 unsigned long sctlr_elx; 67 68 assert(ctx); 69 70 security_state = GET_SECURITY_STATE(ep->h.attr); 71 72 /* Clear any residual register values from the context */ 73 zeromem(ctx, sizeof(*ctx)); 74 75 /* 76 * SCR_EL3 was initialised during reset sequence in macro 77 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 78 * affect the next EL. 79 * 80 * The following fields are initially set to zero and then updated to 81 * the required value depending on the state of the SPSR_EL3 and the 82 * Security state and entrypoint attributes of the next EL. 83 */ 84 scr_el3 = read_scr(); 85 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 86 SCR_ST_BIT | SCR_HCE_BIT); 87 /* 88 * SCR_NS: Set the security state of the next EL. 89 */ 90 if (security_state != SECURE) 91 scr_el3 |= SCR_NS_BIT; 92 /* 93 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 94 * Exception level as specified by SPSR. 95 */ 96 if (GET_RW(ep->spsr) == MODE_RW_64) 97 scr_el3 |= SCR_RW_BIT; 98 /* 99 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 100 * Secure timer registers to EL3, from AArch64 state only, if specified 101 * by the entrypoint attributes. 102 */ 103 if (EP_GET_ST(ep->h.attr)) 104 scr_el3 |= SCR_ST_BIT; 105 106 #ifndef HANDLE_EA_EL3_FIRST 107 /* 108 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 109 * to EL3 when executing at a lower EL. When executing at EL3, External 110 * Aborts are taken to EL3. 111 */ 112 scr_el3 &= ~SCR_EA_BIT; 113 #endif 114 115 #ifdef IMAGE_BL31 116 /* 117 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ rounting as 118 * indicated by the interrupt routing model for BL31. 119 */ 120 scr_el3 |= get_scr_el3_from_routing_model(security_state); 121 #endif 122 123 /* 124 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 125 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 126 * next mode is Hyp. 127 */ 128 if ((GET_RW(ep->spsr) == MODE_RW_64 129 && GET_EL(ep->spsr) == MODE_EL2) 130 || (GET_RW(ep->spsr) != MODE_RW_64 131 && GET_M32(ep->spsr) == MODE32_hyp)) { 132 scr_el3 |= SCR_HCE_BIT; 133 } 134 135 /* 136 * Initialise SCTLR_EL1 to the reset value corresponding to the target 137 * execution state setting all fields rather than relying of the hw. 138 * Some fields have architecturally UNKNOWN reset values and these are 139 * set to zero. 140 * 141 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 142 * 143 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 144 * required by PSCI specification) 145 */ 146 sctlr_elx = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0; 147 if (GET_RW(ep->spsr) == MODE_RW_64) 148 sctlr_elx |= SCTLR_EL1_RES1; 149 else { 150 /* 151 * If the target execution state is AArch32 then the following 152 * fields need to be set. 153 * 154 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 155 * instructions are not trapped to EL1. 156 * 157 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 158 * instructions are not trapped to EL1. 159 * 160 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 161 * CP15DMB, CP15DSB, and CP15ISB instructions. 162 */ 163 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 164 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 165 } 166 167 /* 168 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 169 * and other EL2 registers are set up by cm_preapre_ns_entry() as they 170 * are not part of the stored cpu_context. 171 */ 172 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 173 174 if (security_state == SECURE) { 175 /* 176 * Initialise PMCR_EL0 for secure context only, setting all 177 * fields rather than relying on hw. Some fields are 178 * architecturally UNKNOWN on reset. 179 * 180 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that 181 * is recorded in PMOVSCLR_EL0[31], occurs on the increment 182 * that changes PMCCNTR_EL0[63] from 1 to 0. 183 * 184 * PMCR_EL0.DP: Set to one so that the cycle counter, 185 * PMCCNTR_EL0 does not count when event counting is prohibited. 186 * 187 * PMCR_EL0.X: Set to zero to disable export of events. 188 * 189 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 190 * counts on every clock cycle. 191 */ 192 pmcr_el0 = ((PMCR_EL0_RESET_VAL | PMCR_EL0_LC_BIT 193 | PMCR_EL0_DP_BIT) 194 & ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)); 195 write_ctx_reg(get_sysregs_ctx(ctx), CTX_PMCR_EL0, pmcr_el0); 196 } 197 198 /* Populate EL3 state so that we've the right context before doing ERET */ 199 state = get_el3state_ctx(ctx); 200 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 201 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 202 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 203 204 /* 205 * Store the X0-X7 value from the entrypoint into the context 206 * Use memcpy as we are in control of the layout of the structures 207 */ 208 gp_regs = get_gpregs_ctx(ctx); 209 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 210 } 211 212 /******************************************************************************* 213 * Enable architecture extensions on first entry to Non-secure world. 214 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 215 * it is zero. 216 ******************************************************************************/ 217 static void enable_extensions_nonsecure(int el2_unused) 218 { 219 #if IMAGE_BL31 220 #if ENABLE_SPE_FOR_LOWER_ELS 221 spe_enable(el2_unused); 222 #endif 223 #endif 224 } 225 226 /******************************************************************************* 227 * The following function initializes the cpu_context for a CPU specified by 228 * its `cpu_idx` for first use, and sets the initial entrypoint state as 229 * specified by the entry_point_info structure. 230 ******************************************************************************/ 231 void cm_init_context_by_index(unsigned int cpu_idx, 232 const entry_point_info_t *ep) 233 { 234 cpu_context_t *ctx; 235 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 236 cm_init_context_common(ctx, ep); 237 } 238 239 /******************************************************************************* 240 * The following function initializes the cpu_context for the current CPU 241 * for first use, and sets the initial entrypoint state as specified by the 242 * entry_point_info structure. 243 ******************************************************************************/ 244 void cm_init_my_context(const entry_point_info_t *ep) 245 { 246 cpu_context_t *ctx; 247 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 248 cm_init_context_common(ctx, ep); 249 } 250 251 /******************************************************************************* 252 * Prepare the CPU system registers for first entry into secure or normal world 253 * 254 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 255 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 256 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 257 * For all entries, the EL1 registers are initialized from the cpu_context 258 ******************************************************************************/ 259 void cm_prepare_el3_exit(uint32_t security_state) 260 { 261 uint32_t sctlr_elx, scr_el3, mdcr_el2; 262 cpu_context_t *ctx = cm_get_context(security_state); 263 int el2_unused = 0; 264 265 assert(ctx); 266 267 if (security_state == NON_SECURE) { 268 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 269 if (scr_el3 & SCR_HCE_BIT) { 270 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 271 sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx), 272 CTX_SCTLR_EL1); 273 sctlr_elx &= SCTLR_EE_BIT; 274 sctlr_elx |= SCTLR_EL2_RES1; 275 write_sctlr_el2(sctlr_elx); 276 } else if (EL_IMPLEMENTED(2)) { 277 el2_unused = 1; 278 279 /* 280 * EL2 present but unused, need to disable safely. 281 * SCTLR_EL2 can be ignored in this case. 282 * 283 * Initialise all fields in HCR_EL2, except HCR_EL2.RW, 284 * to zero so that Non-secure operations do not trap to 285 * EL2. 286 * 287 * HCR_EL2.RW: Set this field to match SCR_EL3.RW 288 */ 289 write_hcr_el2((scr_el3 & SCR_RW_BIT) ? HCR_RW_BIT : 0); 290 291 /* 292 * Initialise CPTR_EL2 setting all fields rather than 293 * relying on the hw. All fields have architecturally 294 * UNKNOWN reset values. 295 * 296 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 297 * accesses to the CPACR_EL1 or CPACR from both 298 * Execution states do not trap to EL2. 299 * 300 * CPTR_EL2.TTA: Set to zero so that Non-secure System 301 * register accesses to the trace registers from both 302 * Execution states do not trap to EL2. 303 * 304 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 305 * to SIMD and floating-point functionality from both 306 * Execution states do not trap to EL2. 307 */ 308 write_cptr_el2(CPTR_EL2_RESET_VAL & 309 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 310 | CPTR_EL2_TFP_BIT)); 311 312 /* 313 * Initiliase CNTHCTL_EL2. All fields are 314 * architecturally UNKNOWN on reset and are set to zero 315 * except for field(s) listed below. 316 * 317 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 318 * Hyp mode of Non-secure EL0 and EL1 accesses to the 319 * physical timer registers. 320 * 321 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 322 * Hyp mode of Non-secure EL0 and EL1 accesses to the 323 * physical counter registers. 324 */ 325 write_cnthctl_el2(CNTHCTL_RESET_VAL | 326 EL1PCEN_BIT | EL1PCTEN_BIT); 327 328 /* 329 * Initialise CNTVOFF_EL2 to zero as it resets to an 330 * architecturally UNKNOWN value. 331 */ 332 write_cntvoff_el2(0); 333 334 /* 335 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 336 * MPIDR_EL1 respectively. 337 */ 338 write_vpidr_el2(read_midr_el1()); 339 write_vmpidr_el2(read_mpidr_el1()); 340 341 /* 342 * Initialise VTTBR_EL2. All fields are architecturally 343 * UNKNOWN on reset. 344 * 345 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 346 * 2 address translation is disabled, cache maintenance 347 * operations depend on the VMID. 348 * 349 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 350 * translation is disabled. 351 */ 352 write_vttbr_el2(VTTBR_RESET_VAL & 353 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 354 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 355 356 /* 357 * Initialise MDCR_EL2, setting all fields rather than 358 * relying on hw. Some fields are architecturally 359 * UNKNOWN on reset. 360 * 361 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 362 * EL1 System register accesses to the Debug ROM 363 * registers are not trapped to EL2. 364 * 365 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 366 * System register accesses to the powerdown debug 367 * registers are not trapped to EL2. 368 * 369 * MDCR_EL2.TDA: Set to zero so that System register 370 * accesses to the debug registers do not trap to EL2. 371 * 372 * MDCR_EL2.TDE: Set to zero so that debug exceptions 373 * are not routed to EL2. 374 * 375 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 376 * Monitors. 377 * 378 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 379 * EL1 accesses to all Performance Monitors registers 380 * are not trapped to EL2. 381 * 382 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 383 * and EL1 accesses to the PMCR_EL0 or PMCR are not 384 * trapped to EL2. 385 * 386 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 387 * architecturally-defined reset value. 388 */ 389 mdcr_el2 = ((MDCR_EL2_RESET_VAL | 390 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 391 >> PMCR_EL0_N_SHIFT)) & 392 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT 393 | MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT 394 | MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT 395 | MDCR_EL2_TPMCR_BIT)); 396 397 write_mdcr_el2(mdcr_el2); 398 399 /* 400 * Initialise HSTR_EL2. All fields are architecturally 401 * UNKNOWN on reset. 402 * 403 * HSTR_EL2.T<n>: Set all these fields to zero so that 404 * Non-secure EL0 or EL1 accesses to System registers 405 * do not trap to EL2. 406 */ 407 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 408 /* 409 * Initialise CNTHP_CTL_EL2. All fields are 410 * architecturally UNKNOWN on reset. 411 * 412 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 413 * physical timer and prevent timer interrupts. 414 */ 415 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 416 ~(CNTHP_CTL_ENABLE_BIT)); 417 } 418 enable_extensions_nonsecure(el2_unused); 419 } 420 421 cm_el1_sysregs_context_restore(security_state); 422 cm_set_next_eret_context(security_state); 423 } 424 425 /******************************************************************************* 426 * The next four functions are used by runtime services to save and restore 427 * EL1 context on the 'cpu_context' structure for the specified security 428 * state. 429 ******************************************************************************/ 430 void cm_el1_sysregs_context_save(uint32_t security_state) 431 { 432 cpu_context_t *ctx; 433 434 ctx = cm_get_context(security_state); 435 assert(ctx); 436 437 el1_sysregs_context_save(get_sysregs_ctx(ctx)); 438 439 #if IMAGE_BL31 440 if (security_state == SECURE) 441 PUBLISH_EVENT(cm_exited_secure_world); 442 else 443 PUBLISH_EVENT(cm_exited_normal_world); 444 #endif 445 } 446 447 void cm_el1_sysregs_context_restore(uint32_t security_state) 448 { 449 cpu_context_t *ctx; 450 451 ctx = cm_get_context(security_state); 452 assert(ctx); 453 454 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); 455 456 #if IMAGE_BL31 457 if (security_state == SECURE) 458 PUBLISH_EVENT(cm_entering_secure_world); 459 else 460 PUBLISH_EVENT(cm_entering_normal_world); 461 #endif 462 } 463 464 /******************************************************************************* 465 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 466 * given security state with the given entrypoint 467 ******************************************************************************/ 468 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 469 { 470 cpu_context_t *ctx; 471 el3_state_t *state; 472 473 ctx = cm_get_context(security_state); 474 assert(ctx); 475 476 /* Populate EL3 state so that ERET jumps to the correct entry */ 477 state = get_el3state_ctx(ctx); 478 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 479 } 480 481 /******************************************************************************* 482 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 483 * pertaining to the given security state 484 ******************************************************************************/ 485 void cm_set_elr_spsr_el3(uint32_t security_state, 486 uintptr_t entrypoint, uint32_t spsr) 487 { 488 cpu_context_t *ctx; 489 el3_state_t *state; 490 491 ctx = cm_get_context(security_state); 492 assert(ctx); 493 494 /* Populate EL3 state so that ERET jumps to the correct entry */ 495 state = get_el3state_ctx(ctx); 496 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 497 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 498 } 499 500 /******************************************************************************* 501 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 502 * pertaining to the given security state using the value and bit position 503 * specified in the parameters. It preserves all other bits. 504 ******************************************************************************/ 505 void cm_write_scr_el3_bit(uint32_t security_state, 506 uint32_t bit_pos, 507 uint32_t value) 508 { 509 cpu_context_t *ctx; 510 el3_state_t *state; 511 uint32_t scr_el3; 512 513 ctx = cm_get_context(security_state); 514 assert(ctx); 515 516 /* Ensure that the bit position is a valid one */ 517 assert((1 << bit_pos) & SCR_VALID_BIT_MASK); 518 519 /* Ensure that the 'value' is only a bit wide */ 520 assert(value <= 1); 521 522 /* 523 * Get the SCR_EL3 value from the cpu context, clear the desired bit 524 * and set it to its new value. 525 */ 526 state = get_el3state_ctx(ctx); 527 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 528 scr_el3 &= ~(1 << bit_pos); 529 scr_el3 |= value << bit_pos; 530 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 531 } 532 533 /******************************************************************************* 534 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 535 * given security state. 536 ******************************************************************************/ 537 uint32_t cm_get_scr_el3(uint32_t security_state) 538 { 539 cpu_context_t *ctx; 540 el3_state_t *state; 541 542 ctx = cm_get_context(security_state); 543 assert(ctx); 544 545 /* Populate EL3 state so that ERET jumps to the correct entry */ 546 state = get_el3state_ctx(ctx); 547 return read_ctx_reg(state, CTX_SCR_EL3); 548 } 549 550 /******************************************************************************* 551 * This function is used to program the context that's used for exception 552 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 553 * the required security state 554 ******************************************************************************/ 555 void cm_set_next_eret_context(uint32_t security_state) 556 { 557 cpu_context_t *ctx; 558 559 ctx = cm_get_context(security_state); 560 assert(ctx); 561 562 cm_set_next_context(ctx); 563 } 564