1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <gic_common.h> 12 #include <gicv2.h> 13 #include <interrupt_props.h> 14 #include <spinlock.h> 15 #include "../common/gic_common_private.h" 16 #include "gicv2_private.h" 17 18 static const gicv2_driver_data_t *driver_data; 19 20 /* 21 * Spinlock to guard registers needing read-modify-write. APIs protected by this 22 * spinlock are used either at boot time (when only a single CPU is active), or 23 * when the system is fully coherent. 24 */ 25 spinlock_t gic_lock; 26 27 /******************************************************************************* 28 * Enable secure interrupts and use FIQs to route them. Disable legacy bypass 29 * and set the priority mask register to allow all interrupts to trickle in. 30 ******************************************************************************/ 31 void gicv2_cpuif_enable(void) 32 { 33 unsigned int val; 34 35 assert(driver_data); 36 assert(driver_data->gicc_base); 37 38 /* 39 * Enable the Group 0 interrupts, FIQEn and disable Group 0/1 40 * bypass. 41 */ 42 val = CTLR_ENABLE_G0_BIT | FIQ_EN_BIT | FIQ_BYP_DIS_GRP0; 43 val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; 44 45 /* Program the idle priority in the PMR */ 46 gicc_write_pmr(driver_data->gicc_base, GIC_PRI_MASK); 47 gicc_write_ctlr(driver_data->gicc_base, val); 48 } 49 50 /******************************************************************************* 51 * Place the cpu interface in a state where it can never make a cpu exit wfi as 52 * as result of an asserted interrupt. This is critical for powering down a cpu 53 ******************************************************************************/ 54 void gicv2_cpuif_disable(void) 55 { 56 unsigned int val; 57 58 assert(driver_data); 59 assert(driver_data->gicc_base); 60 61 /* Disable secure, non-secure interrupts and disable their bypass */ 62 val = gicc_read_ctlr(driver_data->gicc_base); 63 val &= ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT); 64 val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; 65 val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; 66 gicc_write_ctlr(driver_data->gicc_base, val); 67 } 68 69 /******************************************************************************* 70 * Per cpu gic distributor setup which will be done by all cpus after a cold 71 * boot/hotplug. This marks out the secure SPIs and PPIs & enables them. 72 ******************************************************************************/ 73 void gicv2_pcpu_distif_init(void) 74 { 75 assert(driver_data); 76 assert(driver_data->gicd_base); 77 78 #if !ERROR_DEPRECATED 79 if (driver_data->interrupt_props != NULL) { 80 #endif 81 gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base, 82 driver_data->interrupt_props, 83 driver_data->interrupt_props_num); 84 #if !ERROR_DEPRECATED 85 } else { 86 assert(driver_data->g0_interrupt_array); 87 gicv2_secure_ppi_sgi_setup(driver_data->gicd_base, 88 driver_data->g0_interrupt_num, 89 driver_data->g0_interrupt_array); 90 } 91 #endif 92 } 93 94 /******************************************************************************* 95 * Global gic distributor init which will be done by the primary cpu after a 96 * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It 97 * then enables the secure GIC distributor interface. 98 ******************************************************************************/ 99 void gicv2_distif_init(void) 100 { 101 unsigned int ctlr; 102 103 assert(driver_data); 104 assert(driver_data->gicd_base); 105 106 /* Disable the distributor before going further */ 107 ctlr = gicd_read_ctlr(driver_data->gicd_base); 108 gicd_write_ctlr(driver_data->gicd_base, 109 ctlr & ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT)); 110 111 /* Set the default attribute of all SPIs */ 112 gicv2_spis_configure_defaults(driver_data->gicd_base); 113 114 #if !ERROR_DEPRECATED 115 if (driver_data->interrupt_props != NULL) { 116 #endif 117 gicv2_secure_spis_configure_props(driver_data->gicd_base, 118 driver_data->interrupt_props, 119 driver_data->interrupt_props_num); 120 #if !ERROR_DEPRECATED 121 } else { 122 assert(driver_data->g0_interrupt_array); 123 124 /* Configure the G0 SPIs */ 125 gicv2_secure_spis_configure(driver_data->gicd_base, 126 driver_data->g0_interrupt_num, 127 driver_data->g0_interrupt_array); 128 } 129 #endif 130 131 /* Re-enable the secure SPIs now that they have been configured */ 132 gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT); 133 } 134 135 /******************************************************************************* 136 * Initialize the ARM GICv2 driver with the provided platform inputs 137 ******************************************************************************/ 138 void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data) 139 { 140 unsigned int gic_version; 141 assert(plat_driver_data); 142 assert(plat_driver_data->gicd_base); 143 assert(plat_driver_data->gicc_base); 144 145 #if !ERROR_DEPRECATED 146 if (plat_driver_data->interrupt_props == NULL) { 147 /* Interrupt properties array size must be 0 */ 148 assert(plat_driver_data->interrupt_props_num == 0); 149 150 /* The platform should provide a list of secure interrupts */ 151 assert(plat_driver_data->g0_interrupt_array); 152 153 /* 154 * If there are no interrupts of a particular type, then the 155 * number of interrupts of that type should be 0 and vice-versa. 156 */ 157 assert(plat_driver_data->g0_interrupt_array ? 158 plat_driver_data->g0_interrupt_num : 159 plat_driver_data->g0_interrupt_num == 0); 160 } 161 #else 162 assert(plat_driver_data->interrupt_props != NULL); 163 assert(plat_driver_data->interrupt_props_num > 0); 164 #endif 165 166 /* Ensure that this is a GICv2 system */ 167 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 168 gic_version = (gic_version >> PIDR2_ARCH_REV_SHIFT) 169 & PIDR2_ARCH_REV_MASK; 170 171 /* 172 * GICv1 with security extension complies with trusted firmware 173 * GICv2 driver as far as virtualization and few tricky power 174 * features are not used. GICv2 features that are not supported 175 * by GICv1 with Security Extensions are: 176 * - virtual interrupt support. 177 * - wake up events. 178 * - writeable GIC state register (for power sequences) 179 * - interrupt priority drop. 180 * - interrupt signal bypass. 181 */ 182 assert(gic_version == ARCH_REV_GICV2 || gic_version == ARCH_REV_GICV1); 183 184 driver_data = plat_driver_data; 185 186 /* 187 * The GIC driver data is initialized by the primary CPU with caches 188 * enabled. When the secondary CPU boots up, it initializes the 189 * GICC/GICR interface with the caches disabled. Hence flush the 190 * driver_data to ensure coherency. This is not required if the 191 * platform has HW_ASSISTED_COHERENCY enabled. 192 */ 193 #if !HW_ASSISTED_COHERENCY 194 flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data)); 195 flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data)); 196 #endif 197 INFO("ARM GICv2 driver initialized\n"); 198 } 199 200 /****************************************************************************** 201 * This function returns whether FIQ is enabled in the GIC CPU interface. 202 *****************************************************************************/ 203 unsigned int gicv2_is_fiq_enabled(void) 204 { 205 unsigned int gicc_ctlr; 206 207 assert(driver_data); 208 assert(driver_data->gicc_base); 209 210 gicc_ctlr = gicc_read_ctlr(driver_data->gicc_base); 211 return (gicc_ctlr >> FIQ_EN_SHIFT) & 0x1; 212 } 213 214 /******************************************************************************* 215 * This function returns the type of the highest priority pending interrupt at 216 * the GIC cpu interface. The return values can be one of the following : 217 * PENDING_G1_INTID : The interrupt type is non secure Group 1. 218 * 0 - 1019 : The interrupt type is secure Group 0. 219 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 220 * sufficient priority to be signaled 221 ******************************************************************************/ 222 unsigned int gicv2_get_pending_interrupt_type(void) 223 { 224 assert(driver_data); 225 assert(driver_data->gicc_base); 226 227 return gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; 228 } 229 230 /******************************************************************************* 231 * This function returns the id of the highest priority pending interrupt at 232 * the GIC cpu interface. GIC_SPURIOUS_INTERRUPT is returned when there is no 233 * interrupt pending. 234 ******************************************************************************/ 235 unsigned int gicv2_get_pending_interrupt_id(void) 236 { 237 unsigned int id; 238 239 assert(driver_data); 240 assert(driver_data->gicc_base); 241 242 id = gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; 243 244 /* 245 * Find out which non-secure interrupt it is under the assumption that 246 * the GICC_CTLR.AckCtl bit is 0. 247 */ 248 if (id == PENDING_G1_INTID) 249 id = gicc_read_ahppir(driver_data->gicc_base) & INT_ID_MASK; 250 251 return id; 252 } 253 254 /******************************************************************************* 255 * This functions reads the GIC cpu interface Interrupt Acknowledge register 256 * to start handling the pending secure 0 interrupt. It returns the 257 * contents of the IAR. 258 ******************************************************************************/ 259 unsigned int gicv2_acknowledge_interrupt(void) 260 { 261 assert(driver_data); 262 assert(driver_data->gicc_base); 263 264 return gicc_read_IAR(driver_data->gicc_base); 265 } 266 267 /******************************************************************************* 268 * This functions writes the GIC cpu interface End Of Interrupt register with 269 * the passed value to finish handling the active secure group 0 interrupt. 270 ******************************************************************************/ 271 void gicv2_end_of_interrupt(unsigned int id) 272 { 273 assert(driver_data); 274 assert(driver_data->gicc_base); 275 276 gicc_write_EOIR(driver_data->gicc_base, id); 277 } 278 279 /******************************************************************************* 280 * This function returns the type of the interrupt id depending upon the group 281 * this interrupt has been configured under by the interrupt controller i.e. 282 * group0 secure or group1 non secure. It returns zero for Group 0 secure and 283 * one for Group 1 non secure interrupt. 284 ******************************************************************************/ 285 unsigned int gicv2_get_interrupt_group(unsigned int id) 286 { 287 assert(driver_data); 288 assert(driver_data->gicd_base); 289 290 return gicd_get_igroupr(driver_data->gicd_base, id); 291 } 292 293 /******************************************************************************* 294 * This function returns the priority of the interrupt the processor is 295 * currently servicing. 296 ******************************************************************************/ 297 unsigned int gicv2_get_running_priority(void) 298 { 299 assert(driver_data); 300 assert(driver_data->gicc_base); 301 302 return gicc_read_rpr(driver_data->gicc_base); 303 } 304 305 /******************************************************************************* 306 * This function sets the GICv2 target mask pattern for the current PE. The PE 307 * target mask is used to translate linear PE index (returned by platform core 308 * position) to a bit mask used when targeting interrupts to a PE, viz. when 309 * raising SGIs and routing SPIs. 310 ******************************************************************************/ 311 void gicv2_set_pe_target_mask(unsigned int proc_num) 312 { 313 assert(driver_data); 314 assert(driver_data->gicd_base); 315 assert(driver_data->target_masks); 316 assert(proc_num < GICV2_MAX_TARGET_PE); 317 assert(proc_num < driver_data->target_masks_num); 318 319 /* Return if the target mask is already populated */ 320 if (driver_data->target_masks[proc_num]) 321 return; 322 323 /* Read target register corresponding to this CPU */ 324 driver_data->target_masks[proc_num] = 325 gicv2_get_cpuif_id(driver_data->gicd_base); 326 } 327 328 /******************************************************************************* 329 * This function returns the active status of the interrupt (either because the 330 * state is active, or active and pending). 331 ******************************************************************************/ 332 unsigned int gicv2_get_interrupt_active(unsigned int id) 333 { 334 assert(driver_data); 335 assert(driver_data->gicd_base); 336 assert(id <= MAX_SPI_ID); 337 338 return gicd_get_isactiver(driver_data->gicd_base, id); 339 } 340 341 /******************************************************************************* 342 * This function enables the interrupt identified by id. 343 ******************************************************************************/ 344 void gicv2_enable_interrupt(unsigned int id) 345 { 346 assert(driver_data); 347 assert(driver_data->gicd_base); 348 assert(id <= MAX_SPI_ID); 349 350 /* 351 * Ensure that any shared variable updates depending on out of band 352 * interrupt trigger are observed before enabling interrupt. 353 */ 354 dsbishst(); 355 gicd_set_isenabler(driver_data->gicd_base, id); 356 } 357 358 /******************************************************************************* 359 * This function disables the interrupt identified by id. 360 ******************************************************************************/ 361 void gicv2_disable_interrupt(unsigned int id) 362 { 363 assert(driver_data); 364 assert(driver_data->gicd_base); 365 assert(id <= MAX_SPI_ID); 366 367 /* 368 * Disable interrupt, and ensure that any shared variable updates 369 * depending on out of band interrupt trigger are observed afterwards. 370 */ 371 gicd_set_icenabler(driver_data->gicd_base, id); 372 dsbishst(); 373 } 374 375 /******************************************************************************* 376 * This function sets the interrupt priority as supplied for the given interrupt 377 * id. 378 ******************************************************************************/ 379 void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority) 380 { 381 assert(driver_data); 382 assert(driver_data->gicd_base); 383 assert(id <= MAX_SPI_ID); 384 385 gicd_set_ipriorityr(driver_data->gicd_base, id, priority); 386 } 387 388 /******************************************************************************* 389 * This function assigns group for the interrupt identified by id. The group can 390 * be any of GICV2_INTR_GROUP* 391 ******************************************************************************/ 392 void gicv2_set_interrupt_type(unsigned int id, unsigned int type) 393 { 394 assert(driver_data); 395 assert(driver_data->gicd_base); 396 assert(id <= MAX_SPI_ID); 397 398 /* Serialize read-modify-write to Distributor registers */ 399 spin_lock(&gic_lock); 400 switch (type) { 401 case GICV2_INTR_GROUP1: 402 gicd_set_igroupr(driver_data->gicd_base, id); 403 break; 404 case GICV2_INTR_GROUP0: 405 gicd_clr_igroupr(driver_data->gicd_base, id); 406 break; 407 default: 408 assert(0); 409 } 410 spin_unlock(&gic_lock); 411 } 412 413 /******************************************************************************* 414 * This function raises the specified SGI to requested targets. 415 * 416 * The proc_num parameter must be the linear index of the target PE in the 417 * system. 418 ******************************************************************************/ 419 void gicv2_raise_sgi(int sgi_num, int proc_num) 420 { 421 unsigned int sgir_val, target; 422 423 assert(driver_data); 424 assert(proc_num < GICV2_MAX_TARGET_PE); 425 assert(driver_data->gicd_base); 426 427 /* 428 * Target masks array must have been supplied, and the core position 429 * should be valid. 430 */ 431 assert(driver_data->target_masks); 432 assert(proc_num < driver_data->target_masks_num); 433 434 /* Don't raise SGI if the mask hasn't been populated */ 435 target = driver_data->target_masks[proc_num]; 436 assert(target != 0); 437 438 sgir_val = GICV2_SGIR_VALUE(SGIR_TGT_SPECIFIC, target, sgi_num); 439 440 /* 441 * Ensure that any shared variable updates depending on out of band 442 * interrupt trigger are observed before raising SGI. 443 */ 444 dsbishst(); 445 gicd_write_sgir(driver_data->gicd_base, sgir_val); 446 } 447 448 /******************************************************************************* 449 * This function sets the interrupt routing for the given SPI interrupt id. 450 * The interrupt routing is specified in routing mode. The proc_num parameter is 451 * linear index of the PE to target SPI. When proc_num < 0, the SPI may target 452 * all PEs. 453 ******************************************************************************/ 454 void gicv2_set_spi_routing(unsigned int id, int proc_num) 455 { 456 int target; 457 458 assert(driver_data); 459 assert(driver_data->gicd_base); 460 461 assert(id >= MIN_SPI_ID && id <= MAX_SPI_ID); 462 463 /* 464 * Target masks array must have been supplied, and the core position 465 * should be valid. 466 */ 467 assert(driver_data->target_masks); 468 assert(proc_num < GICV2_MAX_TARGET_PE); 469 assert(proc_num < driver_data->target_masks_num); 470 471 if (proc_num < 0) { 472 /* Target all PEs */ 473 target = GIC_TARGET_CPU_MASK; 474 } else { 475 /* Don't route interrupt if the mask hasn't been populated */ 476 target = driver_data->target_masks[proc_num]; 477 assert(target != 0); 478 } 479 480 gicd_set_itargetsr(driver_data->gicd_base, id, target); 481 } 482 483 /******************************************************************************* 484 * This function clears the pending status of an interrupt identified by id. 485 ******************************************************************************/ 486 void gicv2_clear_interrupt_pending(unsigned int id) 487 { 488 assert(driver_data); 489 assert(driver_data->gicd_base); 490 491 /* SGIs can't be cleared pending */ 492 assert(id >= MIN_PPI_ID); 493 494 /* 495 * Clear pending interrupt, and ensure that any shared variable updates 496 * depending on out of band interrupt trigger are observed afterwards. 497 */ 498 gicd_set_icpendr(driver_data->gicd_base, id); 499 dsbishst(); 500 } 501 502 /******************************************************************************* 503 * This function sets the pending status of an interrupt identified by id. 504 ******************************************************************************/ 505 void gicv2_set_interrupt_pending(unsigned int id) 506 { 507 assert(driver_data); 508 assert(driver_data->gicd_base); 509 510 /* SGIs can't be cleared pending */ 511 assert(id >= MIN_PPI_ID); 512 513 /* 514 * Ensure that any shared variable updates depending on out of band 515 * interrupt trigger are observed before setting interrupt pending. 516 */ 517 dsbishst(); 518 gicd_set_ispendr(driver_data->gicd_base, id); 519 } 520 521 /******************************************************************************* 522 * This function sets the PMR register with the supplied value. Returns the 523 * original PMR. 524 ******************************************************************************/ 525 unsigned int gicv2_set_pmr(unsigned int mask) 526 { 527 unsigned int old_mask; 528 529 assert(driver_data); 530 assert(driver_data->gicc_base); 531 532 old_mask = gicc_read_pmr(driver_data->gicc_base); 533 534 /* 535 * Order memory updates w.r.t. PMR write, and ensure they're visible 536 * before potential out of band interrupt trigger because of PMR update. 537 */ 538 dmbishst(); 539 gicc_write_pmr(driver_data->gicc_base, mask); 540 dsbishst(); 541 542 return old_mask; 543 } 544