1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_gic.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <delay_timer.h> 14 #include <dw_ufs.h> 15 #include <errno.h> 16 #include <generic_delay_timer.h> 17 #include <gicv2.h> 18 #include <hi3660.h> 19 #include <mmio.h> 20 #include <platform.h> 21 #include <platform_def.h> 22 #include <string.h> 23 #include <tbbr/tbbr_img_desc.h> 24 #include <ufs.h> 25 26 #include "../../bl1/bl1_private.h" 27 #include "hikey960_def.h" 28 #include "hikey960_private.h" 29 30 enum { 31 BOOT_MODE_RECOVERY = 0, 32 BOOT_MODE_NORMAL, 33 BOOT_MODE_MASK = 1, 34 }; 35 36 /* 37 * Declarations of linker defined symbols which will help us find the layout 38 * of trusted RAM 39 */ 40 41 /* Data structure which holds the extents of the trusted RAM for BL1 */ 42 static meminfo_t bl1_tzram_layout; 43 44 /****************************************************************************** 45 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 46 * interrupts. 47 *****************************************************************************/ 48 const unsigned int g0_interrupt_array[] = { 49 IRQ_SEC_PHY_TIMER, 50 IRQ_SEC_SGI_0 51 }; 52 53 const gicv2_driver_data_t hikey960_gic_data = { 54 .gicd_base = GICD_REG_BASE, 55 .gicc_base = GICC_REG_BASE, 56 .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), 57 .g0_interrupt_array = g0_interrupt_array, 58 }; 59 60 meminfo_t *bl1_plat_sec_mem_layout(void) 61 { 62 return &bl1_tzram_layout; 63 } 64 65 /******************************************************************************* 66 * Function that takes a memory layout into which BL2 has been loaded and 67 * populates a new memory layout for BL2 that ensures that BL1's data sections 68 * resident in secure RAM are not visible to BL2. 69 ******************************************************************************/ 70 void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, 71 meminfo_t *bl2_mem_layout) 72 { 73 74 assert(bl1_mem_layout != NULL); 75 assert(bl2_mem_layout != NULL); 76 77 /* 78 * Cannot remove BL1 RW data from the scope of memory visible to BL2 79 * like arm platforms because they overlap in hikey960 80 */ 81 bl2_mem_layout->total_base = BL2_BASE; 82 bl2_mem_layout->total_size = NS_BL1U_LIMIT - BL2_BASE; 83 84 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); 85 } 86 87 /* 88 * Perform any BL1 specific platform actions. 89 */ 90 void bl1_early_platform_setup(void) 91 { 92 unsigned int id, uart_base; 93 94 generic_delay_timer_init(); 95 hikey960_read_boardid(&id); 96 if (id == 5300) 97 uart_base = PL011_UART5_BASE; 98 else 99 uart_base = PL011_UART6_BASE; 100 /* Initialize the console to provide early debug support */ 101 console_init(uart_base, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 102 103 /* Allow BL1 to see the whole Trusted RAM */ 104 bl1_tzram_layout.total_base = BL1_RW_BASE; 105 bl1_tzram_layout.total_size = BL1_RW_SIZE; 106 107 INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 108 BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */ 109 } 110 111 /* 112 * Perform the very early platform specific architecture setup here. At the 113 * moment this only does basic initialization. Later architectural setup 114 * (bl1_arch_setup()) does not do anything platform specific. 115 */ 116 void bl1_plat_arch_setup(void) 117 { 118 hikey960_init_mmu_el3(bl1_tzram_layout.total_base, 119 bl1_tzram_layout.total_size, 120 BL1_RO_BASE, 121 BL1_RO_LIMIT, 122 BL_COHERENT_RAM_BASE, 123 BL_COHERENT_RAM_END); 124 } 125 126 static void hikey960_ufs_reset(void) 127 { 128 unsigned int data, mask; 129 130 mmio_write_32(CRG_PERDIS7_REG, 1 << 14); 131 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 132 do { 133 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 134 } while (data & BIT_SYSCTRL_REF_CLOCK_EN); 135 /* use abb clk */ 136 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); 137 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); 138 mmio_write_32(PCTRL_PERI_CTRL3_REG, (1 << 0) | (1 << 16)); 139 mdelay(1); 140 mmio_write_32(CRG_PEREN7_REG, 1 << 14); 141 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 142 143 mmio_write_32(CRG_PERRSTEN3_REG, PERI_UFS_BIT); 144 do { 145 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 146 } while ((data & PERI_UFS_BIT) == 0); 147 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); 148 mdelay(1); 149 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); 150 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 151 MASK_UFS_DEVICE_RESET); 152 /* clear SC_DIV_UFS_PERIBUS */ 153 mask = SC_DIV_UFS_PERIBUS << 16; 154 mmio_write_32(CRG_CLKDIV17_REG, mask); 155 /* set SC_DIV_UFSPHY_CFG(3) */ 156 mask = SC_DIV_UFSPHY_CFG_MASK << 16; 157 data = SC_DIV_UFSPHY_CFG(3); 158 mmio_write_32(CRG_CLKDIV16_REG, mask | data); 159 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 160 data &= ~MASK_SYSCTRL_CFG_CLOCK_FREQ; 161 data |= 0x39; 162 mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data); 163 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); 164 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, 165 MASK_UFS_CLK_GATE_BYPASS); 166 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); 167 168 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); 169 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); 170 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); 171 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); 172 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_ARST_UFS_BIT); 173 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); 174 mdelay(1); 175 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 176 MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET); 177 mdelay(20); 178 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 179 0x03300330); 180 181 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_UFS_BIT); 182 do { 183 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 184 } while (data & PERI_UFS_BIT); 185 } 186 187 static void hikey960_ufs_init(void) 188 { 189 dw_ufs_params_t ufs_params; 190 191 memset(&ufs_params, 0, sizeof(ufs_params)); 192 ufs_params.reg_base = UFS_REG_BASE; 193 ufs_params.desc_base = HIKEY960_UFS_DESC_BASE; 194 ufs_params.desc_size = HIKEY960_UFS_DESC_SIZE; 195 196 if ((ufs_params.flags & UFS_FLAGS_SKIPINIT) == 0) 197 hikey960_ufs_reset(); 198 dw_ufs_init(&ufs_params); 199 } 200 201 /* 202 * Function which will perform any remaining platform-specific setup that can 203 * occur after the MMU and data cache have been enabled. 204 */ 205 void bl1_platform_setup(void) 206 { 207 hikey960_clk_init(); 208 hikey960_pmu_init(); 209 hikey960_regulator_enable(); 210 hikey960_tzc_init(); 211 hikey960_peri_init(); 212 hikey960_ufs_init(); 213 hikey960_pinmux_init(); 214 hikey960_io_setup(); 215 } 216 217 /* 218 * The following function checks if Firmware update is needed, 219 * by checking if TOC in FIP image is valid or not. 220 */ 221 unsigned int bl1_plat_get_next_image_id(void) 222 { 223 unsigned int mode, ret; 224 225 mode = mmio_read_32(SCTRL_BAK_DATA0_REG); 226 switch (mode & BOOT_MODE_MASK) { 227 case BOOT_MODE_RECOVERY: 228 ret = NS_BL1U_IMAGE_ID; 229 break; 230 default: 231 WARN("Invalid boot mode is found:%d\n", mode); 232 panic(); 233 } 234 return ret; 235 } 236 237 image_desc_t *bl1_plat_get_image_desc(unsigned int image_id) 238 { 239 unsigned int index = 0; 240 241 while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) { 242 if (bl1_tbbr_image_descs[index].image_id == image_id) 243 return &bl1_tbbr_image_descs[index]; 244 index++; 245 } 246 247 return NULL; 248 } 249 250 void bl1_plat_set_ep_info(unsigned int image_id, 251 entry_point_info_t *ep_info) 252 { 253 unsigned int data = 0; 254 uintptr_t tmp = HIKEY960_NS_TMP_OFFSET; 255 256 if (image_id != NS_BL1U_IMAGE_ID) 257 panic(); 258 /* Copy NS BL1U from 0x1AC1_8000 to 0x1AC9_8000 */ 259 memcpy((void *)tmp, (void *)HIKEY960_NS_IMAGE_OFFSET, 260 NS_BL1U_SIZE); 261 memcpy((void *)NS_BL1U_BASE, (void *)tmp, NS_BL1U_SIZE); 262 inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE); 263 /* Initialize the GIC driver, cpu and distributor interfaces */ 264 gicv2_driver_init(&hikey960_gic_data); 265 gicv2_distif_init(); 266 gicv2_pcpu_distif_init(); 267 gicv2_cpuif_enable(); 268 /* CNTFRQ is read-only in EL1 */ 269 write_cntfrq_el0(plat_get_syscnt_freq2()); 270 data = read_cpacr_el1(); 271 do { 272 data |= 3 << 20; 273 write_cpacr_el1(data); 274 data = read_cpacr_el1(); 275 } while ((data & (3 << 20)) != (3 << 20)); 276 INFO("cpacr_el1:0x%x\n", data); 277 278 ep_info->args.arg0 = 0xffff & read_mpidr(); 279 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 280 DISABLE_ALL_EXCEPTIONS); 281 } 282