1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <cassert.h> 12 #include <common_def.h> 13 #include <sys/types.h> 14 #include <utils.h> 15 #include <utils_def.h> 16 #include <xlat_tables_v2.h> 17 #include "../xlat_tables_private.h" 18 19 unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr) 20 { 21 /* Physical address can't exceed 48 bits */ 22 assert((max_addr & ADDR_MASK_48_TO_63) == 0); 23 24 /* 48 bits address */ 25 if (max_addr & ADDR_MASK_44_TO_47) 26 return TCR_PS_BITS_256TB; 27 28 /* 44 bits address */ 29 if (max_addr & ADDR_MASK_42_TO_43) 30 return TCR_PS_BITS_16TB; 31 32 /* 42 bits address */ 33 if (max_addr & ADDR_MASK_40_TO_41) 34 return TCR_PS_BITS_4TB; 35 36 /* 40 bits address */ 37 if (max_addr & ADDR_MASK_36_TO_39) 38 return TCR_PS_BITS_1TB; 39 40 /* 36 bits address */ 41 if (max_addr & ADDR_MASK_32_TO_35) 42 return TCR_PS_BITS_64GB; 43 44 return TCR_PS_BITS_4GB; 45 } 46 47 #if ENABLE_ASSERTIONS 48 /* Physical Address ranges supported in the AArch64 Memory Model */ 49 static const unsigned int pa_range_bits_arr[] = { 50 PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100, 51 PARANGE_0101, 52 #if ARM_ARCH_AT_LEAST(8, 2) 53 PARANGE_0110, 54 #endif 55 }; 56 57 unsigned long long xlat_arch_get_max_supported_pa(void) 58 { 59 u_register_t pa_range = read_id_aa64mmfr0_el1() & 60 ID_AA64MMFR0_EL1_PARANGE_MASK; 61 62 /* All other values are reserved */ 63 assert(pa_range < ARRAY_SIZE(pa_range_bits_arr)); 64 65 return (1ull << pa_range_bits_arr[pa_range]) - 1ull; 66 } 67 #endif /* ENABLE_ASSERTIONS*/ 68 69 int is_mmu_enabled_ctx(const xlat_ctx_t *ctx) 70 { 71 if (ctx->xlat_regime == EL1_EL0_REGIME) { 72 assert(xlat_arch_current_el() >= 1); 73 return (read_sctlr_el1() & SCTLR_M_BIT) != 0; 74 } else { 75 assert(ctx->xlat_regime == EL3_REGIME); 76 assert(xlat_arch_current_el() >= 3); 77 return (read_sctlr_el3() & SCTLR_M_BIT) != 0; 78 } 79 } 80 81 82 void xlat_arch_tlbi_va(uintptr_t va) 83 { 84 #if IMAGE_EL == 1 85 assert(IS_IN_EL(1)); 86 xlat_arch_tlbi_va_regime(va, EL1_EL0_REGIME); 87 #elif IMAGE_EL == 3 88 assert(IS_IN_EL(3)); 89 xlat_arch_tlbi_va_regime(va, EL3_REGIME); 90 #endif 91 } 92 93 void xlat_arch_tlbi_va_regime(uintptr_t va, xlat_regime_t xlat_regime) 94 { 95 /* 96 * Ensure the translation table write has drained into memory before 97 * invalidating the TLB entry. 98 */ 99 dsbishst(); 100 101 /* 102 * This function only supports invalidation of TLB entries for the EL3 103 * and EL1&0 translation regimes. 104 * 105 * Also, it is architecturally UNDEFINED to invalidate TLBs of a higher 106 * exception level (see section D4.9.2 of the ARM ARM rev B.a). 107 */ 108 if (xlat_regime == EL1_EL0_REGIME) { 109 assert(xlat_arch_current_el() >= 1); 110 tlbivaae1is(TLBI_ADDR(va)); 111 } else { 112 assert(xlat_regime == EL3_REGIME); 113 assert(xlat_arch_current_el() >= 3); 114 tlbivae3is(TLBI_ADDR(va)); 115 } 116 } 117 118 void xlat_arch_tlbi_va_sync(void) 119 { 120 /* 121 * A TLB maintenance instruction can complete at any time after 122 * it is issued, but is only guaranteed to be complete after the 123 * execution of DSB by the PE that executed the TLB maintenance 124 * instruction. After the TLB invalidate instruction is 125 * complete, no new memory accesses using the invalidated TLB 126 * entries will be observed by any observer of the system 127 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 128 * "Ordering and completion of TLB maintenance instructions". 129 */ 130 dsbish(); 131 132 /* 133 * The effects of a completed TLB maintenance instruction are 134 * only guaranteed to be visible on the PE that executed the 135 * instruction after the execution of an ISB instruction by the 136 * PE that executed the TLB maintenance instruction. 137 */ 138 isb(); 139 } 140 141 int xlat_arch_current_el(void) 142 { 143 int el = GET_EL(read_CurrentEl()); 144 145 assert(el > 0); 146 147 return el; 148 } 149 150 /******************************************************************************* 151 * Macro generating the code for the function enabling the MMU in the given 152 * exception level, assuming that the pagetables have already been created. 153 * 154 * _el: Exception level at which the function will run 155 * _tlbi_fct: Function to invalidate the TLBs at the current 156 * exception level 157 ******************************************************************************/ 158 #define DEFINE_ENABLE_MMU_EL(_el, _tlbi_fct) \ 159 static void enable_mmu_internal_el##_el(int flags, \ 160 uint64_t mair, \ 161 uint64_t tcr, \ 162 uint64_t ttbr) \ 163 { \ 164 uint32_t sctlr = read_sctlr_el##_el(); \ 165 assert((sctlr & SCTLR_M_BIT) == 0); \ 166 \ 167 /* Invalidate TLBs at the current exception level */ \ 168 _tlbi_fct(); \ 169 \ 170 write_mair_el##_el(mair); \ 171 write_tcr_el##_el(tcr); \ 172 \ 173 /* Set TTBR bits as well */ \ 174 if (ARM_ARCH_AT_LEAST(8, 2)) { \ 175 /* Enable CnP bit so as to share page tables */ \ 176 /* with all PEs. This is mandatory for */ \ 177 /* ARMv8.2 implementations. */ \ 178 ttbr |= TTBR_CNP_BIT; \ 179 } \ 180 write_ttbr0_el##_el(ttbr); \ 181 \ 182 /* Ensure all translation table writes have drained */ \ 183 /* into memory, the TLB invalidation is complete, */ \ 184 /* and translation register writes are committed */ \ 185 /* before enabling the MMU */ \ 186 dsbish(); \ 187 isb(); \ 188 \ 189 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \ 190 if (flags & DISABLE_DCACHE) \ 191 sctlr &= ~SCTLR_C_BIT; \ 192 else \ 193 sctlr |= SCTLR_C_BIT; \ 194 \ 195 write_sctlr_el##_el(sctlr); \ 196 \ 197 /* Ensure the MMU enable takes effect immediately */ \ 198 isb(); \ 199 } 200 201 /* Define EL1 and EL3 variants of the function enabling the MMU */ 202 #if IMAGE_EL == 1 203 DEFINE_ENABLE_MMU_EL(1, tlbivmalle1) 204 #elif IMAGE_EL == 3 205 DEFINE_ENABLE_MMU_EL(3, tlbialle3) 206 #endif 207 208 void enable_mmu_arch(unsigned int flags, 209 uint64_t *base_table, 210 unsigned long long max_pa, 211 uintptr_t max_va) 212 { 213 uint64_t mair, ttbr, tcr; 214 215 /* Set attributes in the right indices of the MAIR. */ 216 mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 217 mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX); 218 mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX); 219 220 ttbr = (uint64_t) base_table; 221 222 /* 223 * Set TCR bits as well. 224 */ 225 226 /* 227 * Limit the input address ranges and memory region sizes translated 228 * using TTBR0 to the given virtual address space size. 229 */ 230 assert(max_va < UINTPTR_MAX); 231 uintptr_t virtual_addr_space_size = max_va + 1; 232 assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); 233 /* 234 * __builtin_ctzll(0) is undefined but here we are guaranteed that 235 * virtual_addr_space_size is in the range [1,UINTPTR_MAX]. 236 */ 237 tcr = 64 - __builtin_ctzll(virtual_addr_space_size); 238 239 /* 240 * Set the cacheability and shareability attributes for memory 241 * associated with translation table walks. 242 */ 243 if (flags & XLAT_TABLE_NC) { 244 /* Inner & outer non-cacheable non-shareable. */ 245 tcr |= TCR_SH_NON_SHAREABLE | 246 TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC; 247 } else { 248 /* Inner & outer WBWA & shareable. */ 249 tcr |= TCR_SH_INNER_SHAREABLE | 250 TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA; 251 } 252 253 /* 254 * It is safer to restrict the max physical address accessible by the 255 * hardware as much as possible. 256 */ 257 unsigned long long tcr_ps_bits = tcr_physical_addr_size_bits(max_pa); 258 259 #if IMAGE_EL == 1 260 assert(IS_IN_EL(1)); 261 /* 262 * TCR_EL1.EPD1: Disable translation table walk for addresses that are 263 * translated using TTBR1_EL1. 264 */ 265 tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT); 266 enable_mmu_internal_el1(flags, mair, tcr, ttbr); 267 #elif IMAGE_EL == 3 268 assert(IS_IN_EL(3)); 269 tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT); 270 enable_mmu_internal_el3(flags, mair, tcr, ttbr); 271 #endif 272 } 273