1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_config.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <errno.h> 12 #include <gicv3.h> 13 #include <mmio.h> 14 #include <plat_arm.h> 15 #include <platform.h> 16 #include <psci.h> 17 #include <spe.h> 18 #include <v2m_def.h> 19 #include "drivers/pwrc/fvp_pwrc.h" 20 #include "fvp_def.h" 21 #include "fvp_private.h" 22 23 24 #if ARM_RECOM_STATE_ID_ENC 25 /* 26 * The table storing the valid idle power states. Ensure that the 27 * array entries are populated in ascending order of state-id to 28 * enable us to use binary search during power state validation. 29 * The table must be terminated by a NULL entry. 30 */ 31 const unsigned int arm_pm_idle_states[] = { 32 /* State-id - 0x01 */ 33 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET, 34 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), 35 /* State-id - 0x02 */ 36 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, 37 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), 38 /* State-id - 0x22 */ 39 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 40 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), 41 /* State-id - 0x222 */ 42 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 43 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN), 44 0, 45 }; 46 #endif 47 48 /******************************************************************************* 49 * Function which implements the common FVP specific operations to power down a 50 * cluster in response to a CPU_OFF or CPU_SUSPEND request. 51 ******************************************************************************/ 52 static void fvp_cluster_pwrdwn_common(void) 53 { 54 uint64_t mpidr = read_mpidr_el1(); 55 56 #if ENABLE_SPE_FOR_LOWER_ELS 57 /* 58 * On power down we need to disable statistical profiling extensions 59 * before exiting coherency. 60 */ 61 spe_disable(); 62 #endif 63 64 /* Disable coherency if this cluster is to be turned off */ 65 fvp_interconnect_disable(); 66 67 /* Program the power controller to turn the cluster off */ 68 fvp_pwrc_write_pcoffr(mpidr); 69 } 70 71 /* 72 * Empty implementation of these hooks avoid setting the GICR_WAKER.Sleep bit 73 * on ARM GICv3 implementations on FVP. This is required, because FVP does not 74 * support SYSTEM_SUSPEND and it is `faked` in firmware. Hence, for wake up 75 * from `fake` system suspend the GIC must not be powered off. 76 */ 77 void arm_gicv3_distif_pre_save(unsigned int proc_num) 78 {} 79 80 void arm_gicv3_distif_post_restore(unsigned int proc_num) 81 {} 82 83 static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state) 84 { 85 unsigned long mpidr; 86 87 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 88 ARM_LOCAL_STATE_OFF); 89 90 /* Get the mpidr for this cpu */ 91 mpidr = read_mpidr_el1(); 92 93 /* Perform the common cluster specific operations */ 94 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 95 ARM_LOCAL_STATE_OFF) { 96 /* 97 * This CPU might have woken up whilst the cluster was 98 * attempting to power down. In this case the FVP power 99 * controller will have a pending cluster power off request 100 * which needs to be cleared by writing to the PPONR register. 101 * This prevents the power controller from interpreting a 102 * subsequent entry of this cpu into a simple wfi as a power 103 * down request. 104 */ 105 fvp_pwrc_write_pponr(mpidr); 106 107 /* Enable coherency if this cluster was off */ 108 fvp_interconnect_enable(); 109 } 110 /* Perform the common system specific operations */ 111 if (target_state->pwr_domain_state[ARM_PWR_LVL2] == 112 ARM_LOCAL_STATE_OFF) 113 arm_system_pwr_domain_resume(); 114 115 /* 116 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere 117 * with a cpu power down unless the bit is set again 118 */ 119 fvp_pwrc_clr_wen(mpidr); 120 } 121 122 123 /******************************************************************************* 124 * FVP handler called when a CPU is about to enter standby. 125 ******************************************************************************/ 126 void fvp_cpu_standby(plat_local_state_t cpu_state) 127 { 128 129 assert(cpu_state == ARM_LOCAL_STATE_RET); 130 131 /* 132 * Enter standby state 133 * dsb is good practice before using wfi to enter low power states 134 */ 135 dsb(); 136 wfi(); 137 } 138 139 /******************************************************************************* 140 * FVP handler called when a power domain is about to be turned on. The 141 * mpidr determines the CPU to be turned on. 142 ******************************************************************************/ 143 int fvp_pwr_domain_on(u_register_t mpidr) 144 { 145 int rc = PSCI_E_SUCCESS; 146 unsigned int psysr; 147 148 /* 149 * Ensure that we do not cancel an inflight power off request for the 150 * target cpu. That would leave it in a zombie wfi. Wait for it to power 151 * off and then program the power controller to turn that CPU on. 152 */ 153 do { 154 psysr = fvp_pwrc_read_psysr(mpidr); 155 } while (psysr & PSYSR_AFF_L0); 156 157 fvp_pwrc_write_pponr(mpidr); 158 return rc; 159 } 160 161 /******************************************************************************* 162 * FVP handler called when a power domain is about to be turned off. The 163 * target_state encodes the power state that each level should transition to. 164 ******************************************************************************/ 165 void fvp_pwr_domain_off(const psci_power_state_t *target_state) 166 { 167 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 168 ARM_LOCAL_STATE_OFF); 169 170 /* 171 * If execution reaches this stage then this power domain will be 172 * suspended. Perform at least the cpu specific actions followed 173 * by the cluster specific operations if applicable. 174 */ 175 176 /* Prevent interrupts from spuriously waking up this cpu */ 177 plat_arm_gic_cpuif_disable(); 178 179 /* Turn redistributor off */ 180 plat_arm_gic_redistif_off(); 181 182 /* Program the power controller to power off this cpu. */ 183 fvp_pwrc_write_ppoffr(read_mpidr_el1()); 184 185 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 186 ARM_LOCAL_STATE_OFF) 187 fvp_cluster_pwrdwn_common(); 188 189 } 190 191 /******************************************************************************* 192 * FVP handler called when a power domain is about to be suspended. The 193 * target_state encodes the power state that each level should transition to. 194 ******************************************************************************/ 195 void fvp_pwr_domain_suspend(const psci_power_state_t *target_state) 196 { 197 unsigned long mpidr; 198 199 /* 200 * FVP has retention only at cpu level. Just return 201 * as nothing is to be done for retention. 202 */ 203 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 204 ARM_LOCAL_STATE_RET) 205 return; 206 207 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 208 ARM_LOCAL_STATE_OFF); 209 210 /* Get the mpidr for this cpu */ 211 mpidr = read_mpidr_el1(); 212 213 /* Program the power controller to enable wakeup interrupts. */ 214 fvp_pwrc_set_wen(mpidr); 215 216 /* Prevent interrupts from spuriously waking up this cpu */ 217 plat_arm_gic_cpuif_disable(); 218 219 /* 220 * The Redistributor is not powered off as it can potentially prevent 221 * wake up events reaching the CPUIF and/or might lead to losing 222 * register context. 223 */ 224 225 /* Perform the common cluster specific operations */ 226 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 227 ARM_LOCAL_STATE_OFF) 228 fvp_cluster_pwrdwn_common(); 229 230 /* Perform the common system specific operations */ 231 if (target_state->pwr_domain_state[ARM_PWR_LVL2] == 232 ARM_LOCAL_STATE_OFF) 233 arm_system_pwr_domain_save(); 234 235 /* Program the power controller to power off this cpu. */ 236 fvp_pwrc_write_ppoffr(read_mpidr_el1()); 237 } 238 239 /******************************************************************************* 240 * FVP handler called when a power domain has just been powered on after 241 * being turned off earlier. The target_state encodes the low power state that 242 * each level has woken up from. 243 ******************************************************************************/ 244 void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) 245 { 246 fvp_power_domain_on_finish_common(target_state); 247 248 /* Enable the gic cpu interface */ 249 plat_arm_gic_pcpu_init(); 250 251 /* Program the gic per-cpu distributor or re-distributor interface */ 252 plat_arm_gic_cpuif_enable(); 253 } 254 255 /******************************************************************************* 256 * FVP handler called when a power domain has just been powered on after 257 * having been suspended earlier. The target_state encodes the low power state 258 * that each level has woken up from. 259 * TODO: At the moment we reuse the on finisher and reinitialize the secure 260 * context. Need to implement a separate suspend finisher. 261 ******************************************************************************/ 262 void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 263 { 264 /* 265 * Nothing to be done on waking up from retention from CPU level. 266 */ 267 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 268 ARM_LOCAL_STATE_RET) 269 return; 270 271 fvp_power_domain_on_finish_common(target_state); 272 273 /* Enable the gic cpu interface */ 274 plat_arm_gic_cpuif_enable(); 275 } 276 277 /******************************************************************************* 278 * FVP handlers to shutdown/reboot the system 279 ******************************************************************************/ 280 static void __dead2 fvp_system_off(void) 281 { 282 /* Write the System Configuration Control Register */ 283 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 284 V2M_CFGCTRL_START | 285 V2M_CFGCTRL_RW | 286 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN)); 287 wfi(); 288 ERROR("FVP System Off: operation not handled.\n"); 289 panic(); 290 } 291 292 static void __dead2 fvp_system_reset(void) 293 { 294 /* Write the System Configuration Control Register */ 295 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 296 V2M_CFGCTRL_START | 297 V2M_CFGCTRL_RW | 298 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT)); 299 wfi(); 300 ERROR("FVP System Reset: operation not handled.\n"); 301 panic(); 302 } 303 304 static int fvp_node_hw_state(u_register_t target_cpu, 305 unsigned int power_level) 306 { 307 unsigned int psysr; 308 int ret; 309 310 /* 311 * The format of 'power_level' is implementation-defined, but 0 must 312 * mean a CPU. We also allow 1 to denote the cluster 313 */ 314 if (power_level != ARM_PWR_LVL0 && power_level != ARM_PWR_LVL1) 315 return PSCI_E_INVALID_PARAMS; 316 317 /* 318 * Read the status of the given MPDIR from FVP power controller. The 319 * power controller only gives us on/off status, so map that to expected 320 * return values of the PSCI call 321 */ 322 psysr = fvp_pwrc_read_psysr(target_cpu); 323 if (psysr == PSYSR_INVALID) 324 return PSCI_E_INVALID_PARAMS; 325 326 switch (power_level) { 327 case ARM_PWR_LVL0: 328 ret = (psysr & PSYSR_AFF_L0) ? HW_ON : HW_OFF; 329 break; 330 case ARM_PWR_LVL1: 331 ret = (psysr & PSYSR_AFF_L1) ? HW_ON : HW_OFF; 332 break; 333 } 334 335 return ret; 336 } 337 338 /* 339 * The FVP doesn't truly support power management at SYSTEM power domain. The 340 * SYSTEM_SUSPEND will be down-graded to the cluster level within the platform 341 * layer. The `fake` SYSTEM_SUSPEND allows us to validate some of the driver 342 * save and restore sequences on FVP. 343 */ 344 void fvp_get_sys_suspend_power_state(psci_power_state_t *req_state) 345 { 346 unsigned int i; 347 348 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) 349 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; 350 } 351 352 /******************************************************************************* 353 * Handler to filter PSCI requests. 354 ******************************************************************************/ 355 /* 356 * The system power domain suspend is only supported only via 357 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain 358 * will be downgraded to the lower level. 359 */ 360 static int fvp_validate_power_state(unsigned int power_state, 361 psci_power_state_t *req_state) 362 { 363 int rc; 364 rc = arm_validate_power_state(power_state, req_state); 365 366 /* 367 * Ensure that the system power domain level is never suspended 368 * via PSCI CPU SUSPEND API. Currently system suspend is only 369 * supported via PSCI SYSTEM SUSPEND API. 370 */ 371 req_state->pwr_domain_state[ARM_PWR_LVL2] = ARM_LOCAL_STATE_RUN; 372 return rc; 373 } 374 375 /* 376 * Custom `translate_power_state_by_mpidr` handler for FVP. Unlike in the 377 * `fvp_validate_power_state`, we do not downgrade the system power 378 * domain level request in `power_state` as it will be used to query the 379 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level. 380 */ 381 static int fvp_translate_power_state_by_mpidr(u_register_t mpidr, 382 unsigned int power_state, 383 psci_power_state_t *output_state) 384 { 385 return arm_validate_power_state(power_state, output_state); 386 } 387 388 /******************************************************************************* 389 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard 390 * platform layer will take care of registering the handlers with PSCI. 391 ******************************************************************************/ 392 plat_psci_ops_t plat_arm_psci_pm_ops = { 393 .cpu_standby = fvp_cpu_standby, 394 .pwr_domain_on = fvp_pwr_domain_on, 395 .pwr_domain_off = fvp_pwr_domain_off, 396 .pwr_domain_suspend = fvp_pwr_domain_suspend, 397 .pwr_domain_on_finish = fvp_pwr_domain_on_finish, 398 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish, 399 .system_off = fvp_system_off, 400 .system_reset = fvp_system_reset, 401 .validate_power_state = fvp_validate_power_state, 402 .validate_ns_entrypoint = arm_validate_psci_entrypoint, 403 .translate_power_state_by_mpidr = fvp_translate_power_state_by_mpidr, 404 .get_node_hw_state = fvp_node_hw_state, 405 .get_sys_suspend_power_state = fvp_get_sys_suspend_power_state, 406 /* 407 * mem_protect is not supported in RESET_TO_BL31 and RESET_TO_SP_MIN, 408 * as that would require mapping in all of NS DRAM into BL31 or BL32. 409 */ 410 #if !RESET_TO_BL31 && !RESET_TO_SP_MIN 411 .mem_protect_chk = arm_psci_mem_protect_chk, 412 .read_mem_protect = arm_psci_read_mem_protect, 413 .write_mem_protect = arm_nor_psci_write_mem_protect, 414 #endif 415 }; 416