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Searched refs:REG32 (Results 1 – 25 of 183) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DregTSP.h278 } REG32; typedef
292 typedef REG32 REG_PidFlt;
336 REG32 Ctrl;
364 REG32 Match[TSP_FILTER_DEPTH/sizeof(MS_U32)];
366 REG32 Mask[TSP_FILTER_DEPTH/sizeof(MS_U32)];
368 REG32 BufStart;
371 REG32 BufEnd;
373 REG32 BufRead;
375 REG32 BufWrite;
377 REG32 BufCur;
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DregTSP.h297 } REG32; typedef
311 typedef REG32 REG_PidFlt;
355 REG32 Ctrl;
386 REG32 Match[TSP_FILTER_DEPTH/sizeof(MS_U32)];
388 REG32 Mask[TSP_FILTER_DEPTH/sizeof(MS_U32)];
390 REG32 BufStart;
393 REG32 BufEnd;
395 REG32 BufRead;
397 REG32 BufWrite;
399 REG32 BufCur;
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DregTSP.h301 } REG32; typedef
315 typedef REG32 REG_PidFlt;
360 REG32 Ctrl;
388 REG32 Match[TSP_FILTER_DEPTH/sizeof(MS_U32)];
390 REG32 Mask[TSP_FILTER_DEPTH/sizeof(MS_U32)];
392 REG32 BufStart;
395 REG32 BufEnd;
397 REG32 BufRead;
399 REG32 BufWrite;
401 REG32 BufCur;
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DregTSP.h301 } REG32; typedef
315 typedef REG32 REG_PidFlt;
360 REG32 Ctrl;
388 REG32 Match[TSP_FILTER_DEPTH/sizeof(MS_U32)];
390 REG32 Mask[TSP_FILTER_DEPTH/sizeof(MS_U32)];
392 REG32 BufStart;
395 REG32 BufEnd;
397 REG32 BufRead;
399 REG32 BufWrite;
401 REG32 BufCur;
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DregTSP.h287 } REG32; typedef
301 typedef REG32 REG_PidFlt;
345 REG32 Ctrl;
373 REG32 Match[TSP_FILTER_DEPTH/sizeof(MS_U32)];
375 REG32 Mask[TSP_FILTER_DEPTH/sizeof(MS_U32)];
377 REG32 BufStart;
380 REG32 BufEnd;
382 REG32 BufRead;
384 REG32 BufWrite;
386 REG32 BufCur;
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/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DregTSP.h308 } REG32; typedef
322 typedef REG32 REG_PidFlt;
367 REG32 Ctrl;
395 REG32 Match[TSP_FILTER_DEPTH/sizeof(MS_U32)];
397 REG32 Mask[TSP_FILTER_DEPTH/sizeof(MS_U32)];
399 REG32 BufStart;
402 REG32 BufEnd;
404 REG32 BufRead;
406 REG32 BufWrite;
408 REG32 BufCur;
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/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DregTSP.h308 } REG32; typedef
322 typedef REG32 REG_PidFlt;
367 REG32 Ctrl;
395 REG32 Match[TSP_FILTER_DEPTH/sizeof(MS_U32)];
397 REG32 Mask[TSP_FILTER_DEPTH/sizeof(MS_U32)];
399 REG32 BufStart;
402 REG32 BufEnd;
404 REG32 BufRead;
406 REG32 BufWrite;
408 REG32 BufCur;
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/utopia/UTPA2-700.0.x/modules/dmx/hal/messi/tsp/
H A DregTSP.h247 } REG32; typedef
261 typedef REG32 REG_PidFlt;
293 REG32 Ctrl;
330 REG32 Match[TSP_FILTER_DEPTH/sizeof(MS_U32)];
331 REG32 Mask[TSP_FILTER_DEPTH/sizeof(MS_U32)];
332 REG32 BufStart;
334 REG32 BufEnd;
335 REG32 BufRead;
336 REG32 BufWrite;
337 REG32 BufCur;
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/mainz/tsp/
H A DregTSP.h247 } REG32; typedef
261 typedef REG32 REG_PidFlt;
293 REG32 Ctrl;
330 REG32 Match[TSP_FILTER_DEPTH/sizeof(MS_U32)];
331 REG32 Mask[TSP_FILTER_DEPTH/sizeof(MS_U32)];
332 REG32 BufStart;
334 REG32 BufEnd;
335 REG32 BufRead;
336 REG32 BufWrite;
337 REG32 BufCur;
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/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/
H A DregTSP.h282 } REG32; typedef
296 typedef REG32 REG_PidFlt;
340 REG32 Ctrl;
372 REG32 Match[TSP_FILTER_DEPTH/sizeof(MS_U32)];
374 REG32 Mask[TSP_FILTER_DEPTH/sizeof(MS_U32)];
376 REG32 BufStart;
379 REG32 BufEnd;
381 REG32 BufRead;
383 REG32 BufWrite;
385 REG32 BufCur;
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/utopia/UTPA2-700.0.x/modules/dmx/hal/mooney/tsp/
H A DregTSP.h240 } REG32; typedef
254 typedef REG32 REG_PidFlt;
286 REG32 Ctrl;
323 REG32 Match[TSP_FILTER_DEPTH/sizeof(MS_U32)];
324 REG32 Mask[TSP_FILTER_DEPTH/sizeof(MS_U32)];
325 REG32 BufStart;
327 REG32 BufEnd;
328 REG32 BufRead;
329 REG32 BufWrite;
330 REG32 BufCur;
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DregTSP.h9 } REG32; typedef
343 REG32 Str2mi_head2pvr1; // 0xbf802a04 0x01
346 …REG32 Str2mi_mid2pvr1; // 0xbf802a0c 0x03 ,wpt…
349 REG32 Str2mi_tail2pvr1; // 0xbf802a14 0x05
352 REG32 Pcr_L; // 0xbf802a1c 0x07
355 REG32 Pcr_H; // 0xbf802a24 0x09
361 REG32 _xbf202a2c; // 0xbf802a30 0x0c
363 REG32 PVR2_Config; // 0xbf802a38 0x0e
396 REG32 PVR2_LPCR1; // 0xbf802a40 0x10
399 REG32 Str2mi_head1_pvr2; // 0xbf802a48 0x12
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DregTSP.h9 } REG32; typedef
378 REG32 Str2mi_head2pvr1; // 0xbf802a04 0x01
381 …REG32 Str2mi_mid2pvr1; // 0xbf802a0c 0x03 ,wpt…
384 REG32 Str2mi_tail2pvr1; // 0xbf802a14 0x05
387 REG32 Pcr_L; // 0xbf802a1c 0x07
390 REG32 Pcr_H; // 0xbf802a24 0x09
396 REG32 _xbf202a2c; // 0xbf802a30 0x0c
398 REG32 PVR2_Config; // 0xbf802a38 0x0e
431 REG32 PVR2_LPCR1; // 0xbf802a40 0x10
434 REG32 Str2mi_head1_pvr2; // 0xbf802a48 0x12
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/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h9 } REG32; typedef
380 REG32 Str2mi_head2pvr1; // 0xbf802a04 0x01
383 …REG32 Str2mi_mid2pvr1; // 0xbf802a0c 0x03 ,wpt…
386 REG32 Str2mi_tail2pvr1; // 0xbf802a14 0x05
389 REG32 Pcr_L; // 0xbf802a1c 0x07
392 REG32 Pcr_H; // 0xbf802a24 0x09
398 REG32 _xbf202a2c; // 0xbf802a30 0x0c
400 REG32 PVR2_Config; // 0xbf802a38 0x0e
433 REG32 PVR2_LPCR1; // 0xbf802a40 0x10
436 REG32 Str2mi_head1_pvr2; // 0xbf802a48 0x12
[all …]
H A DregNDSRASP.h460 } REG32; typedef
481 REG32 RASP_PktTimer; // 0xbf201c00 0x00
482 REG32 RASP_PktNum; // 0xbf201c08 0x02
559 REG32 RASP_Str2miu_Head; // 0xbf201c40 0x10
560 REG32 RASP_Str2miu_Tail; // 0xbf201c48 0x12
561 REG32 RASP_Str2miu_Mid; // 0xbf201c50 0x14
562 REG32 RASP_Str2miu_Head2; // 0xbf201c58 0x16
563 REG32 RASP_Str2miu_Tail2; // 0xbf201c60 0x18
564 REG32 RASP_Str2miu_Mid2; // 0xbf201c68 0x1a
610 REG32 RASP_EventDescriptor; // 0xbf201d40 0x50
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/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h9 } REG32; typedef
412 REG32 Str2mi_head2pvr1; // 0xbf802a04 0x01
415 …REG32 Str2mi_mid2pvr1; // 0xbf802a0c 0x03 ,wpt…
418 REG32 Str2mi_tail2pvr1; // 0xbf802a14 0x05
421 REG32 Pcr_L; // 0xbf802a1c 0x07
424 REG32 Pcr_H; // 0xbf802a24 0x09
430 REG32 _xbf202a2c; // 0xbf802a30 0x0c
432 REG32 PVR2_Config; // 0xbf802a38 0x0e
465 REG32 PVR2_LPCR1; // 0xbf802a40 0x10
468 REG32 Str2mi_head1_pvr2; // 0xbf802a48 0x12
[all …]
H A DregNDSRASP.h460 } REG32; typedef
481 REG32 RASP_PktTimer; // 0xbf201c00 0x00
482 REG32 RASP_PktNum; // 0xbf201c08 0x02
559 REG32 RASP_Str2miu_Head; // 0xbf201c40 0x10
560 REG32 RASP_Str2miu_Tail; // 0xbf201c48 0x12
561 REG32 RASP_Str2miu_Mid; // 0xbf201c50 0x14
562 REG32 RASP_Str2miu_Head2; // 0xbf201c58 0x16
563 REG32 RASP_Str2miu_Tail2; // 0xbf201c60 0x18
564 REG32 RASP_Str2miu_Mid2; // 0xbf201c68 0x1a
610 REG32 RASP_EventDescriptor; // 0xbf201d40 0x50
[all …]
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h9 } REG32; typedef
413 REG32 Str2mi_head2pvr1; // 0xbf802a04 0x01
415 …REG32 Str2mi_mid2pvr1; // 0xbf802a0c 0x03 ,wpt…
417 REG32 Str2mi_tail2pvr1; // 0xbf802a14 0x05
420 … REG32 Pcr_L; // 0xbf802a1c 0x07_0x08
422 … REG32 Pcr_H; // 0xbf802a24 0x09_0x0a
428 … REG32 _xbf202a2c; // 0xbf802a30 0x0c_0x0d
430 … REG32 PVR2_Config; // 0xbf802a38 0x0e_0x0f
463 … REG32 PVR2_LPCR1; // 0xbf802a40 0x10_0x11
466 … REG32 Str2mi_head1_pvr2; // 0xbf802a48 0x12_0x13
[all …]
H A DregNDSRASP.h460 } REG32; typedef
481 REG32 RASP_PktTimer; // 0xbf201c00 0x00
482 REG32 RASP_PktNum; // 0xbf201c08 0x02
559 REG32 RASP_Str2miu_Head; // 0xbf201c40 0x10
560 REG32 RASP_Str2miu_Tail; // 0xbf201c48 0x12
561 REG32 RASP_Str2miu_Mid; // 0xbf201c50 0x14
562 REG32 RASP_Str2miu_Head2; // 0xbf201c58 0x16
563 REG32 RASP_Str2miu_Tail2; // 0xbf201c60 0x18
564 REG32 RASP_Str2miu_Mid2; // 0xbf201c68 0x1a
610 REG32 RASP_EventDescriptor; // 0xbf201d40 0x50
[all …]
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h9 } REG32; typedef
413 REG32 Str2mi_head2pvr1; // 0xbf802a04 0x01
415 …REG32 Str2mi_mid2pvr1; // 0xbf802a0c 0x03 ,wpt…
417 REG32 Str2mi_tail2pvr1; // 0xbf802a14 0x05
420 … REG32 Pcr_L; // 0xbf802a1c 0x07_0x08
422 … REG32 Pcr_H; // 0xbf802a24 0x09_0x0a
428 … REG32 _xbf202a2c; // 0xbf802a30 0x0c_0x0d
430 … REG32 PVR2_Config; // 0xbf802a38 0x0e_0x0f
463 … REG32 PVR2_LPCR1; // 0xbf802a40 0x10_0x11
466 … REG32 Str2mi_head1_pvr2; // 0xbf802a48 0x12_0x13
[all …]
H A DregNDSRASP.h460 } REG32; typedef
481 REG32 RASP_PktTimer; // 0xbf201c00 0x00
482 REG32 RASP_PktNum; // 0xbf201c08 0x02
559 REG32 RASP_Str2miu_Head; // 0xbf201c40 0x10
560 REG32 RASP_Str2miu_Tail; // 0xbf201c48 0x12
561 REG32 RASP_Str2miu_Mid; // 0xbf201c50 0x14
562 REG32 RASP_Str2miu_Head2; // 0xbf201c58 0x16
563 REG32 RASP_Str2miu_Tail2; // 0xbf201c60 0x18
564 REG32 RASP_Str2miu_Mid2; // 0xbf201c68 0x1a
610 REG32 RASP_EventDescriptor; // 0xbf201d40 0x50
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DregTSP.h9 } REG32; typedef
414 REG32 Str2mi_head2pvr1; // 0xbf802a04 0x01
417 …REG32 Str2mi_mid2pvr1; // 0xbf802a0c 0x03 ,wpt…
420 REG32 Str2mi_tail2pvr1; // 0xbf802a14 0x05
423 REG32 Pcr_L; // 0xbf802a1c 0x07
426 REG32 Pcr_H; // 0xbf802a24 0x09
432 REG32 _xbf202a2c; // 0xbf802a30 0x0c
434 REG32 PVR2_Config; // 0xbf802a38 0x0e
467 REG32 PVR2_LPCR1; // 0xbf802a40 0x10
470 REG32 Str2mi_head1_pvr2; // 0xbf802a48 0x12
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DregTSP.h9 } REG32; typedef
413 REG32 Str2mi_head2pvr1; // 0xbf802a04 0x01
415 …REG32 Str2mi_mid2pvr1; // 0xbf802a0c 0x03 ,wpt…
417 REG32 Str2mi_tail2pvr1; // 0xbf802a14 0x05
420 … REG32 Pcr_L; // 0xbf802a1c 0x07_0x08
422 … REG32 Pcr_H; // 0xbf802a24 0x09_0x0a
428 … REG32 _xbf202a2c; // 0xbf802a30 0x0c_0x0d
430 … REG32 PVR2_Config; // 0xbf802a38 0x0e_0x0f
463 … REG32 PVR2_LPCR1; // 0xbf802a40 0x10_0x11
466 … REG32 Str2mi_head1_pvr2; // 0xbf802a48 0x12_0x13
[all …]
/utopia/UTPA2-700.0.x/modules/dscmb/hal/curry/nsk2/
H A DregNDSRASP.h460 } REG32; typedef
481 REG32 RASP_PktTimer; // 0xbf201c00 0x00
482 REG32 RASP_PktNum; // 0xbf201c08 0x02
559 REG32 RASP_Str2miu_Head; // 0xbf201c40 0x10
560 REG32 RASP_Str2miu_Tail; // 0xbf201c48 0x12
561 REG32 RASP_Str2miu_Mid; // 0xbf201c50 0x14
562 REG32 RASP_Str2miu_Head2; // 0xbf201c58 0x16
563 REG32 RASP_Str2miu_Tail2; // 0xbf201c60 0x18
564 REG32 RASP_Str2miu_Mid2; // 0xbf201c68 0x1a
610 REG32 RASP_EventDescriptor; // 0xbf201d40 0x50
[all …]
/utopia/UTPA2-700.0.x/modules/security/hal/maserati/aesdma/
H A DregAESDMA.h192 } REG32; typedef
196 REG32 Key_L;
197 REG32 Key_H;
202 REG32 IV_L;
203 REG32 IV_H;
208 REG32 Dma_Ctrl; //0x50
227 REG32 Dma_Filein_Addr; //0x52
228 REG32 Dma_Filein_Num; //0x54
229 REG32 Dma_Fileout_SAddr; //0x56
230 REG32 Dma_Fileout_EAddr; //0x58
[all …]

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