1 #ifndef _TSP2_REG_H_ 2 #define _TSP2_REG_H_ 3 typedef struct _REG32 4 { 5 volatile MS_U16 low; 6 volatile MS_U16 _null_l; 7 volatile MS_U16 high; 8 volatile MS_U16 _null_h; 9 } REG32; 10 11 typedef struct _REG16 12 { 13 volatile MS_U16 data; //[jerry] not to name "low" 14 volatile MS_U16 _null; 15 } REG16; 16 17 typedef struct _TSP32 18 { 19 volatile MS_U32 reg32; 20 } TSP32; 21 22 23 //######################################################################### 24 //#### Hardware Capability Macro Start 25 //######################################################################### 26 27 #define TSP_TSIF_NUM 4 28 #define TSP_PVRENG_NUM 4 29 #define TSP_PVR_IF_NUM 4 30 #define TSP_OTVENG_NUM 4 31 #define STC_ENG_NUM 2 32 #define TSP_PCRFLT_NUM STC_ENG_NUM 33 34 #define TSP_PIDFLT_NUM 192 35 #define TSP_SECFLT_NUM 192 36 #define TSP_SECBUF_NUM 192 37 38 #define TSP_MERGESTREAM_NUM 8 39 40 //@NOTE: accroding to width of FW/VQ/SEC buffer base addr , lower / upper bound may be different 41 #define TSP_FW_BUF_LOW_BUD 0 42 #define TSP_FW_BUF_UP_BUD ((1ULL << 32) - 1) // base addr: bits[31:4] , unit: 16-bytes (bits[3:0]) 43 // base addr = {reg_dma_raddr_msb(8-bits),reg_dma_raddr(16-bits),4'b0(4-bits)} 44 #define TSP_VQ_BUF_LOW_BUD 0 45 #define TSP_VQ_BUF_UP_BUD ((1ULL << 32) - 1) // base addr: bits[31:0] , unit: 1-byte 46 #define TSP_SEC_BUF_LOW_BUD 0 47 #define TSP_SEC_BUF_UP_BUD ((1ULL << 32) - 1) // base addr: bits[31:0] , unit: 1-byte 48 49 50 51 //######################################################################### 52 //#### Hardware Capability Macro End 53 //######################################################################### 54 55 56 // PID Filter 57 typedef TSP32 REG_PidFlt; // 0x210000 58 59 // TSIF 60 #define TSP_PIDFLT_TSIF_MASK 0x0000E000 61 #define TSP_PIDFLT_TSIF_SHFT 13 62 63 #define TSP_FILTER_DEPTH 16 64 65 66 //######################################################################### 67 //#### CLKGEN0 Bank:0x100B 68 //######################################################################### 69 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x1600 + ((addr)<<2)))) 70 71 #define REG_CLKGEN0_DC0_SYTNTH 0x05 72 #define REG_CLKGEN0_STC_CW_SEL 0x0002 73 #define REG_CLKGEN0_STC_CW_EN 0x0004 74 #define REG_CLKGEN0_STC1_CW_SEL 0x0200 75 #define REG_CLKGEN0_STC1_CW_EN 0x0400 76 77 #define REG_CLKGEN0_DC0_STC_CW_L 0x06 78 #define REG_CLKGEN0_DC0_STC_CW_H 0x07 79 #define REG_CLKGEN0_DC0_STC1_CW_L 0x08 80 #define REG_CLKGEN0_DC0_STC1_CW_H 0x09 81 82 #define REG_CLKGEN0_S2P_IN_CLK_SRC 0x0C 83 #define REG_CLKGEN0_S2P_IN_CLK_SHIFT 0 84 #define REG_CLKGEN0_S2P1_IN_CLK_SHIFT 8 85 #define REG_CLKGEN0_S2P_IN_CLK_MASK 0x1F 86 #define REG_CLKGEN0_S2P_IN_CLK_DISABLE 0x0001 87 #define REG_CLKGEN0_S2P_IN_CLK_INVERT 0x0002 88 #define REG_CLKGEN0_S2P_IN_CLK_SRC_SHIFT 2 89 #define REG_CLKGEN0_S2P_IN_CLK_SRC_MASK 0x7 90 91 #define REG_CLKGEN0_TSO0_CLK 0x27 92 #define REG_CLKGEN0_TSO0_SHIFT 0 93 #define REG_CLKGEN0_TS0_CLK 0x28 94 #define REG_CLKGEN0_TS0_SHIFT 0 95 #define REG_CLKGEN0_TS1_CLK 0x28 96 #define REG_CLKGEN0_TS1_SHIFT 8 97 #define REG_CLKGEN0_TS2_CLK 0x29 98 #define REG_CLKGEN0_TS2_SHIFT 0 99 #define REG_CLKGEN0_TS3_CLK 0x29 100 #define REG_CLKGEN0_TS3_SHIFT 8 101 #define REG_CLKGEN0_TS_MASK 0x003F // 4 bit each 102 #define REG_CLKGEN0_TS_DISABLE 0x0001 103 #define REG_CLKGEN0_TS_INVERT 0x0002 104 #define REG_CLKGEN0_TS_SRC_SHIFT 2 105 #define REG_CLKGEN0_TS_SRC_MASK 0x000F 106 #define REG_CLKGEN0_TS_SRC_EXT0 0x0000 107 #define REG_CLKGEN0_TS_SRC_EXT1 0x0001 108 #define REG_CLKGEN0_TS_SRC_EXT2 0x0002 109 #define REG_CLKGEN0_TS_SRC_EXT3 0x0003 110 #define REG_CLKGEN0_TS_SRC_EXT4 0x0004 111 #define REG_CLKGEN0_TS_SRC_EXT5 0x0005 112 #define REG_CLKGEN0_TS_SRC_EXT6 0x0006 113 #define REG_CLKGEN0_TS_SRC_TSO0 0x0007 114 #define REG_CLKGEN0_TS_SRC_TSIO0 0x0008 115 //@NOTE Not support internal demod in KANO 116 #define REG_CLKGEN0_TS_SRC_DMD0 0x000E 117 #define REG_CLKGEN0_TS_SRC_DMD1 0x000F 118 119 //get TSP Clk Gen bank 120 #define REG_CLKGEN0_TSP_CLK 0x2A 121 #define REG_CLKGEN0_TSP_CLK_MASK 0x001F 122 #define REG_CLKGEN0_TSP_SHIFT 0 123 #define REG_CLKGEN0_TSP_DISABLE 0x0001 124 #define REG_CLKGEN0_TSP_INVERT 0x0002 125 //SRC 126 #define REG_CLKGEN0_TSP_SRC_SHIFT 2 127 #define REG_CLKGEN0_TSP_SRC_MASK 0x0007 128 #define REG_CLKGEN0_TSP_SRC_192MHZ 0x0000 129 #define REG_CLKGEN0_TSP_SRC_172MHZ 0x0001 130 #define REG_CLKGEN0_TSP_SRC_144MHZ 0x0002 131 #define REG_CLKGEN0_TSP_SRC_108MHZ 0x0003 132 #define REG_CLKGEN0_TSP_SRC_XTAL 0x0007 133 134 //get STC0/1 Clk Gen bank 135 #define REG_CLKGEN0_STC0_CLK 0x2A 136 #define REG_CLKGEN0_STC0_MASK 0x0F00 137 #define REG_CLKGEN0_STC0_SHIFT 8 138 #define REG_CLKGEN0_STC1_CLK 0x2A 139 #define REG_CLKGEN0_STC1_MASK 0xF000 140 #define REG_CLKGEN0_STC1_SHIFT 12 141 #define REG_CLKGEN0_STC_DISABLE 0x0001 142 #define REG_CLKGEN0_STC_INVERT 0x0002 143 //SRC 144 #define REG_CLKGEN0_STC_SRC_SHIFT 2 145 #define REG_CLKGEN0_STC_SRC_MASK 0x0003 146 #define REG_CLKGEN0_STC_SRC_SYNTH 0x0000 147 #define REG_CLKGEN0_STC_SRC_ONE 0x0001 148 #define REG_CLKGEN0_STC_SRC_27M 0x0002 149 #define REG_CLKGEN0_STC_SRC_XTAL 0x0003 150 151 #define REG_CLKGEN0_STAMP_CLK 0x2F 152 #define REG_CLKGEN0_STAMP_MASK 0x0F00 153 #define REG_CLKGEN0_STAMP_SHIFT 8 154 #define REG_CLKGEN0_STAMP_DISABLE 0x0001 155 #define REG_CLKGEN0_STAMP_INVERT 0x0002 156 157 #define REG_CLKGEN0_PARSER_CLK 0x39 158 #define REG_CLKGEN0_PARSER_MASK 0x0F00 159 #define REG_CLKGEN0_PARSER_SHIFT 8 160 #define REG_CLKGEN0_PARSER_DISABLE 0x0001 161 #define REG_CLKGEN0_PARSER_INVERT 0x0002 162 163 //######################################################################### 164 //#### CLKGEN2 Bank:0x100A 165 //######################################################################### 166 #define TSP_CLKGEN2_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x1400 + ((addr)<<2)))) 167 #define REG_CLKGEN2_DC0_SYTNTH 0x4A 168 #define REG_CLKGEN2_STC2_CW_SEL 0x0002 169 #define REG_CLKGEN2_STC2_CW_EN 0x0004 170 #define REG_CLKGEN2_STC3_CW_SEL 0x0200 171 #define REG_CLKGEN2_STC3_CW_EN 0x0400 172 173 #define REG_CLKGEN2_DC0_STC2_CW_L 0x4B 174 #define REG_CLKGEN2_DC0_STC2_CW_H 0x4C 175 #define REG_CLKGEN2_DC0_STC3_CW_L 0x4D 176 #define REG_CLKGEN2_DC0_STC3_CW_H 0x4E 177 178 //get STC2/3 Clk Gen bank 179 #define REG_CLKGEN2_STC2_CLK 0x4F 180 #define REG_CLKGEN2_STC2_MASK 0x000F 181 #define REG_CLKGEN2_STC2_SHIFT 0 182 #define REG_CLKGEN2_STC3_CLK 0x4F 183 #define REG_CLKGEN2_STC3_MASK 0x00F0 184 #define REG_CLKGEN2_STC3_SHIFT 4 185 #define REG_CLKGEN2_STC_DISABLE 0x0001 186 #define REG_CLKGEN2_STC_INVERT 0x0002 187 //SRC 188 #define REG_CLKGEN2_STC_SRC_SHIFT 2 189 #define REG_CLKGEN2_STC_SRC_MASK 0x0003 190 #define REG_CLKGEN2_STC_SRC_SYNTH 0x0000 191 #define REG_CLKGEN2_STC_SRC_ONE 0x0001 192 #define REG_CLKGEN2_STC_SRC_27M 0x0002 193 #define REG_CLKGEN2_STC_SRC_XTAL 0x0003 194 195 //######################################################################### 196 //#### CHIPTOP Bank:0x101E 197 //######################################################################### 198 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x3c00UL + ((addr)<<2)))) 199 #define REG_TOP_TS0_MUX 0x38 200 #define REG_TOP_TS0_SHIFT 0x0 201 #define REG_TOP_TS1_MUX 0x38 202 #define REG_TOP_TS1_SHIFT 0x4 203 #define REG_TOP_TS2_MUX 0x38 204 #define REG_TOP_TS2_SHIFT 0x8 205 #define REG_TOP_TS3_MUX 0x38 206 #define REG_TOP_TS3_SHIFT 0xC 207 208 209 #define REG_TOP_TSO0_MUX 0x3A 210 #define REG_TOP_TSO0_SHIFT 0 211 212 #define REG_TOP_TS_SRC_MASK 0x000F 213 #define REG_TOP_TS_SRC_EXT0 0x0000 214 #define REG_TOP_TS_SRC_EXT1 0x0001 215 #define REG_TOP_TS_SRC_EXT2 0x0002 216 #define REG_TOP_TS_SRC_EXT3 0x0003 217 #define REG_TOP_TS_SRC_EXT4 0x0004 218 #define REG_TOP_TS_SRC_EXT5 0x0005 219 #define REG_TOP_TS_SRC_EXT6 0x0006 220 #define REG_TOP_TS_SRC_TSO0 0x0007 221 #define REG_TOP_TS_SRC_TSIO0 0x0008 222 #define REG_TOP_TS_SRC_DMD0 0x000e 223 #define REG_TOP_TS_SRC_DMD1 0x000f 224 225 #define REG_TOP_TSO4_5_MUX 0x3B 226 #define REG_TOP_TSO4_SHIFT 0 227 #define REG_TOP_TSO4_MASK 0x0003 228 #define REG_TOP_TSO5_SHIFT 4 229 #define REG_TOP_TSO5_MASK 0x0003 230 231 #define REG_TOP_TS_PADMUX_MODE 0x02 232 #define REG_TOP_TS0MODE_MASK 0x1 233 #define REG_TOP_TS0MODE_SHIFT 0 234 #define REG_TOP_TS0MODE_PARALLEL 1 235 #define REG_TOP_TS1MODE_MASK 0x3 236 #define REG_TOP_TS1MODE_SHIFT 1 237 #define REG_TOP_TS1MODE_INPUT 1 238 #define REG_TOP_TS2MODE_MASK 0x3 239 #define REG_TOP_TS2MODE_SHIFT 3 240 #define REG_TOP_TS2MODE_PARALLEL 1 241 #define REG_TOP_TS2MODE_4WIRED 2 242 #define REG_TOP_TS2MODE_3WIRED 3 243 244 #define REG_TOP_TS_OUTPUT_MODE 0x07 245 #define REG_TOP_TS_OUT_MODE_MASK 0x3 246 #define REG_TOP_TS_OUT_MODE_SHIFT 14 247 #define REG_TOP_TS_OUT_MODE_TSO 1 248 #define REG_TOP_TS_OUT_MODE_S2P 2 249 #define REG_TOP_TS_OUT_MODE_S2P1 3 250 251 #define REG_TOP_TSP_BOOT_CLK_SEL 0x54 252 #define REG_TOP_TSP_BOOT_CLK_SEL_MASK 0x0100 253 #define REG_TOP_TSP_BOOT_CLK_SEL_TSP 0x0000 254 255 #define REG_TOP_TSP_3WIRE_MODE 0x11 256 #define REG_TOP_TSP_TS0_3WIRE_EN 0x01 257 #define REG_TOP_TSP_TS1_3WIRE_EN 0x02 258 259 #define REG_TOP_TSP_3WIRE_MODE1 0x7b 260 #define REG_TOP_TSP_TS2_3WIRE_EN 0x01 261 #define REG_TOP_TSP_TS3_3WIRE_EN 0x02 262 263 264 265 #define TSP_MMFI_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x27E00 + ((addr)<<2)))) 266 #define REG_MMFI_TSP_SEL_SRAM 0x70 267 #define REG_MMFI_TSP_SEL_SRAM_EN 0x0002 268 269 #define TSP_TSO_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0xE0C00 + ((addr)<<2)))) 270 #define REG_TSO_TSP_CONFIG0 0x1C 271 #define REG_TSO_TSP_S2P_MASK 0x001F 272 #define REG_TSO_TSP_S2P_EN 0x0001 273 #define REG_TSO_TSP_S2P_TS_SIN_C0 0x0002 274 #define REG_TSO_TSP_S2P_TS_SIN_C1 0x0004 275 #define REG_TSO_TSP_S2P_3WIRE 0x0008 276 #define REG_TSO_TSP_BYPASS_S2P 0x0010 277 278 #define REG_TSO_TSP_S2P1_MASK 0x1F00 279 #define REG_TSO_TSP_S2P1_EN 0x0100 280 #define REG_TSO_TSP_S2P1_TS_SIN_C0 0x0200 281 #define REG_TSO_TSP_S2P1_TS_SIN_C1 0x0400 282 #define REG_TSO_TSP_S2P1_3WIRE 0x0800 283 #define REG_TSO_TSP_BYPASS_S2P1 0x1000 284 285 286 typedef struct _REG_SecFlt 287 { 288 TSP32 Ctrl; 289 // Software Usage Flags 290 #define TSP_SECFLT_USER_MASK 0x00000007 291 #define TSP_SECFLT_USER_SHFT 0 292 #define TSP_SECFLT_USER_NULL 0x0 293 #define TSP_SECFLT_USER_SEC 0x1 294 #define TSP_SECFLT_USER_PES 0x2 295 #define TSP_SECFLT_USER_PKT 0x3 296 #define TSP_SECFLT_USER_PCR 0x4 297 #define TSP_SECFLT_USER_TTX 0x5 298 /* 299 #define TSP_SECFLT_USER_EMM 0x6 300 #define TSP_SECFLT_USER_ECM 0x7 301 #define TSP_SECFLT_USER_OAD 0x8 302 */ 303 304 #define TSP_SEC_MATCH_INV 0x00000008 // HW 305 306 // for 307 // TSP_SECFLT_TYPE_SEC 308 // TSP_SECFLT_TYPE_PES 309 // TSP_SECFLT_TYPE_PKT 310 // TSP_SECFLT_TYPE_TTX 311 // TSP_SECFLT_TYPE_OAD 312 #define TSP_SECFLT_MODE_MASK 0x00000030 // software implementation 313 #define TSP_SECFLT_MODE_SHFT 4 314 #define TSP_SECFLT_MODE_CONTI 0x0 // SEC 315 #define TSP_SECFLT_MODE_ONESHOT 0x1 316 #define TSP_SECFLT_MODE_CRCCHK 0x2 317 // for TSP_SECFLT_TYPE_PCR 318 #define TSP_SECFLT_PCRRST 0x00000010 //[OBSOLETED] PCR 319 320 321 //[NOTE] update section filter 322 // It's not recommended for user updating section filter control register 323 // when filter is enable. There may be race condition. 324 #define TSP_SECFLT_STATE_MASK 0x000000C0 // software implementation 325 #define TSP_SECFLT_STATE_SHFT 6 326 #define TSP_SECFLT_STATE_OVERFLOW 0x1 327 #define TSP_SECFLT_STATE_DISABLE 0x2 328 329 #define TSP_SECFLT_BEMASK 0x0000FF00 //[Reserved] 330 331 332 // for 333 // TSP_SECFLT_SEL_BUF 334 #define TSP_SECFLT_SECBUF_MASK 0xFF000000 // [31:26] secbuf id 335 #define TSP_SECFLT_SECBUF_SHFT 24 336 #define TSP_SECFLT_SECBUF_MAX 0xFF // software usage 337 338 TSP32 Match[TSP_FILTER_DEPTH/sizeof(TSP32)]; 339 TSP32 Mask[TSP_FILTER_DEPTH/sizeof(TSP32)]; 340 /* 341 TSP32 BufStart; 342 TSP32 BufEnd; 343 TSP32 BufRead; 344 TSP32 BufWrite; 345 TSP32 BufCur; 346 */ 347 TSP32 _x24[(0x38-0x24)/sizeof(TSP32)]; // (0x00211024-0x0021103B)/4 348 349 TSP32 RmnCnt; 350 #define TSP_SECFLT_ALLOC_MASK 0x80000000 351 #define TSP_SECFLT_ALLOC_SHFT 31 352 #define TSP_SECFLT_OWNER_MASK 0x70000000 353 #define TSP_SECFLT_OWNER_SHFT 24 354 355 #define TSP_SECFLT_MODE_AUTO_CRCCHK 0x00100000 //sec flt mode bits are not enough, arbitrarily occupy here 356 357 #define TSP_SECBUF_RMNCNT_MASK 0x0000FFFF // TS/PES length 358 #define TSP_SECBUF_RMNCNT_SHFT 0 359 360 /* 361 // for 362 // TSP_SECFLT_TYPE_ECM 363 #define TSP_SECFLT_ECM_IDX_SHFT 16 364 #define TSP_SECFLT_ECM_IDX_MASK 0x00070000 365 #define TSP_SECFLT_ECM_IDX_NULL 0x00000007 // only alow 0 .. 5 366 */ 367 368 TSP32 CRC32; 369 TSP32 NMask[TSP_FILTER_DEPTH/sizeof(MS_U32)]; 370 TSP32 _x50[(0x80-0x50)/sizeof(TSP32)]; // (0x00211050-0x0021107F)/4 371 } REG_SecFlt; 372 373 typedef struct _REG_SecBuf 374 { 375 TSP32 Start; 376 #define TSP_SECBUF_START_MASK 0x1FFFFFF0 //section buffers of kaiser and keltic are "4" bits aligment 377 #define TSP_SECBUF_OWNER_MASK 0x60000000 378 #define TSP_SECBUF_OWNER_SHFT 29 379 #define TSP_SECBUF_ALLOC_MASK 0x80000000 380 #define TSP_SECBUF_ALLOC_SHFT 31 381 TSP32 End; 382 TSP32 Read; 383 TSP32 Write; 384 TSP32 Cur; 385 TSP32 _x38[(0xA4-0x38)/sizeof(TSP32)]; // (0x0021103C-0x002110A4)/4 386 } REG_SecBuf; 387 388 typedef struct _REG_Pid 389 { // CPU(byte) RIU(index) MIPS(0x1500/2+RIU)*4 390 REG_PidFlt Flt[TSP_PIDFLT_NUM]; // 0x00210000-0x00210007C 391 } REG_Pid; 392 393 typedef struct _REG_Sec 394 { // CPU(byte) RIU(index) MIPS(0x1500/2+RIU)*4 395 REG_SecFlt Flt[TSP_SECFLT_NUM]; 396 } REG_Sec; 397 398 399 typedef struct _REG_Buf 400 { 401 REG_SecBuf Buf[TSP_SECFLT_NUM]; 402 } REG_Buf; 403 404 405 //@NOTE TSP 0~1 406 typedef struct _REG_Ctrl 407 { 408 //---------------------------------------------- 409 // 0xBF802A00 MIPS direct access 410 //---------------------------------------------- 411 // Type Name Index(word) CPU(byte) MIPS(0x1500/2+index)*4 412 REG16 _xbf202a00; // 0xbf802a00 0x00 413 REG32 Str2mi_head2pvr1; // 0xbf802a04 0x01 414 #define TSP_HW_PVR1_BUF_HEAD2_MASK 0x0FFFFFFF 415 REG32 Str2mi_mid2pvr1; // 0xbf802a0c 0x03 ,wptr & mid share same register 416 #define TSP_HW_PVR1_BUF_MID2_MASK 0x0FFFFFFF 417 REG32 Str2mi_tail2pvr1; // 0xbf802a14 0x05 418 #define TSP_HW_PVR1_BUF_TAIL2_MASK 0x0FFFFFFF 419 420 REG32 Pcr_L; // 0xbf802a1c 0x07_0x08 421 #define TSP_PCR64_L32_MASK 0xFFFFFFFF 422 REG32 Pcr_H; // 0xbf802a24 0x09_0x0a 423 #define TSP_PCR64_H32_MASK 0xFFFFFFFF // PCR64 Middle 64 424 425 REG16 Mobf_Filein_Idx; // 0xbf802a2c 0x0b 426 #define TSP_MOBF_FILEIN_MASK 0x0000001F 427 428 REG32 _xbf202a2c; // 0xbf802a30 0x0c_0x0d 429 430 REG32 PVR2_Config; // 0xbf802a38 0x0e_0x0f 431 #define TSP_PVR2_LPCR1_WLD 0x00000001 432 #define TSP_PVR2_LPCR1_RLD 0x00000002 433 #define TSP_PVR2_STR2MIU_DSWAP 0x00000004 434 #define TSP_PVR2_STR2MIU_EN 0x00000008 435 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010 436 #define TSP_PVR2_STR2MIU_BT_ORDER 0x00000020 437 #define TSP_PVR2_STR2MIU_PAUSE 0x00000040 438 #define TSP_PVR2_REG_PINGPONG_EN 0x00000080 439 #define TSP_PVR2_PVR_ALIGN_EN 0x00000100 440 #define TSP_PVR2_DMA_FLUSH_EN 0x00000200 441 #define TSP_PVR2_PKT192_EN 0x00000400 442 #define TSP_PVR2_BURST_LEN_MASK 0x00001800 443 #define TSP_PVR2_BURST_LEN_SHIFT 11 444 #define TSP_REC_DATA2_INV 0x00002000 445 #define TSP_V_BLOCK_DIS 0x00004000 446 #define TSP_V3d_BLOCK_DIS 0x00008000 447 #define TSP_A_BLOCK_DIS 0x00010000 448 #define TSP_AD_BLOCK_DIS 0x00020000 449 #define TSP_PVR1_BLOCK_DIS 0x00040000 450 #define TSP_PVR2_BLOCK_DIS 0x00080000 451 #define TSP_TS_IF2_EN 0x00100000 452 #define TSP_TS_DATA2_SWAP 0x00200000 453 #define TSP_P_SEL2 0x00400000 454 #define TSP_EXT_SYNC_SEL2 0x00800000 455 #define TSP_BYPASS_TSIF2 0x01000000 456 #define TSP_TEI_SKIP_PKT2 0x02000000 457 #define TSP_AC_BLOCK_DIS 0x04000000 458 #define TSP_ADD_BLOCK_DIS 0x08000000 459 #define TSP_CLR_LOCKED_PKT_CNT 0x20000000 460 #define TSP_CLR_PKT_CNT 0x40000000 461 #define TSP_CLR_PVR_OVERFLOW 0x80000000 462 463 REG32 PVR2_LPCR1; // 0xbf802a40 0x10_0x11 464 #define TSP_STR2MI2_ADDR_MASK 0x0FFFFFFF 465 466 REG32 Str2mi_head1_pvr2; // 0xbf802a48 0x12_0x13 467 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14_0x15 468 REG32 Str2mi_tail1_pvr2; // 0xbf802a58 0x16_0x17 469 REG32 Str2mi_head2_pvr2; // 0xbf802a60 0x18_0x19 470 REG32 Str2mi_mid2_pvr2; // 0xbf802a68 0x1a_0x1b, PVR2 mid address & write point 471 REG32 Str2mi_tail2_pvr2; // 0xbf802a70 0x1c_0x1d 472 REG32 Hw_SyncByte2; // 0xbf802a78 0x1e_0x1f 473 #define TSP_HW_CFG2_PACKET_SYNCBYTE2_MASK 0x000000FF 474 #define TSP_HW_CFG2_PACKET_SYNCBYTE2_SHFT 0 475 #define TSP_HW_CFG2_PACKET_SIZE2_MASK 0x0000FF00 476 #define TSP_HW_CFG2_PACKET_SIZE2_SHFT 8 477 #define TSP_HW_CFG2_PACKET_CHK_SIZE2_MASK 0x00FF0000 478 #define TSP_HW_CFG2_PACKET_CHK_SIZE2_SHFT 16 479 480 REG32 Pkt_CacheW0; // 0xbf802a80 0x20 481 REG32 Pkt_CacheW1; // 0xbf802a88 0x22 482 REG32 Pkt_CacheW2; // 0xbf802a90 0x24 483 REG32 Pkt_CacheW3; // 0xbf802a98 0x26 484 REG32 Pkt_CacheIdx; // 0xbf802aa0 0x28 485 486 REG32 Pkt_DMA; // 0xbf802aa8 0x2a 487 #define TSP_SEC_DMAFIL_NUM_MASK 0x000000FF 488 #define TSP_SEC_DMAFIL_NUM_SHIFT 0 489 #define TSP_SEC_DMASRC_OFFSET_MASK 0x0000FF00 490 #define TSP_SEC_DMASRC_OFFSET_SHIFT 8 491 #define TSP_SEC_DMADES_LEN_MASK 0x00FF0000 492 #define TSP_SEC_DMADES_LEN_SHIFT 16 493 494 REG16 Hw_Config0; // 0xbf802ab0 0x2c 495 #define TSP_HW_CFG0_DATA_PORT_SEL 0x0001 //TSIF0 data port output select. 0: select live TS to be TSIF output 1: select data port to be TSIF output 496 #define TSP_HW_CFG0_TSIFO_SERL 0x0000 497 #define TSP_HW_CFG0_TSIF0_PARL 0x0002 498 #define TSP_HW_CFG0_TSIF0_EXTSYNC 0x0004 499 #define TSP_HW_CFG0_TSIF0_TS_BYPASS 0x0008 500 #define TSP_HW_CFG0_TSIF0_VPID_BYPASS 0x0010 501 #define TSP_HW_CFG0_TSIF0_APID_BYPASS 0x0020 502 #define TSP_HW_CFG0_WB_DMA_RESET 0x0040 503 #define TSP_HW_CFG0_PACKET_BUF_SIZE_MASK 0xFF00 504 #define TSP_HW_CFG0_PACKET_BUF_SIZE_SHIFT 8 505 506 REG16 Hw_PktSize0; // 0xbf802ab4 0x2d 507 #define TSP_HW_CFG0_PACKET_PIDFLT0_SIZE_MASK 0x00FF 508 #define TSP_HW_CFG0_PACKET_PIDFLT0_SIZE_SHIFT 0 509 #define TSP_HW_CFG0_PACKET_CHK_SIZE_MASK 0xFF00 510 #define TSP_HW_CFG0_PACKET_CHK_SIZE_SHFT 8 511 512 REG16 STC_Config; // 0xbf802ab8 0x2e 513 #define TSP_STC_CFG_SET_TIME_BASE_64b_3 0x0001 514 #define TSP_STC_CFG_CNT64b_3_EN 0x0002 515 #define TSP_STC_CFG_CNT64b_3_LD 0x0004 516 #define TSP_STC_CFG_SET_TIME_BASE_64b_4 0x0010 517 #define TSP_STC_CFG_CNT64b_4_EN 0x0020 518 #define TSP_STC_CFG_CNT64b_4_LD 0x0040 519 520 REG16 TSP_DBG_PORT; // 0xbf802ab8 0x2f 521 #define TSP_DNG_DATA_PORT_MASK 0x00FF 522 #define TSP_DNG_DATA_PORT_SHIFT 0 523 524 REG32 Pcr_L_CmdQ; // 0xbf802ac0 0x30 525 REG16 Pcr_H_CmdQ; // 0xbf802ac8 0x32 526 #define TSP_REG_PCR_CMDQ_H 0x0001 527 528 REG16 Vd_Pid_Hit; // 0xbf802acc 0x33 529 #define TSP_VPID_MASK 0x1FFF 530 531 REG16 Aud_Pid_Hit; // 0xbf802ad0 0x34 532 #define TSP_APID_MASK 0x1FFF 533 534 REG16 Pkt_Info; // 0xbf802ad4 0x35 535 #define TSP_PKT_PID_8_12_CP_MASK 0x001F 536 #define TSP_PKT_PID_8_12_CP_SHIFT 0 537 #define TSP_PKT_PRI_MASK 0x0020 538 #define TSP_PKT_PRI_SHIFT 5 539 #define TSP_PKT_PLST_MASK 0x0040 540 #define TSP_PKT_PLST_SHIFT 6 541 #define TSP_PKT_ERR 0x0080 542 #define TSP_PKT_ERR_SHIFT 7 543 544 REG16 Pkt_Info2; // 0xbf802ad8 0x36 545 #define TSP_PKT_INFO_CC_MASK 0x000F 546 #define TSP_PKT_INFO_CC_SHFT 0 547 #define TSP_PKT_INFO_ADPCNTL_MASK 0x0030 548 #define TSP_PKT_INFO_ADPCNTL_SHFT 4 549 #define TSP_PKT_INFO_SCMB 0x00C0 550 #define TSP_PKT_INFO_SCMB_SHFT 6 551 #define TSP_PKT_PID_0_7_CP_MASK 0xFF00 552 #define TSP_PKT_PID_0_7_CP_SHIFT 8 553 554 REG16 AVFifoSts; // 0xbf802adc 0x37 555 #define TSP_VFIFO3D_EMPTY 0x0001 556 #define TSP_VFIFO3D_EMPTY_SHFT 0 557 #define TSP_VFIFO3D_FULL 0x0002 558 #define TSP_VFIFO3D_FULL_SHFT 1 559 #define TSP_VFIFO3D_LEVEL 0x000C 560 #define TSP_VFIFO3D_LEVEL_SHFT 2 561 #define TSP_VFIFO_EMPTY 0x0010 562 #define TSP_VFIFO_EMPTY_SHFT 4 563 #define TSP_VFIFO_FULL 0x0020 564 #define TSP_VFIFO_FULL_SHFT 5 565 #define TSP_VFIFO_LEVEL 0x00C0 566 #define TSP_VFIFO_LEVEL_SHFT 6 567 #define TSP_AFIFO_EMPTY 0x0100 568 #define TSP_AFIFO_EMPTY_SHFT 8 569 #define TSP_AFIFO_FULL 0x0200 570 #define TSP_AFIFO_FULL_SHFT 9 571 #define TSP_AFIFO_LEVEL 0x0C00 572 #define TSP_AFIFO_LEVEL_SHFT 10 573 #define TSP_AFIFOB_EMPTY 0x1000 574 #define TSP_AFIFOB_EMPTY_SHFT 12 575 #define TSP_AFIFOB_FULL 0x2000 576 #define TSP_AFIFOB_FULL_SHFT 13 577 #define TSP_AFIFOB_LEVEL 0xC000 578 #define TSP_AFIFOB_LEVEL_SHFT 14 579 580 REG32 SwInt_Stat; // 0xbf802ae0 0x38 581 #define TSP_SWINT_INFO_SEC_MASK 0x000000FF 582 #define TSP_SWINT_INFO_SEC_SHFT 0 583 #define TSP_SWINT_INFO_ENG_MASK 0x0000FF00 584 #define TSP_SWINT_INFO_ENG_SHFT 8 585 #define TSP_SWINT_STATUS_CMD_MASK 0x7FFF0000 586 #define TSP_SWINT_STATUS_CMD_SHFT 16 587 #define TSP_SWINT_STATUS_SEC_RDY 0x0001 588 #define TSP_SWINT_STATUS_REQ_RDY 0x0002 589 #define TSP_SWINT_STATUS_SEC_RDY_CRCERR 0x0003 590 #define TSP_SWINT_STATUS_BUF_OVFLOW 0x0006 591 #define TSP_SWINT_STATUS_SEC_CRCERR 0x0007 592 #define TSP_SWINT_STATUS_SEC_ERROR 0x0008 593 #define TSP_SWINT_STATUS_SYNC_LOST 0x0010 594 #define TSP_SWINT_STATUS_PKT_OVRUN 0x0020 595 #define TSP_SWINT_STATUS_DEBUG 0x0030 596 #define TSP_SWINT_CMD_DMA_PAUSE 0x0100 597 #define TSP_SWINT_CMD_DMA_RESUME 0x0200 598 #define TSP_SWINT_STATUS_SEC_GROUP 0x000F 599 #define TSP_SWINT_STATUS_GROUP 0x00FF 600 #define TSP_SWINT_CMD_GROUP 0x7F00 601 #define TSP_SWINT_CMD_STC_UPD 0x0400 602 #define TSP_SWINT_CTRL_FIRE 0x80000000 603 604 REG32 TsDma_Addr; // 0xbf802ae8 0x3a 605 REG32 TsDma_Size; // 0xbf802af0 0x3c 606 REG16 TsDma_Ctrl; // 0xbf802af8 0x3e 607 #define TSP_TSDMA_CTRL_START 0x0001 608 #define TSP_TSDMA_FILEIN_DONE 0x0002 609 #define TSP_TSDMA_INIT_TRUST 0x0004 610 #define TSP_TSDMA_STAT_ABORT 0x0080 611 612 REG16 TsDma_mdQ; // 0xbf802af8 0x3f 613 #define TSP_CMDQ_CNT_MASK 0x001F 614 #define TSP_CMDQ_CNT_SHFT 0 615 #define TSP_CMDQ_FULL 0x0040 616 #define TSP_CMDQ_EMPTY 0x0080 617 #define TSP_CMDQ_SIZE 16 618 #define TSP_CMDQ_WR_LEVEL_MASK 0x0300 619 #define TSP_CMDQ_WR_LEVEL_SHFT 8 620 621 REG32 MCU_Cmd; // 0xbf802b00 0x40 622 #define TSP_MCU_CMD_MASK 0x0000FFFF 623 #define TSP_MCU_CMD_NULL 0x00000000 624 #define TSP_MCU_CMD_READ 0x00000001 625 #define TSP_MCU_CMD_WRITE 0x00000002 626 #define TSP_MCU_CMD_ALIVE 0x00000100 627 #define TSP_MCU_CMD_DBG 0x00000200 628 #define TSP_MCU_CMD_BUFRST 0x00000400 629 #define TSP_MCU_CMD_SECRDYINT_DISABLE 0x00000800 630 #define TSP_MCU_CMD_SEC_CC_CHECK_DISABLE 0x00001000 631 #define TSP_MCU_CMD_INFO 0x00008000 632 #define INFO_FW_VERSION 0x0001 633 #define INFO_FW_DATE 0x0002 634 635 REG16 PktSize1; // 0xbf802b08 0x42 636 #define TSP_HW_CFG2_PACKET_CHK_SIZE1_MASK 0x00FF 637 #define TSP_HW_CFG2_PACKET_CHK_SIZE1_SHFT 0 638 #define TSP_HW_CFG2_PACKET_SYNCBYTE1_MASK 0xFF00 639 #define TSP_HW_CFG2_PACKET_SYNCBYTE1_SHFT 8 640 641 REG16 Hw_Config2; // 0xbf802b0C 0x43 642 #define TSP_HW_CFG2_PACKET_SIZE1_MASK 0x00FF 643 #define TSP_HW_CFG2_PACKET_SIZE1_SHFT 0 644 #define TSP_HW_CFG2_TSIF1_SERL 0x0000 645 #define TSP_HW_CFG2_TSIF1_PARL 0x0100 646 #define TSP_HW_CFG2_TSIF1_EXTSYNC 0x0200 647 #define TSP_HW_CFG2_TSIF1_TS_BYPASS 0x1000 648 649 REG16 Hw_PVRCfg; // 0xbf802b10 0x44 650 #define TSP_HW_CFG4_SECDMA_PRI_HIGH 0x0001 651 #define TSP_HW_CFG4_PVR_ENABLE 0x0002 652 #define TSP_HW_CFG4_PVR_ENDIAN_BIG 0x0004 // 1: record TS to MIU with big endian, 0: record TS to MIU with little endian 653 #define TSP_HW_CFG4_TSIF1_ENABLE 0x0008 // 1: enable ts interface 1 and vice versa 654 #define TSP_HW_CFG4_PVR_FLUSH 0x0010 // 1: str2mi_wadr <- str2mi_miu_head 655 #define TSP_HW_CFG4_PVRBUF_BYTEORDER_BIG 0x0020 // Byte order of 8-byte recoding buffer to MIU. 656 #define TSP_HW_CFG4_PVR_PAUSE 0x0040 657 #define TSP_HW_CFG4_MEMTSDATA_ENDIAN_BIG 0x0080 // 32-bit data byte order read from 8x64 FIFO when playing file. 658 #define TSP_HW_CFG4_TSIF0_ENABLE 0x0100 // 1: enable ts interface 0 and vice versa 659 #define TSP_SYNC_RISING_DETECT 0x0200 // Reset bit count when data valid signal of TS interface is low. 660 #define TSP_VALID_FALLING_DETECT 0x0400 // Reset bit count on the rising sync signal of TS interface. 661 #define TSP_HW_CFG4_TS_DATA0_SWAP 0x0800 // Set 1 to swap the bit order of TS0 DATA bus 662 #define TSP_HW_CFG4_TS_DATA1_SWAP 0x1000 // Set 1 to swap the bit order of TS1 DATA bus 663 #define TSP_HW_TSP2OUTAEON_INT_EN 0x4000 // Set 1 to force interrupt to outside AEON 664 #define TSP_HW_HK_INT_FORCE 0x8000 // Set 1 to force interrupt to HK_MCU 665 666 REG16 Hw_Config4; // 0xbf802b14 0x45 667 #define TSP_HW_CFG4_ALT_TS_SIZE 0x0001 // enable TS packets in 204 mode 668 #define TSP_HW_CFG4_PS_AUDC_EN 0x0002 // program stream audiodC enable 669 #define TSP_HW_CFG4_BYTE_ADDR_DMA 0x000D // prevent from byte enable bug, bit1~3 must enable togather 670 #define TSP_HW_DMA_MODE_MASK 0x0030 // Section filter DMA mode, 2'b00: Single.2'b01: Burst 2 bytes.2'b10: Burst 4 bytes.2'b11: Burst 8 bytes. 671 #define TSP_HW_DMA_MODE_SHIFT 4 672 #define TSP_HW_CFG4_WSTAT_CH_EN 0x0040 673 #define TSP_HW_CFG4_PS_VID_EN 0x0080 // program stream video enable 674 #define TSP_HW_CFG4_PS_AUD_EN 0x0100 // program stream audio enable 675 #define TSP_HW_CFG4_PS_AUDB_EN 0x0200 // program stream audioB enable 676 #define TSP_HW_CFG4_APES_ERR_RM_EN 0x0400 // Set 1 to enable removing APES error packet 677 #define TSP_HW_CFG4_VPES_ERR_RM_EN 0x0800 // Set 1 to enable removing VPES error packet 678 #define TSP_HW_CFG4_SEC_ERR_RM_EN 0x1000 // Set 1 to enable removing section error packet 679 #define TSP_HW_CFG4_PS_AUDD_EN 0x2000 // program stream audioD enable 680 #define TSP_HW_CFG4_DATA_CHK_2T 0x8000 // Set 1 to enable the patch of internal sync in "tsif" 681 682 REG32 NOEA_PC; // 0xbf802b18 0x46 683 684 REG16 Idr_Ctrl; // 0xbf802b20 0x48 685 #define TSP_IDR_START 0x0001 686 #define TSP_IDR_READ 0x0000 687 #define TSP_IDR_WRITE 0x0002 688 #define TSP_IDR_WR_ENDIAN_BIG 0x0004 689 #define TSP_IDR_WR_ADDR_AUTO_INC 0x0008 // Set 1 to enable address auto-increment after finishing read/write 690 #define TSP_IDR_WDAT0_TRIG_EN 0x0010 // WDAT0_TRIG_EN 691 #define TSP_IDR_MCUWAIT 0x0020 692 #define TSP_IDR_SOFT_RST 0x0080 // Set 1 to soft-reset the IND32 module 693 #define TSP_IDR_AUTO_INC_VAL_MASK 0x0F00 694 #define TSP_IDR_AUTO_INC_VAL_SHIFT 8 695 696 REG32 Idr_Addr; // 0xbf802b24 0x49 697 REG32 Idr_Write; // 0xbf802b2c 0x4b 698 REG32 Idr_Read; // 0xbf802b34 0x4d 699 700 REG16 Fifo_Status; // 0xbf802b3c 0x4f 701 #define TSP_V3D_FIFO_DISCON 0x0010 702 #define TSP_V3D_FIFO_OVERFLOW 0x0020 703 #define TSP_VD_FIFO_DISCON 0x0200 704 #define TSP_VD_FIFO_OVERFLOW 0x0800 705 #define TSP_AUB_FIFO_OVERFLOW 0x1000 706 #define TSP_AU_FIFO_OVERFLOW 0x2000 707 708 // only 25 bits supported in PVR address. 8 bytes address 709 #define TSP_STR2MI2_ADDR_MASK 0x0FFFFFFF 710 REG32 TsRec_Head; // 0xbf802b40 0x50 711 REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid address & write point 712 REG32 TsRec_Tail; // 0xbf802b50 0x54 713 REG32 _xbf802b58[2]; // 0xbf802b58 ~ 0xbf802b60 0x56~0x59 714 715 REG16 reg15b4; // 0xbf802b68 0x5a 716 #define TSP_VQ_DMAW_PROTECT_EN 0x0001 717 #define TSP_SEC_CB_PVR2_DAMW_PROTECT_EN 0x0002 718 #define TSP_PVR_PID_BYPASS 0x0008 // Set 1 to bypass PID in record 719 #define TSP_PVR_PID_BYPASS2 0x0010 // Set 1 to bypass PID in record2 720 #define TSP_BD_AUD_EN 0x0020 // Set 1 to enable the BD audio stream recognization ( core /extend audio stream) 721 #define TSP_BD2_AUD_EN 0x0200 // Set 1 to enable the BD audio stream recognization ( core /extend audio stream) 722 #define TSP_AVFIFO_RD_EN 0x0080 // 0: AFIFO and VFIFO read are connected to MVD and MAD, 1: AFIFO and VFIFO read are controlled by registers (0x15B5[2:0]) 723 #define TSP_AVFIFO_RD 0x0100 // If AVFIFO_RD_EN is 1, set to 1, then set to 0 would issue a read strobe to AFIFO or VFIFO 724 #define TSP_NMATCH_DISABLE 0x0800 725 #define TSP_PVR_INVERT 0x1000 // Set 1 to enable data payload invert for PVR record 726 #define TSP_PLY_FILE_INV_EN 0x2000 // Set 1 to enable data payload invert in pidflt0 file path 727 #define TSP_PLY_TS_INV_EN 0x4000 // Set 1 to enable data payload invert in pidflt0 TS path 728 #define TSP_FILEIN_BYTETIMER_ENABLE 0x8000 // Set 1 to enable byte timer in ts_if0 TS path 729 730 REG16 reg15b8; // 0xbf802b6C 0x5b 731 #define TSP_PVR1_PINGPONG 0x0001 // Set 1 to enable MIU addresses with pinpon mode 732 #define TSP_VQ_STATUS_SEL 0x0002 733 #define TSP_TEI_SKIPE_PKT_PID0 0x0004 // Set 1 to skip error packets in pidflt0 TS path 734 #define TSP_TEI_SKIPE_PKT_PID4 0x0008 // Set 1 to skip error packets in pidflt4 TS path 735 #define TSP_TEI_SKIPE_PKT_PID1 0x0010 // Set 1 to skip error packets in pidflt1 TS path 736 #define TSP_TEI_SKIPE_PKT_PID3 0x0020 // Set 1 to skip error packets in pidflt3 TS path 737 #define TSP_REMOVE_DUP_AV_PKT 0x0040 // Set 1 to remove duplicate A/V packet 738 #define TSP_64bit_PCR2_ld 0x0080 739 #define TSP_cnt_33b_ld 0x0100 740 #define TSP_FORCE_SYNCBYTE 0x0200 // Set 1 to force sync byte (8'h47) in ts_if0 and ts_if1 path. 741 #define TSP_SERIAL_EXT_SYNC_1T 0x0400 // Set 1 to detect serial-in sync without 8-cycle mode 742 #define TSP_BURST_LEN_MASK 0x1800 // 00,01: burst length = 4; 10,11: burst length = 1 743 #define TSP_BURST_LEN_SHIFT 11 744 #define TSP_MATCH_PID_SRC_MASK 0xE000 // Select the source of pid filter number with hit pid and match pid number with scramble information, 00 : from pkt_demux0, 01 : from pkt_demux_file, 10 : from pkt_demux1, 11 : from pkt_demux2 745 #define TSP_MATCH_PID_SRC_SHIFT 13 746 #define TSP_MATCH_PID_SRC_PKTDMX0 0 747 #define TSP_MATCH_PID_SRC_PKTDMX1 1 748 #define TSP_MATCH_PID_SRC_PKTDMX2 2 749 #define TSP_MATCH_PID_SRC_PKTDMX3 3 750 751 REG32 TSP_MATCH_PID_NUM; // 0xbf802b70 0x5c 752 REG32 TSP_IWB_WAIT; // 0xbf802b78 0x5e // Wait count settings for IWB when TSP CPU i-cache is enabled. 753 754 REG32 Cpu_Base; // 0xbf802b80 0x60 755 #define TSP_CPU_BASE_ADDR_MASK 0x0FFFFFFF 756 757 REG32 Qmem_Ibase; // 0xbf802b88 0x62 758 REG32 Qmem_Imask; // 0xbf802b90 0x64 759 REG32 Qmem_Dbase; // 0xbf802b98 0x66 760 REG32 Qmem_Dmask; // 0xbf802ba0 0x68 761 762 REG32 TSP_Debug; // 0xbf802ba8 0x6a 763 #define TSP_DEBUG_MASK 0x00FFFFFF 764 765 REG32 _xbf802bb0; // 0xbf802bb0 0x6c 766 767 REG32 TsFileIn_RPtr; // 0xbf802bb8 0x6e 768 #define TSP_FILE_RPTR_MASK 0x0FFFFFFF 769 REG32 TsFileIn_Timer; // 0xbf802bc0 0x70 770 #define TSP_FILE_TIMER_MASK 0x00FFFFFF 771 REG32 TsFileIn_Head; // 0xbf802bc8 0x72 772 #define TSP_FILE_ADDR_MASK 0x0FFFFFFF 773 REG32 TsFileIn_Mid; // 0xbf802bd0 0x74 774 775 REG32 TsFileIn_Tail; // 0xbf802bd8 0x76 776 777 REG16 Dnld_Ctrl_Addr; // 0xbf802be0 0x78 778 #define TSP_DNLD_ADDR_MASK 0xFFFF 779 #define TSP_DNLD_ADDR_SHFT 0 780 #define TSP_DNLD_ADDR_ALI_SHIFT 4 // Bit [11:4] of DMA_RADDR[19:0] 781 782 REG16 Dnld_Ctrl_Size; // 0xbf802be4 0x79 783 #define TSP_DNLD_NUM_MASK 0xFFFF 784 #define TSP_DNLD_NUM_SHFT 0 785 786 REG16 TSP_Ctrl; // 0xbf802be8 0x7a 787 #define TSP_CTRL_CPU_EN 0x0001 788 #define TSP_CTRL_SW_RST 0x0002 789 #define TSP_CTRL_DNLD_START 0x0004 790 #define TSP_CTRL_DNLD_DONE 0x0008 // See 0x78 for related information 791 #define TSP_CTRL_TSFILE_EN 0x0010 792 #define TSP_CTRL_R_PRIO 0x0020 793 #define TSP_CTRL_W_PRIO 0x0040 794 #define TSP_CTRL_ICACHE_EN 0x0100 795 #define TSP_CTRL_CPU2MI_R_PRIO 0x0400 796 #define TSP_CTRL_CPU2MI_W_PRIO 0x0800 797 #define TSP_CTRL_I_EL 0x0000 798 #define TSP_CTRL_I_BL 0x1000 799 #define TSP_CTRL_D_EL 0x0000 800 #define TSP_CTRL_D_BL 0x2000 801 #define TSP_CTRL_NOEA_QMEM_ACK_DIS 0x4000 802 #define TSP_CTRL_MEM_TS_WORDER 0x8000 803 804 REG16 TSP_SyncByte; // 0xbf802bec 0x7b 805 #define TSP_SYNC_BYTE_MASK 0x00FF 806 #define TSP_SYNC_BYTE_SHIFT 0 807 808 REG16 PKT_CNT; // 0xbf802bf0 0x7c 809 #define TSP_PKT_CNT_MASK 0x00FF 810 811 REG16 DBG_SEL; // 0xbf802bf4 0x7d 812 #define TSP_DBG_SEL_MASK 0xFFFF 813 #define TSP_DBG_SEL_SHIFT 0 814 815 REG16 HwInt_Stat; // 0xbf802bf8 0x7e 816 /* 817 7: audio/video packet error 818 6: DMA read done 819 5: HK_INT_FORCE. // it's trigure bit is at bank 15 44 bit[15] 820 4: TSP_FILE_RP meets TSP_FILE_TAIL. 821 3: TSP_FILE_RP meets TSP_FILE_MID. 822 2: HK_INT_FORCE. // it's trigure bit is at bank 15 39 bit[15] 823 1: STR2MI_WADR meets STR2MI_MID. 824 0: STR2MI_WADR meets STR2MI_TAIL." 825 */ 826 #define TSP_HWINT_EN_MASK 0x00FF // Tsp2hk_int enable bits. 827 #define TSP_HWINT_EN_SHIFT 0 828 #define TSP_HWINT_TSP_PVR_TAIL0_EN 0x0001 // currently not used in ISR 829 #define TSP_HWINT_TSP_PVR_MID0_EN 0x0002 // currently not used in ISR 830 #define TSP_HWINT_HW_PVR0_EN_MASK (TSP_HWINT_TSP_PVR_TAIL0_EN | TSP_HWINT_TSP_PVR_MID0_EN) 831 #define TSP_HWINT_TSP_HK_INT_FORCE_EN 0x0004 // currently not used in ISR 832 #define TSP_HWINT_TSP_FILEIN_MID_INT_EN 0x0008 // currently not used in ISR 833 #define TSP_HWINT_TSP_FILEIN_TAIL_INT_EN 0x0010 // currently not used in ISR 834 #define TSP_HWINT_TSP_SW_INT_EN 0x0020 835 #define TSP_HWINT_TSP_DMA_READ_DONE_EN 0x0040 // currently not used in ISR 836 #define TSP_HWINT_TSP_AV_PKT_ERR_EN 0x0080 // currently not used in ISR 837 #define TSP_HWINT_TSP_SUPPORT_ALL (TSP_HWINT_TSP_SW_INT_EN) 838 #define TSP_HWINT_ALL TSP_HWINT_TSP_SUPPORT_ALL 839 840 #define TSP_HWINT_STATUS_MASK 0xFF00 841 #define TSP_HWINT_STATUS_SHIFT 8 842 #define TSP_HWINT_TSP_PVR_TAIL0_STATUS 0x0100 843 #define TSP_HWINT_TSP_PVR_MID0_STATUS 0x0200 844 #define TSP_HWINT_HW_PVR0_STATUS_MASK (TSP_HWINT_TSP_PVR_TAIL0_STATUS | TSP_HWINT_TSP_PVR_MID0_STATUS) 845 #define TSP_HWINT_TSP_HK_INT_FORCE_STATUS 0x0400 846 #define TSP_HWINT_TSP_FILEIN_MID_INT_STATUS 0x0800 847 #define TSP_HWINT_TSP_FILEIN_TAIL_INT_STATUS 0x1000 848 #define TSP_HWINT_TSP_SW_INT_STATUS 0x2000 849 #define TSP_HWINT_TSP_DMA_READ_DONE 0x4000 850 #define TSP_HWINT_TSP_AV_PKT_ERR 0x8000 851 852 // following mask is merged with bank 15 7e(LOW BYTE) and bank 16 6c(HIGH BYTE) 853 #define TSP_HWINT_HW_PVR_ALL_MASK (TSP_HWINT_HW_PVR0_STATUS_MASK | TSP_HWINT_HW_PVR1_MASK) //@FIXME this is for all pvr interrupt but PVR 3 and 4 is not added 854 855 REG16 TSP_Ctrl1; // 0xbf802bfc 0x7f 856 // 0x7f: TSP_CTRL1: hidden in HwInt_Stat 857 #define TSP_CTRL1_FILEIN_TIMER_ENABLE 0x0001 858 #define TSP_CTRL1_TSP_FILE_NON_STOP 0x0002 //Set 1 to enable TSP file data read without timer check 859 #define TSP_CTRL1_FILEIN_PAUSE 0x0004 //Set 1 to pause file-in engine fetch data 860 #define TSP_CTRL1_FILE_CHECK_WP 0x0008 861 #define TSP_CTRL1_FILE_WP_SEL_MASK 0x0030 862 #define TSP_CTRL1_FILE_WP_FI 0x0010 863 #define TSP_CTRL1_FILE_WP_PVR 0x0020 864 #define TSP_CTRL1_STANDBY 0x0080 865 #define TSP_CTRL1_INT2NOEA 0x0100 866 #define TSP_CTRL1_INT2NOEA_FORCE 0x0200 867 #define TSP_CTRL1_FORCE_XIU_WRDY 0x0400 868 #define TSP_CTRL1_CMDQ_RESET 0x0800 869 #define TSP_CTRL1_DLEND_EN 0x1000 // Set 1 to enable little-endian mode in TSP CPU 870 #define TSP_CTRL1_PVR_CMD_QUEUE_ENABLE 0x2000 871 #define TSP_CTRL1_FILEIN_RADDR_READ 0x4000 872 #define TSP_CTRL1_DMA_RST 0x8000 873 874 //---------------------------------------------- 875 // 0xBF802C00 MIPS direct access 876 //---------------------------------------------- 877 REG32 MCU_Data0; // 0xbf802c00 0x00 878 #define TSP_MCU_DATA_ALIVE TSP_MCU_CMD_ALIVE 879 880 REG32 PVR1_LPcr1; // 0xbf802c08 0x02 881 REG32 LPcr2; // 0xbf802c10 0x04 882 883 REG16 reg160C; // 0xbf802c18 0x06 884 #define TSP_PVR1_LPCR1_WLD 0x0001 // Set 1 to load LPCR1 value (Default: 0) 885 #define TSP_PVR1_LPCR1_RLD 0x0002 // Set 1 to read LPCR1 value (Default: 1) 886 #define TSP_LPCR2_WLD 0x0004 // Set 1 to load LPCR2 value (Default: 0) 887 #define TSP_LPCR2_RLD 0x0008 // Set 1 to read LPCR2 value (Default: 1) 888 #define TSP_RECORD192_EN 0x0010 // 160C bit(5)enable TS packets with 192 bytes on record mode 889 #define TSP_FILEIN192_EN 0x0020 // 160C bit(5)enable TS packets with 192 bytes on file-in mode 890 #define TSP_ORZ_DMAW_PROT_EN 0x0080 // 160C bit(7) open RISC DMA write protection 891 #define TSP_CLR_PIDFLT_BYTE_CNT 0x0100 // Clear pidflt0_file byte counter 892 #define TSP_DOUBLE_BUF_DESC 0x4000 // 160d bit(6) remove buffer limitation, Force pinpong buffer to flush 893 #define TSP_TIMESTAMP_RESET 0x8000 // 160d bit(7) reset timestamp 894 895 REG16 reg160E; // 0xbf802c1C 0x07 896 #define TSP_VQTX0_BLOCK_DIS 0x0001 897 #define TSP_VQTX1_BLOCK_DIS 0x0002 898 #define TSP_VQTX2_BLOCK_DIS 0x0004 899 #define TSP_VQTX3_BLOCK_DIS 0x0008 900 #define TSP_DIS_MIU_RQ 0x0010 // Disable miu R/W request for reset TSP usage 901 #define TSP_RM_DMA_GLITCH 0x0080 // Fix sec_dma overflow glitch 902 #define TSP_RESET_VFIFO 0x0100 // Reset VFIFO -- ECO Done 903 #define TSP_RESET_AFIFO 0x0200 // Reset AFIFO -- ECO Done 904 #define TSP_RESET_AFIFO3 0x0400 // Reset AFIFOC -- ECO Done 905 #define TSP_CLR_ALL_FLT_MATCH 0x0800 // Set 1 to clean all flt_match in a packet 906 #define TSP_RESET_AFIFO2 0x1000 907 #define TSP_RESET_VFIFO3D 0x2000 908 #define TSP_PVR_WPRI_HIGH 0x4000 909 #define TSP_OPT_ORACESS_TIMING 0x8000 910 911 REG16 PktChkSizeFilein; // 0xbf802c20 0x08 912 #define TSP_PKT_SIZE_MASK 0x00ff 913 #define TSP_PKT192_BLK_DIS_FIN 0x0100 // Set 1 to disable file-in timestamp block scheme 914 #define TSP_AV_CLR 0x0200 // Clear AV FIFO overflow flag and in/out counter 915 #define TSP_HW_STANDBY_MODE 0x0400 // Set 1 to disable all SRAM in TSP for low power mode automatically 916 #define TSP_RESET_AFIFO4 0x4000 // Reset AFIFOC -- ECO Done 917 918 REG16 TSP_Cfg5; // 0xbf802c24 0x09 919 #define TSP_PREVENT_OVF_META 0x0001 920 #define TSP_OVF_META_SEL 0x0004 921 #define TSP_SYSTIME_MODE 0x0008 922 #define TSP_SEC_DMA_BURST_EN 0x0080 // Enable Section DMA burst 923 924 REG16 Dnld_AddrH; // 0xbf802c28 0x0a 925 #define TSP_DMA_RADDR_MSB_MASK 0x00FF 926 #define TSP_DMA_RADDR_MSB_SHIFT 0 927 928 REG16 TSP_Ctrl2; // 0xbf802c2c 0x0b 929 #define TSP_CMQ_WORD_EN 0x0040 // Set 1 to access CMDQ related registers in word. 930 #define TSP_AV_DIRECT_STOP 0x0080 //Set 1 to enable A/V fifo full pull back tsif0 file in 931 #define TSP_AV_DIRECT_STOP1 0x0100 //Set 1 to enable A/V fifo full pull back tsif1 file in 932 #define TSP_AV_DIRECT_STOP2 0x0200 //Set 1 to enable A/V fifo full pull back tsif2 file in 933 #define TSP_AV_DIRECT_STOP3 0x0400 //Set 1 to enable A/V fifo full pull back tsif3 file in 934 #define TSP_TS_OUT_EN 0x1000 // TS_CB out enable. for Serial input to parallel output 935 #define TSP_PS_VID_3D_EN 0x2000 //Set 1 to enable video 3D path in program stream mode 936 937 REG32 TsPidScmbStatTsin; // 0xbf802c30 0x0c 938 REG32 TsPidScmbStatFile; // 0xbf802c38 0x0e 939 940 REG32 PCR64_2_L; // 0xbf802c40 0x10 941 REG32 PCR64_2_H; // 0xbf802c48 0x12 942 #define TSP_DMAW_BND_MASK 0xFFFFFFFFUL 943 944 REG32 DMAW_LBND0; // 0xbf802c50 0x14 //sec1 protect 945 REG32 DMAW_UBND0; // 0xbf802c58 0x16 946 REG32 DMAW_LBND1; // 0xbf802c60 0x18 //sec2 protect 947 REG32 DMAW_UBND1; // 0xbf802c68 0x1A 948 949 REG32 HW2_CFG6; // 0xbf802c68 0x1C 950 REG32 HW2_CFG5; // 0xbf802c68 0x1E 951 952 REG32 VQ0_BASE; // 0xbf802c80 0x20 953 REG16 VQ0_SIZE; // 0xbf802c84 0x22 954 #define TSP_VQ0_SIZE_208PK_MASK 0xFFFF 955 #define TSP_VQ0_SIZE_208PK_SHIFT 0 956 957 REG16 VQ0_CTRL; // 0xbf802c88 0x23 958 #define TSP_VQ0_WR_THRESHOLD_MASK 0x000F 959 #define TSP_VQ0_WR_THRESHOLD_SHIFT 0 960 #define TSP_VQ0_PRIORTY_THRESHOLD_MASK 0x00F0 961 #define TSP_VQ0_PRIORTY_THRESHOL_SHIFT 4 962 #define TSP_VQ0_FORCE_FIRE_CNT_1K_MASK 0x0F00 963 #define TSP_VQ0_FORCE_FIRE_CNT_1K_SHIFT 8 964 #define TSP_VQ0_RESET 0x1000 965 #define TSP_VQ0_OVERFLOW_INT_EN 0x4000 // Enable the interrupt for overflow happened on Virtual Queue path 966 #define TSP_VQ0_CLR_OVERFLOW_INT 0x8000 // Clear the interrupt and the overflow flag 967 968 REG16 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 969 970 #define TSP_REQ_VQ_RX_THRESHOLD_MASKE 0x000E 971 #define TSP_REQ_VQ_RX_THRESHOLD_SHIFT 1 972 #define TSP_REQ_VQ_RX_THRESHOLD_LEN1 0x0000 973 #define TSP_REQ_VQ_RX_THRESHOLD_LEN2 0x0002 974 #define TSP_REQ_VQ_RX_THRESHOLD_LEN4 0x0004 975 #define TSP_REQ_VQ_RX_THRESHOLD_LEN8 0x0006 976 #define TSP_PIDFLT0_OVF_INT_EN 0x0040 977 #define TSP_PIDFLT0_CLR_OVF_INT 0x0080 978 #define TSP_PIDFLT1_OVF_INT_EN 0x0100 979 #define TSP_PIDFLT1_CLR_OVF_INT 0x0200 980 #define TSP_PIDFLT2_OVF_INT_EN 0x0400 981 #define TSP_PIDFLT2_CLR_OVF_INT 0x0800 982 983 REG16 _xbf202c94 ; // 0xbf802c94 0x25 984 985 REG16 MOBF_PVR1_Index[2]; // 0xbf3a2c98 0x26 986 #define TSP_MOBF_PVR1_INDEX_MASK 0x0000001F 987 #define TSP_MOBF_PVR1_INDEX_SHIFT 0 988 REG16 MOBF_PVR2_Index[2]; // 0xbf3a2cA0 0x28 989 #define TSP_MOBF_PVR2_INDEX_MASK 0x0000001F 990 #define TSP_MOBF_PVR2_INDEX_SHIFT 0 991 992 REG32 DMAW_LBND2; // 0xbf802ca8 0x2a //PVR protect 993 #define TSP_PVR_MASK 0x0FFFFFFFUL 994 REG32 DMAW_UBND2; // 0xbf802cb0 0x2c 995 REG32 DMAW_LBND3; // 0xbf802cb8 0x2e //PVR 2 protect 996 REG32 DMAW_UBND3; // 0xbf802cc0 0x30 997 REG32 DMAW_LBND4; // 0xbf802cc8 0x32 //PVR 3 protect 998 REG32 DMAW_UBND4; // 0xbf802cd0 0x34 999 1000 REG32 ORZ_DMAW_LBND; // 0xbf802cd8 0x36 //CPU protect 1001 #define TSP_ORZ_DMAW_LBND_MASK 0xffffffffUL //protect address is base on MIU unit (16byte aligment) 1002 REG32 ORZ_DMAW_UBND; // 0xbf802ce0 0x38 1003 #define TSP_ORZ_DMAW_UBND_MASK 0xffffffffUL 1004 1005 REG16 PIDFLT_PCR0; // 0xbf802ce8 0x3a 1006 #define TSP_PIDFLT_PCR0_PID_MASK 0x1fff 1007 #define TSP_PIDFLT_PCR0_EN 0x8000 1008 1009 REG16 PIDFLT_PCR1; // 0xbf802ce8 0x3b 1010 #define TSP_PIDFLT_PCR1_PID_MASK 0x1fff 1011 #define TSP_PIDFLT_PCR1_EN 0x8000 1012 1013 REG32 HWPCR0_L; // 0xbf802cf0 0x3c 1014 REG32 HWPCR0_H; // 0xbf802cf8 0x3e 1015 1016 REG32 CA_CTRL; // 0xbf802d00 0x40 1017 #define TSP_CA_CTRL_MASK 0xffffffff 1018 #define TSP_CA0_INPUT_TSIF0_LIVEIN 0x00000001 1019 #define TSP_CA0_INPUT_TSIF0_FILEIN 0x00000002 1020 #define TSP_CA0_INPUT_TSIF1 0x00000004 1021 #define TSP_CA0_AVPAUSE 0x00000008 1022 #define TSP_CA0_OUTPUT_PKTDMX0_LIVE 0x00000010 1023 #define TSP_CA0_OUTPUT_PKTDMX0_FILE 0x00000020 1024 #define TSP_CA0_OUTPUT_PKTDMX1 0x00000040 //pkt_demux1 1025 #define TSP_CA0_INPUT_TSIF2 0x00001000 1026 #define TSP_CA0_OUTPUT_PKTDMX2 0x00002000 //pkt_demux2 1027 #define TSP_CA2_INPUT_TSIF2 0x00100000 1028 #define TSP_CA2_OUTPUT_REC2 0x00200000 //pkt_demux2 1029 #define TSP_CA2_INPUT_TSIF0_LIVEIN 0x01000000 1030 #define TSP_CA2_INPUT_TSIF0_FILEIN 0x02000000 1031 #define TSP_CA2_INPUT_TSIF1 0x04000000 1032 #define TSP_CA2_OUTPUT_PLAY_LIVE 0x10000000 1033 #define TSP_CA2_OUTPUT_PLAY_FILE 0x20000000 1034 #define TSP_CA2_OUTPUT_REC1 0x40000000 //pkt_demux1 1035 1036 REG16 OneWay; // 0xbf802d08 0x42 , 1037 #define TSP_ONEWAY_CAREC_DISABLE 0x0001 1038 #define TSP_ONEWAY_PVR 0x0002 1039 #define TSP_ONEWAY_PVR1 0x0004 1040 #define TSP_ONEWAY_FW 0x0008 1041 #define TSP_ONEWAY_QMEM 0x0010 1042 #define TSP_ONEWAY_PVR2 0x0020 1043 #define TSP_ONEWAY_FIQ 0x0040 1044 1045 REG16 _xbf202d0C; // 0xbf802d0C 0x43 1046 1047 REG32 HWPCR1_L; // 0xbf802d10 0x44 1048 REG32 HWPCR1_H; // 0xbf802d18 0x46 1049 1050 REG16 IND32_CMD; // 0xbf802d20 0x48 1051 REG32 IND32_ADDR; // 0xbf802d24 0x49, Indirect address to TSP CPU 1052 REG32 IND32_WDATA; // 0xbf802d2C 0x4B, Indirect write data to TSP CPUr 1053 REG32 IND32_RDATA; // 0xbf802d34 0x4D, IND32_WDATA 1054 1055 REG16 _xbf202d3c; // 0xbf802d3C 0x4F 1056 1057 REG16 FIFO_Src; // 0xbf802d40 0x50 1058 #define TSP_AUD_SRC_MASK 0x0007 1059 #define TSP_AUD_SRC_SHIFT 0 1060 #define TSP_AUDB_SRC_MASK 0x0038 1061 #define TSP_AUDB_SRC_SHIFT 3 1062 #define TSP_VID_SRC_MASK 0x01C0 1063 #define TSP_VID_SRC_SHIFT 6 1064 #define TSP_VID3D_SRC_MASK 0x0E00 1065 #define TSP_VID3D_SRC_SHIFT 9 1066 #define TSP_PVR1_SRC_MASK 0x7000 1067 #define TSP_PVR1_SRC_SHIFT 12 1068 #define TSP_PVR2_SRC_MASK_L 0x8000 1069 #define TSP_PVR2_SRC_SHIFT_L 15 1070 1071 REG16 PCR_Cfg; // 0xbf802d44 0x51 1072 #define TSP_PVR2_SRC_MASK_H 0x0003 1073 #define TSP_PVR2_SRC_SHIFT_H 0 1074 #define TSP_AUDC_SRC_MASK 0x001C 1075 #define TSP_AUDC_SRC_SHIFT 2 1076 #define TSP_AUDD_SRC_MASK 0x00E0 1077 #define TSP_AUDD_SRC_SHIFT 5 1078 #define TSP_TEI_SKIP_PKT_PCR0 0x0100 1079 #define TSP_PCR0_RESET 0x0200 1080 #define TSP_PCR0_INT_CLR 0x0400 1081 #define TSP_PCR0_READ 0x0800 1082 #define TSP_TEI_SKIP_PKT_PCR1 0x1000 1083 #define TSP_PCR1_RESET 0x2000 1084 #define TSP_PCR1_INT_CLR 0x4000 1085 #define TSP_PCR1_READ 0x8000 1086 1087 REG32 STC_DIFF_BUF; // 0xbf802d48 0x52 1088 1089 REG32 STC_DIFF_BUF_H; // 0xbf802d50 0x54 1090 #define TSP_STC_DIFF_BUF_H_MASK 0x0000000F 1091 #define TSP_STC_DIFF_BUF_H_AHIFT 0 1092 1093 REG32 VQ1_Base; // 0xbf802d58 0x56 1094 1095 REG32 _xbf202d60_6C[2]; // 0xbf802d60 0x58~0x5B 1096 1097 REG16 VQ1_Size; // 0xbf802d70 0x5C 1098 #define TSP_VQ1_SIZE_208PK_MASK 0xffff 1099 #define TSP_VQ1_SIZE_208PK_SHIFT 0 1100 1101 REG16 VQ1_Config; // 0xbf802d74 0x5d 1102 #define TSP_VQ1_WR_THRESHOLD_MASK 0x000F 1103 #define TSP_VQ1_WR_THRESHOLD_SHIFT 0 1104 #define TSP_VQ1_PRI_THRESHOLD_MASK 0x00F0 1105 #define TSP_VQ1_PRI_THRESHOLD_SHIFT 4 1106 #define TSP_VQ1_FORCEFIRE_CNT_1K_MASK 0x0F00 1107 #define TSP_VQ1_FORCEFIRE_CNT_1K_SHIFT 8 1108 #define TSP_VQ1_RESET 0x1000 1109 #define TSP_VQ1_OVF_INT_EN 0x4000 1110 #define TSP_VQ1_CLR_OVF_INT 0x8000 1111 1112 REG32 VQ2_Base; // 0xbf802d78 0x5E 1113 1114 REG32 TS_WatchDog_Cnt; // 0xbf802d80 0x60 1115 #define TSP_TS_WATCH_DOG_MASK 0xFFFF0000 1116 #define TSP_TS_WATCH_DOG_SHIFT 16 1117 1118 REG32 Bist_Fail; // 0xbf802d88 0x62 1119 #define TSP_BIST_FAIL_STATUS_MASK 0x00FF0000 1120 #define TSP_BIST_FAIL_STATUS_SRAM1P192x8_MASK 0x00070000 1121 #define TSP_BIST_FAIL_STATUS_SRAM2P512x32w8 0x00080000 1122 #define TSP_BIST_FAIL_STATUS_SRAM2P16x128_MASK 0x00600000 1123 #define TSP_BIST_FAIL_STATUS_SRAM1P2048x32w8 0x00800000 1124 #define TSP_BIST_FAIL_STATUS_SRAM1P1024x32w8 0x01000000 1125 #define TSP_BIST_FAIL_STATUS_SRAM1P512x20 0x00200000 1126 1127 REG16 VQ2_Size; // 0xbf802d90 0x64 1128 #define TSP_VQ2_SIZE_208PK_MASK 0xffff 1129 #define TSP_VQ2_SIZE_208PK_SHIFT 0 1130 1131 REG16 VQ2_Config; // 0xbf802d90 0x65 1132 #define TSP_VQ2_WR_THRESHOLD_MASK 0x000F 1133 #define TSP_VQ2_WR_THRESHOLD_SHIFT 0 1134 #define TSP_VQ2_PRI_THRESHOLD_MASK 0x00F0 1135 #define TSP_VQ2_PRI_THRESHOLD_SHIFT 4 1136 #define TSP_VQ2_FORCEFIRE_CNT_1K_MASK 0x0F00 1137 #define TSP_VQ2_FORCEFIRE_CNT_1K_SHIFT 8 1138 #define TSP_VQ2_RESET 0x1000 1139 #define TSP_VQ2_OVF_INT_EN 0x4000 1140 #define TSP_VQ2_CLR_OVF_INT 0x8000 1141 1142 REG32 VQ_STATUS; // 0xbf802d98 0x66 1143 #define TSP_VQ_STATUS_MASK 0xFFFFFFFF 1144 #define TSP_VQ_STATUS_SHIFT 0 1145 #define TSP_VQ0_STATUS_READ_EVER_FULL 0x00001000 1146 #define TSP_VQ0_STATUS_READ_EVER_OVERFLOW 0x00002000 1147 #define TSP_VQ0_STATUS_EMPTY 0x00004000 1148 #define TSP_VQ0_STATUS_READ_BUSY 0x00008000 1149 #define TSP_VQ1_STATUS_READ_EVER_FULL 0x00010000 1150 #define TSP_VQ1_STATUS_READ_EVER_OVERFLOW 0x00020000 1151 #define TSP_VQ1_STATUS_EMPTY 0x00040000 1152 #define TSP_VQ1_STATUS_READ_BUSY 0x00080000 1153 #define TSP_VQ2_STATUS_READ_EVER_FULL 0x00100000 1154 #define TSP_VQ2_STATUS_READ_EVER_OVERFLOW 0x00200000 1155 #define TSP_VQ2_STATUS_EMPTY 0x00400000 1156 #define TSP_VQ2_STATUS_READ_BUSY 0x00800000 1157 #define TSP_VQ0_STATUS_TX_OVERFLOW 0x10000000 1158 #define TSP_VQ1_STATUS_TX_OVERFLOW 0x20000000 1159 #define TSP_VQ2_STATUS_TX_OVERFLOW 0x40000000 1160 1161 REG32 DM2MI_WAddr_Err; // 0xbf802da0 0x68 , DM2MI_WADDR_ERR0 1162 1163 REG32 ORZ_DMAW_WAddr_Err; // 0xbf802da8 0x6a , ORZ_WADDR_ERR0 1164 1165 REG16 HwInt2_Stat; // 0xbf802dB0 0x6c 1166 /* 1167 [7] : PVR2 meet_tail or PVR2_meet_mid 1168 [6] : vq0, vq1, vq2, vq3 overflow interrupt 1169 [5] : all DMA write address not in the protect zone interrupt 1170 [4] : PVR_cb meet the mid or PVR_cb meet the tail 1171 [3] : pcr filter 0 update finish 1172 [2] : pcr filter 1 update finish 1173 [1] : OTV HW interrupt 1174 [0] : reserved 1175 */ 1176 #define TSP_HWINT2_EN_MASK 0x00FF 1177 #define TSP_HWINT2_EN_SHIFT 0 1178 #define TSP_HWINT2_OTV_EN 0x0002 1179 #define TSP_HWINT2_PCR1_UPDATE_END_EN 0x0004 1180 #define TSP_HWINT2_PCR0_UPDATE_END_EN 0x0008 1181 #define TSP_HWINT2_ALL_DMA_WADDR_NOT_IN_PROCT_Z_EN 0x0020 1182 #define TSP_HWINT2_VQ0_VQ1_VQ2_VQ3_OVERFLOW_EN 0x0040 1183 #define TSP_HWINT2_PVR2_MID_TAIL_STATUS_EN 0x0080 1184 #define TSP_HWINT_PVR (TSP_HWINT2_PVR2_MID_TAIL_STATUS_EN) //@FIXME check what is this doing 1185 #define TSP_HWINT2_SUPPORT_ALL (TSP_HWINT2_PCR0_UPDATE_END_EN|TSP_HWINT2_PCR1_UPDATE_END_EN|TSP_HWINT2_OTV_EN) 1186 #define TSP_HWINT2_ALL TSP_HWINT2_SUPPORT_ALL 1187 1188 #define TSP_HWINT2_STATUS_MASK 0xFF00 1189 #define TSP_HWINT2_STATUS_SHIFT 8 1190 #define TSP_HWINT2_OTV 0x0200 1191 #define TSP_HWINT2_PCR1_UPDATE_END 0x0400 1192 #define TSP_HWINT2_PCR0_UPDATE_END 0x0800 1193 #define TSP_HWINT2_ALL_DMA_WADDR_NOT_IN_PROCT_Z 0x2000 1194 #define TSP_HWINT2_VQ0_VQ1_VQ2_VQ3_OVERFLOW 0x4000 1195 #define TSP_HWINT2_PVR2_MID_TAIL_STATUS 0x8000 1196 1197 REG32 SwInt2_Stat; // 0xbf802dB4 0x6d 1198 REG16 HwInt3_Stat; // 0xbf802dBC 0x6f 1199 /* 1200 [7:2] : reserved 1201 [1] : pcr filter 3 update finish 1202 [0] : pcr filter 2 update finish 1203 */ 1204 #define TSP_HWINT3_EN_MASK 0x00FF 1205 #define TSP_HWINT3_EN_SHIFT 0 1206 #define TSP_HWINT3_PCR2_UPDATE_END_EN 0x0001 1207 #define TSP_HWINT3_PCR3_UPDATE_END_EN 0x0002 1208 #define TSP_HWINT3_SUPPORT_ALL (TSP_HWINT3_PCR2_UPDATE_END_EN|TSP_HWINT3_PCR3_UPDATE_END_EN) 1209 #define TSP_HWINT3_ALL TSP_HWINT3_SUPPORT_ALL 1210 1211 #define TSP_HWINT3_STATUS_MASK 0xFF00 1212 #define TSP_HWINT3_STATUS_SHIFT 8 1213 #define TSP_HWINT3_PCR2_UPDATE_END 0x0100 1214 #define TSP_HWINT3_PCR3_UPDATE_END 0x0200 1215 1216 REG32 TimeStamp_FileIn; // 0xbf802dC0 0x70 1217 1218 REG16 HW2_Config3; // 0xbf802dC8 0x72 1219 #define TSP_PVR_DMAW_PROTECT_EN 0x0001 1220 #define TSP_WADDR_ERR_SRC_SEL_MASK 0x0006 1221 #define TSP_WADDR_ERR_SRC_SEL_SHIFT 1 1222 #define TSP_WADDR_ERR_SRC_PVR 0x0000 1223 #define TSP_WADDR_ERR_SRC_VQ 0x0002 1224 #define TSP_WADDR_ERR_SRC_SEC_CB 0x0004 1225 #define TSP_RM_OVF_GLITCH 0x0008 1226 #define TSP_FILEIN_RADDR_READ 0x0010 1227 #define TSP_DUP_PKT_CNT_CLR 0x0040 1228 #define TSP_DMA_FLUSH_EN 0x0080 //PVR1, PVR2 dma flush 1229 #define TSP_REC_AT_SYNC_DIS 0x0100 1230 #define TSP_PVR1_ALIGN_EN 0x0200 1231 #define TSP_REC_FORCE_SYNC_EN 0x0400 1232 #define TSP_RM_PKT_DEMUX_PIPE 0x0800 1233 #define TSP_VQ_EN 0x4000 1234 #define TSP_VQ2PINGPONG_EN 0x8000 1235 1236 REG16 PVRConfig; // 0xbf802dCC 0x73 1237 #define TSP_PVR1_REC_ALL_EN 0x0001 1238 #define TSP_PVR2_REC_ALL_EN 0x0002 1239 #define TSP_REC_NULL 0x0004 1240 #define TSP_REC_ALL_OLD 0x0008 1241 #define TSP_MATCH_PID_SEL_MASK 0x0700 1242 #define TSP_MATCH_PID_SEL_SHIFT 8 1243 #define TSP_MATCH_PID_LD 0x8000 1244 1245 REG32 VQ3_Base; // 0x74~75 1246 REG16 VQ3_Size; // 0x76 1247 #define TSP_VQ3_SIZE_208PK_MASK 0xffff 1248 #define TSP_VQ3_SIZE_208PK_SHIFT 0 1249 1250 REG16 VQ3_Config; //0x77 1251 #define TSP_VQ3_WR_THRESHOLD_MASK 0x000F 1252 #define TSP_VQ3_WR_THRESHOLD_SHIFT 0 1253 #define TSP_VQ3_PRI_THRESHOLD_MASK 0x00F0 1254 #define TSP_VQ3_PRI_THRESHOLD_SHIFT 4 1255 #define TSP_VQ3_FORCEFIRE_CNT_1K_MASK 0x0F00 1256 #define TSP_VQ3_FORCEFIRE_CNT_1K_SHIFT 8 1257 #define TSP_VQ3_RESET 0x1000 1258 #define TSP_VQ3_OVF_INT_EN 0x4000 1259 #define TSP_VQ3_CLR_OVF_INT 0x8000 1260 1261 REG32 VQ_RX_Status; // 0xbf802de0 0x78 1262 #define VQ_RX_ARBITER_MODE_MASK 0x0000000F 1263 #define VQ_RX_ARBITER_MODE_SHIFT 0 1264 #define VQ_RX0_PRI_MASK 0x000000F0 1265 #define VQ_RX0_PRI_SHIFT 4 1266 #define VQ_RX1_PRI_MASK 0x00000F00 1267 #define VQ_RX1_PRI_SHIFT 8 1268 #define VQ_RX2_PRI_MASK 0x0000F000 1269 #define VQ_RX2_PRI_SHIFT 12 1270 1271 REG32 _xbf802de8; // 0xbf802dC0 0x7a 1272 1273 REG32 MCU_Data1; // 0xbf802dC0 0x7c 1274 } REG_Ctrl; 1275 1276 //TSP 3 1277 typedef struct _REG_Ctrl2 //TSP3 0x1702 1278 { 1279 REG16 CFG_00; // 0x00 1280 #define CFG_00_TSP_FILE_IN_TSIF1_EN 0x0001 //Set 1: Enable FILE_input 1281 #define CFG_00_MEM_TS_DATA_ENDIAN_TSIF1 0x0002 //Set 1 to swap the byte order of TSIF1 DMA DATA bus 1282 #define CFG_00_TSP_FILE_SEGMENT_TSIF1 0x0004 1283 #define CFG_00_FILEIN_RADDR_READ_TSIF1 0x0008 //Read file DMA read address 1284 #define CFG_00_MEM_TS_W_ORDER_TSIF1 0x0010 //Set 1 to swap the word order of TSIF1 MIU DATA bus 1285 #define CFG_00_DIS_MIU_RQ_TSIF1 0x0020 //Disable the MIU request 1286 #define CFG_00_RST_TS_FIN1 0x0040 //reset TSIF1 1287 #define CFG_00_RST_FILEIN_TSIF1 0x0080 //reset the TSIF1 file in path 1288 #define CFG_00_RST_CMDQ_FILEIN_TSIF1 0x0100 //reset the file in TSIF1 command queue 1289 #define CFG_00_WB_RST_FILEIN_TSIF1 0x0200 //reset DMA to TSIF FSM in TSP clock Domain 1290 #define CFG_00_RST_WB_DMA_FILEIN_TSIF1 0x0400 //reset TSIF1 DMA in TSP clock Domain 1291 #define CFG_00_FILE2MI_PRI_TSIF1 0x0800 //Set 1: Higher MIU ABT read priority 1292 #define CFG_00_RST_READ_DMA_1 0x1000 //reset TSIF1 DMA in MIU clock Domain 1293 #define CFG_00_LPCR2_LOAD_TSIF1 0x2000 //Load lpcr2 from TSIF1 90k counter 1294 #define CFG_00_LPCR2_LOAD_BUF1 0x4000 //Load lpcr2 from pdflt1_buffer 90k counter 1295 #define CFG_00_LPCR2_LOAD_BUF0 0x8000 //Load lpcr2 from pdflt0_buffer 90k counter 1296 REG16 CFG_01; // 0x01 1297 #define CFG_01_TSP_FILE_SEGMENT1 0x0001 1298 #define CFG_01_TIMER_EN1 0x0002 //1: enable byte delay timer for TSIF1 filein path 0: packet delay timer 1299 #define CFG_01_PKT192_EN1 0x0004 //Set 1 to enable TS packets with 192 bytes on file-in mode. (Blocking TS packets by timestamp) 1300 #define CFG_01_PKT192_BLK_DISABLE1 0x0008 //Set 1 to disable file-in timestamp block scheme 1301 #define CFG_01_LPCR2_WLD1 0x0010 //Set PCR to TSIF1 90k counter 1302 #define CFG_01_TS_DATA_PORT_SEL1 0x0020 //TSIF1 data port output select. 0: select live TS to be TSIF output 1: select data port to be TSIF output 1303 #define CFG_01_PDFLT2_FILE_SRC 0x00c0 //00:disable 01:tsif0 file in port 10:tsif1 file in port 11:disable 1304 #define CFG_01_PDFLT2_FILE_SRC_SHIFT 6 1305 1306 #define CFG_01_PCR0_SRC_MASK 0x0f00 1307 #define CFG_01_PCR0_SRC_SHIFT 8 1308 #define CFG_01_PCR0_SRC_TSIF0 0x0 1309 #define CFG_01_PCR0_SRC_TSIF1 0x1 1310 #define CFG_01_PCR0_SRC_TSIF2 0x2 1311 #define CFG_01_PCR0_SRC_TSIF3 0x3 1312 #define CFG_01_PCR0_SRC_TSIF4 0x4 1313 #define CFG_01_PCR0_SRC_TSIF5 0x5 1314 #define CFG_01_PCR0_SRC_PKT_MERGE0 0x8 1315 #define CFG_01_PCR0_SRC_PKT_MERGE1 0x9 1316 #define CFG_01_PCR0_SRC_MM_FILEIN0 0xa 1317 #define CFG_01_PCR0_SRC_MM_FILEIN1 0xb 1318 #define CFG_01_PCR0_SRC_FIQ0 0xc 1319 #define CFG_01_PCR0_SRC_FIQ1 0xd 1320 1321 #define CFG_01_PCR1_SRC_MASK 0xf000 1322 #define CFG_01_PCR1_SRC_SHIFT 12 1323 #define CFG_01_PCR1_SRC_TSIF0 0x0 1324 #define CFG_01_PCR1_SRC_TSIF1 0x1 1325 #define CFG_01_PCR1_SRC_TSIF2 0x2 1326 #define CFG_01_PCR1_SRC_TSIF3 0x3 1327 #define CFG_01_PCR1_SRC_TSIF4 0x4 1328 #define CFG_01_PCR1_SRC_TSIF5 0x5 1329 #define CFG_01_PCR1_SRC_PKT_MERGE0 0x8 1330 #define CFG_01_PCR1_SRC_PKT_MERGE1 0x9 1331 #define CFG_01_PCR1_SRC_MM_FILEIN0 0xa 1332 #define CFG_01_PCR1_SRC_MM_FILEIN1 0xb 1333 #define CFG_01_PCR1_SRC_FIQ0 0xc 1334 #define CFG_01_PCR1_SRC_FIQ1 0xd 1335 REG16 CFG_02; 1336 #define CFG_02_PKT_CHK_SIZE_FIN1 0x00ff //(Packet Size - 1) for sync detection in TSIF1 1337 #define CFG_02_PKT_DEMUX_SIZE_1 0xff00 //(Packet Size - 1) for sync detection in pkt_demux1 1338 #define CFG_02_PKT_DEMUX_SIZE_1_SHIFT 8 1339 REG16 CFG_03; 1340 #define CFG_03_TSP_FILE_TIMER1 0xffff //Bit [15:0] of timer threshold for TS file playback data fetch from MIU. 1341 REG16 CFG_04; 1342 #define CFG_04_TSP_FILEIN_ABORT_ECO_TSIF0 0x0001 1343 #define CFG_04_TSP_FILEIN_ABORT_ECO_TSIF1 0x0002 1344 #define CFG_04_TSP_FILEIN_ABORT_ECO_TSIF2 0x0004 1345 #define CFG_04_TSP_FILEIN_ABORT_ECO_TSIF3 0x0008 1346 REG16 CFG_05; 1347 #define CFG_05_TSP_FILEIN_TSIF2 0x0001 //Set 1 to swap the word order of TSIF2 MIU DATA bus 1348 #define CFG_05_MEM_TS_DATA_EDIAN_TSIF2 0x0002 //Set 1 to swap the byte order of TSIF2 DMA DATA bus 1349 #define CFG_05_TSP_FILE_SEGMENT_TSIF2 0x0004 //set 0 to enable file in alignment mdoe 1350 #define CFG_05_FILEIN_RDDR_READ_TSIF2 0x0008 //Read file DMA read address 1351 #define CFG_05_MEM_TS_W_ORDER_TSIF2 0x0010 //Set 1: Enable FILE_input 1352 #define CFG_05_DIS_MIU_RQ_TSIF2 0x0020 //Disable the MIU request 1353 #define CFG_05_RST_TS_FIN2 0x0040 //reset TSIF2 1354 #define CFG_05_RST_FILEIN_TSIF2 0x0080 //reset the TSIF2 file in path 1355 #define CFG_05_RST_CMDQ_FILEIN_TSIF2 0x0100 //reset the file in TSIF2 command queue 1356 #define CFG_05_WB_RST_FILEIN_TSIF2 0x0200 //reset DMA to TSIF FSM in TSP clock Domain 1357 #define CFG_05_RST_WB_DMA_FILEIN_TSIF2 0x0400 //reset TSIF2 DMA in TSP clock Domain 1358 #define CFG_05_FILE2MI_PRI_TSIF2 0x0800 //Set 1: Higher MIU ABT read priority 1359 #define CFG_05_RST_READ_DMA_2 0x1000 //reset TSIF1 DMA in MIU clock Domain 1360 #define CFG_05_LPCR2_LOAD_TSIF2 0x2000 //Load lpcr2 from TSIF2 90k counter 1361 #define CFG_05_LPCR2_LOAD_BUF2 0x4000 //Load lpcr2 from pdflt2_buffer 90k counter 1362 REG16 CFG_06; 1363 #define CFG_06_TSP_FILE_SEGMENT2 0x0001 //set 0 to enable file in alignment mdoe 1364 #define CFG_06_TSP_TIMER_EN2 0x0002 //1: enable byte delay timer for TSIF2 filein path 0: packet delay timer 1365 #define CFG_06_TSP_PKT192_EN2 0x0004 //Set 1 to enable TS packets with 192 bytes on file-in mode. (Blocking TS packets by timestamp) 1366 #define CFG_06_TSP_PKT192_BLK_DISABLE2 0x0008 //Set 1 to disable file-in timestamp block scheme 1367 #define CFG_06_LPCR2_WLD2 0x0010 //Set PCR to TSIF2 90k counter 1368 #define CFG_06_TS_DATA_PORT_SEL2 0x0020 //TSIF2 data port output select. 0: select live TS to be TSIF output 1: select data port to be TSIF output 1369 #define CFG_06_PIDFLT5_FILE_SRC 0x00C0 //pdflt5 file in source 00:disable 01:tsif2 file in port 10:tsif3 file in port 11:disable 1370 #define CFG_06_PIDFLT5_FILE_SRC_SHIFT 6 1371 #define CFG_06_PCR0_ID_SEL 0x0700 //pkt merge multi-stream id select 0: stream 0 1: stream 1 2: stream 2 3: stream 3 1372 #define CFG_06_PCR0_ID_SEL_SHFIT 8 1373 #define CFG_06_PCR1_ID_SEL 0x3800 //pkt merge multi-stream id select 0: stream 0 1: stream 1 2: stream 2 3: stream 3 1374 #define CFG_06_PCR1_ID_SEL_SHFIT 11 1375 REG16 CFG_07; 1376 #define CFG_07_PKT_CHK_SIZE_FIN2 0x00ff //(Packet Size �V 1) for sync detection in TSIF2 1377 #define CFG_07_PKTDMX_SIZE2 0xff00 //(Packet Size �V 1) for sync detection in pkt_demux2 1378 #define CFG_07_PKTDMX_SIZE2_SHIFT 8 1379 REG16 CFG_08; 1380 #define CFG_08_TSP_FILE_TIMER2 0x00ff 1381 REG16 CFG_09; // reserved 1382 REG16 CFG_0A; 1383 #define CFG_0A_TSP_FILE_IN_TSIF3 0x0001 //Set 1: Enable FILE_input 1384 #define CFG_0A_MEM_TS_DATA_EDIAN_TSIF3 0x0002 //Set 1 to swap the byte order of TSIF3 DMA DATA bus 1385 #define CFG_0A_TSP_FILE_SEGMENT_TSIF3 0x0004 //set 0 to enable file in alignment mdoe 1386 #define CFG_0A_FILEIN_RADDR_READ_TSIF3 0x0008 //Read file DMA read address 1387 #define CFG_0A_MEM_TS_W_ORDER_TSIF3 0x0010 //Set 1: Enable FILE_input 1388 #define CFG_0A_DIS_MIU_RQ_TSIF3 0x0020 //Set 1 to swap the byte order of TSIF3 DMA DATA bus 1389 #define CFG_0A_RST_TS_FIN3 0x0040 //set 0 to enable file in alignment mdoe 1390 #define CFG_0A_RST_FILEIN_TSIF3 0x0080 //Read file DMA read address 1391 #define CFG_0A_RST_CMDQ_FILEIN_TSIF3 0x0100 //reset the file in TSIF3 command queue 1392 #define CFG_0A_WB_RST_FILEIN_TSIF3 0x0200 //reset DMA to TSIF FSM in TSP clock Domain 1393 #define CFG_0A_RST_WB_DMA_FILEIN_TSIF3 0x0400 //reset TSIF3 DMA in TSP clock Domain 1394 #define CFG_0A_FILE2MI_PRI_TSIF3 0x0800 //Set 1: Higher MIU ABT read priority 1395 #define CFG_0A_RST_READ_DMA_3 0x1000 //reset TSIF3 DMA in MIU clock Domain 1396 #define CFG_0A_LPCR2_LOAD_TSIF3 0x2000 //Load lpcr2 from TSIF3 90k counter 1397 #define CFG_0A_LPCR2_LOAD_BUF3 0x4000 //Load lpcr2 from pdflt3_buffer 90k counter 1398 REG16 CFG_0B; 1399 #define CFG_0B_TSP_FILE_SEGMENT3 0x0001 //set 0 to enable file in alignment mdoe 1400 #define CFG_0B_TIMER_EN3 0x0002 //1: enable byte delay timer for TSIF3 filein path 0: packet delay timer 1401 #define CFG_0B_PKT192_EN3 0x0004 //Set 1 to enable TS packets with 192 bytes on file-in mode. (Blocking TS packets by timestamp) 1402 #define CFG_0B_PKT192_BLK_DISABLE3 0x0008 //Set 1 to disable file-in timestamp block scheme 1403 #define CFG_0B_LPCR2_WLD3 0x0010 //Set PCR to TSIF3 90k counter 1404 #define CFG_0B_TS_DATA_PORT_SEL3 0x0020 //TSIF3 data port output select. 0: select live TS to be TSIF output 1: select data port to be TSIF output 1405 #define CFG_0B_P_SEL3 0x0040 //select parallel TS interface for TSIF3 1406 #define CFG_0B_EXT_SYNC_SEL3 0x0080 //select exteranl sync for ts_if3 1407 #define CFG_0B_TS_IF3_EN 0x0100 //set 1 tsif3 live in enable 1408 #define CFG_0B_TS_DATA3_SWAP 0x0200 //tsif3 live in bit order swap 1409 REG16 CFG_0C; 1410 #define CFG_0C_PKT_CHK_SIZE_FIN3 0x00ff //(Packet Size �V 1) for sync detection in TSIF3 1411 #define CFG_0C_PKT_DMX_SIZE3 0xff00 //(Packet Size �V 1) for sync detection in pkt_demux3 1412 #define CFG_0C_PKT_DMX_SIZE3_SHIFT 8 1413 REG16 CFG_0D; 1414 #define CFG_0D_TSP_FILE_TIMER3 0xffff //Bit [15:0] of timer threshold for TS file playback data fetch from MIU. 1415 REG16 CFG_0E; 1416 #define CFG_0E_PKT_DEMUX_SIZE_0 0x00ff //(Packet Size - 1) for sync detection in pkt_demux0 1417 #define CFG_0E_PKT_SIZE3 0xff00 //(Packet Size �V 1) for sync detection in pkt_flt3 1418 #define CFG_0E_PKT_SIZE3_SHIFT 8 1419 REG16 CFG_0F; 1420 #define CFG_0F_PKT_CHK_SIZE3 0x00ff //(Packet Size �V 1) for sync detection in TSIF3. 1421 #define CFG_0F_SYNC_BYTE3 0xff00 //Sync byte for TSIF3 1422 #define CFG_0F_SYNC_BYTE3_SHIFT 8 1423 REG16 CFG_10; 1424 #define CFG_10_RESET_PDFLT0 0x0001 //reset Pdflt0 1425 #define CFG_10_RESET_PDFLT1 0x0002 //reset Pdflt1 1426 #define CFG_10_RESET_PDFLT2 0x0004 //reset Pdflt2 1427 #define CFG_10_RESET_PDFLT3 0x0008 //reset Pdflt3 1428 REG16 CFG_11; 1429 #define CFG_11_RECEIVE_BUF0_SRC 0x0003 //Receive BUF0 input Stream source selection 00: pkt_merge0 01: pkt_merge1 10: Dscrmb 1430 #define CFG_11_RECEIVE_BUF0_SRC_SHIFT 0 1431 #define CFG_11_RECEIVE_BUF1_SRC 0x000c //Receive BUF1 input Stream source selection 00: pkt_merge0 01: pkt_merge1 10: Dscrmb 1432 #define CFG_11_RECEIVE_BUF1_SRC_SHIFT 2 1433 #define CFG_11_RECEIVE_BUF2_SRC 0x0030 //Receive BUF2 input Stream source selection 00: pkt_merge0 01: pkt_merge1 10: Dscrmb 1434 #define CFG_11_RECEIVE_BUF2_SRC_SHIFT 4 1435 #define CFG_11_RECEIVE_BUF3_SRC 0x00c0 //Receive BUF3 input Stream source selection 00: pkt_merge0 01: pkt_merge1 10: Dscrmb 1436 #define CFG_11_RECEIVE_BUF3_SRC_SHIFT 6 1437 REG16 CFG_12; 1438 #define CFG_12_TIMESTAMP_SEL_PVR1 0x0001 //PVR1 timestamp sel 0:local timestamp 1:stream timestamp 1439 #define CFG_12_TIMESTAMP_SEL_PVR2 0x0002 //PVR2 timestamp sel 0:local timestamp 1:stream timestamp 1440 #define CFG_12_TIMESTAMP_SEL_PVR3 0x0004 //PVR3 timestamp sel 0:local timestamp 1:stream timestamp 1441 #define CFG_12_TIMESTAMP_SEL_PVR4 0x0008 //PVR4 timestamp sel 0:local timestamp 1:stream timestamp 1442 1443 #define CFG_12_REG_REST_RBF0 0x0010 //reset Receive buffer0 1444 #define CFG_12_REG_REST_RBF1 0x0020 //reset Receive buffer1 1445 #define CFG_12_REG_REST_RBF2 0x0040 //reset Receive buffer2 1446 #define CFG_12_REG_REST_RBF3 0x0080 //reset Receive buffer2 1447 1448 #define CFG_12_REG_REST_PDBF0 0x0400 //reset Pdflt_buf0 1449 #define CFG_12_REG_REST_PDBF1 0x0800 //reset Pdflt_buf1 1450 #define CFG_12_REG_REST_PDBF2 0x1000 //reset Pdflt_buf2 1451 #define CFG_12_REG_REST_PDBF3 0x2000 //reset Pdflt_buf3 1452 REG16 CFG_13; 1453 #define CFG_13_LPCR_WLD0 0x0001 //Set PCR to pdflt_buf0 90k counter 1454 #define CFG_13_LPCR_EN0 0x0002 //Enable Pdflt_buf0 90k counter 1455 #define CFG_13_LPCR_WLD1 0x0004 //Set PCR to pdflt_buf1 90k counter 1456 #define CFG_13_LPCR_EN1 0x0008 //Enable Pdflt_buf1 90k counter 1457 #define CFG_13_LPCR_WLD2 0x0010 //Set PCR to pdflt_bu 1458 #define CFG_13_LPCR_EN2 0x0020 //Enable Pdflt_buf1 90k counter 1459 #define CFG_13_LPCR_WLD3 0x0040 //Set PCR to pdflt_bu 1460 #define CFG_13_LPCR_EN3 0x0080 //Enable Pdflt_buf1 90k counter 1461 #define CFG_13_REG_RESET_ABT0 0x4000 //reset pkt_merge0 1462 #define CFG_13_REG_RESET_ABT1 0x8000 //reset pkt_merge1 1463 REG16 CFG_14; 1464 #define CFG_14_ABT_PORT0_SRC 0x0007 //pkt_merge0 input Stream source selection 0: tsif0 stream 1: tsif1 stream 2: tsif2 stream 3: tsif3 stream 4: tsif4 stream 5: tsif5 stream 1465 #define CFG_14_ABT_PORT0_SRC_SHIFT 0 1466 #define CFG_14_ABT_PORT1_SRC 0x0038 //pkt_merge0 input Stream source selection 1: tsif0 stream 1: tsif1 stream 2: tsif2 stream 3: tsif3 stream 4: tsif4 stream 5: tsif5 stream 1467 #define CFG_14_ABT_PORT1_SRC_SHIFT 3 1468 #define CFG_14_ABT_PORT2_SRC 0x01c0 //pkt_merge0 input Stream source selection 2: tsif0 stream 1: tsif1 stream 2: tsif2 stream 3: tsif3 stream 4: tsif4 stream 5: tsif5 stream 1469 #define CFG_14_ABT_PORT2_SRC_SHIFT 6 1470 #define CFG_14_ABT_PORT3_SRC 0x1E00 //pkt_merge0 input Stream source selection 2: tsif0 stream 1: tsif1 stream 2: tsif2 stream 3: tsif3 stream 4: tsif4 stream 5: tsif5 stream 1471 #define CFG_14_ABT_PORT3_SRC_SHIFT 9 1472 REG16 CFG_15; 1473 #define CFG_15_RBUF_FULL_LEVEL 0x0038 1474 #define CFG_15_PVR3_SRC 0x0e00 //PVR3 input path sel 000: pkt_demux0 001: pkt_demux1 010: pkt_demux2 011: pkt_demux3 100: pkt_demux4 101: pkt_demux5 1475 #define CFG_15_PVR3_SRC_SHIFT 9 1476 #define CFG_15_PVR4_SRC 0x7000 //PVR4input path sel 000: pkt_demux0 001: pkt_demux1 010: pkt_demux2 011: pkt_demux3 100: pkt_demux4 101: pkt_demux5 1477 #define CFG_15_PVR4_SRC_SHIFT 12 1478 1479 REG16 CFG_16; 1480 #define CFG_16_PVR3_REG_PINGPONG_EN 0x0001 //set 1 to enable the pingpong buffer of PVR3 1481 #define CFG_16_PVR3_STR2MI_EN 0x0002 //set 1 to enable PVR3 1482 #define CFG_16_PVR3_STR2MI_RST_WADR 0x0004 //set 1 to reset the PVR3 write pointer to the head address 1483 #define CFG_16_PVR3_STR2MI_PAUSE 0x0008 //set 1 to pause PVR3 1484 #define CFG_16_PVR3_PKT192_EN 0x0010 //set 1 to enable 192 mode of PVR3 1485 #define CFG_16_PVR3_BURST_LEN_MASK 0x0060 //the PVR3 dma burst length 00 : burst 8 01 : burst 4 10/11 : burst 1 1486 #define CFG_16_PVR3_BURST_LEN_SHIFT 5 1487 #define CFG_16_PVR3_LPCR1_WLD 0x0080 //set 1 to write the value of lpcr1 from the register to the lpcr1_buf for PVR3 1488 #define CFG_16_PVR3_PVR_ALIGN_EN 0x0100 //set 1 to enable the function of alignment of PVR3 1489 #define CFG_16_PVR3_STR2MI_DSWAP 0x0200 //set 1 to swap the bit order of stream2miu data bus of PVR3 1490 #define CFG_16_PVR3_STR2MI_BT_ORDER 0x0400 //Byte order of 16-byte recoding buffer to MIU of PVR3 0: Little endian. 1: Big endian 1491 #define CFG_16_REC_DATA3_INV_EN 0x0800 //Set 1 to enable data payload invert for PVR record 1492 #define CFG_16_PVR3_BLOCK_DIS 0x1000 //set 1 to disable the PVR3 fifo blocking mechanism 1493 #define CFG_16_PID_BYPASS3_REC 0x2000 //0: record PES 1: record 188/192 1494 #define CFG_16_REC_ALL3 0x4000 //set 1 to record all 1495 #define CFG_16_PVR3_LPCR1_RLD 0x8000 //set 1 to read the value of lpcr1 from the register to the lpcr1_buf for PVR3 1496 REG32 CFG_17_18; 1497 #define CFG_17_18_PVR3_STR2MI_HEAD 0xffffffff //[31:27] : reserved [26:0] : MIU start address1 of TS recoding buffer for PVR3 1498 REG32 CFG_19_1A; 1499 #define CFG_19_1A_PVR3_STR2MI_MID 0xffffffff //[31:27] : reserved [26:0] : MIU middle address1 of TS recoding buffer for PVR3. 1500 REG32 CFG_1B_1C; 1501 #define CFG_1B_1C_PVR3_STR2MI_TAIL 0xffffffff //[31:27] : reserved [26:0] : MIU tail address1 of TS recoding buffer for PVR3. 1502 REG32 CFG_1D_1E; 1503 #define CFG_1D_1E_PVR3_STR2MI_HEAD2 0xffffffff //[31:27] : reserved [26:0] : MIU start address2 of TS recoding buffer for PVR3 1504 REG32 CFG_1F_20; 1505 #define CFG_1F_20_PVR3_STR2MI_MID2 0xffffffff //[31:27] : reserved [26:0] : MIU middle address2 of TS recoding buffer for PVR3. 1506 REG32 CFG_21_22; 1507 #define CFG_21_22_PVR3_STR2MI_TAIL2 0xffffffff //[31:27] : reserved [26:0] : MIU tail address2 of TS recoding buffer for PVR3. 1508 1509 REG16 CFG_23; 1510 #define CFG_23_PVR4_REG_PINGPONG_EN 0x0001 //set 1 to enable the pingpong buffer of PVR4 1511 #define CFG_23_PVR4_STR2MI_EN 0x0002 //set 1 to enable PVR4 1512 #define CFG_23_PVR4_STR2MI_RST_WADR 0x0004 //set 1 to reset the PVR4 write pointer to the head address 1513 #define CFG_23_PVR4_STR2MI_PAUSE 0x0008 //set 1 to pause PVR4 1514 #define CFG_23_PVR4_PKT192_EN 0x0010 //set 1 to enable 192 mode of PVR4 1515 #define CFG_23_PVR4_BURST_LEN_MASK 0x0060 //the PVR4 dma burst length 00 : burst 8 01 : burst 4 10/11 : burst 1 1516 #define CFG_23_PVR4_BURST_LEN_SHIFT 5 1517 #define CFG_23_PVR4_LPCR1_WLD 0x0080 //set 1 to write the value of lpcr1 from the register to the lpcr1_buf for PVR4 1518 #define CFG_23_PVR4_PVR_ALIGN_EN 0x0100 //set 1 to enable the function of alignment of PVR4 1519 #define CFG_23_PVR4_STR2MI_DSWAP 0x0200 //set 1 to swap the bit order of stream2miu data bus of PVR4 1520 #define CFG_23_PVR4_STR2MI_BT_ORDER 0x0400 //Byte order of 16-byte recoding buffer to MIU of PVR4 0: Little endian. 1: Big endian 1521 #define CFG_23_REC_DATA4_INV_EN 0x0800 //Set 1 to enable data payload invert for PVR record 1522 #define CFG_23_PVR4_BLOCK_DIS 0x1000 //set 1 to disable the PVR4 fifo blocking mechanism 1523 #define CFG_23_PID_BYPASS4_REC 0x2000 //0: record PES 1: record 188/192 1524 #define CFG_23_REC_ALL4 0x4000 //set 1 to record all 1525 #define CFG_23_PVR4_LPCR1_RLD 0x8000 //set 1 to read the value of lpcr1 from the register to the lpcr1_buf for PVR4 1526 1527 REG32 CFG_24_25; 1528 #define CFG_24_25_PVR4_STR2MI_HEAD 0xffffffff //[31:27] : reserved [26:0] : MIU start address1 of TS recoding buffer for PVR4 1529 REG32 CFG_26_27; 1530 #define CFG_26_27_PVR4_STR2MI_MID 0xffffffff //[31:27] : reserved [26:0] : MIU middle address1 of TS recoding buffer for PVR4 1531 REG32 CFG_28_29; 1532 #define CFG_28_29_PVR4_STR2MI_TAIL 0xffffffff //[31:27] : reserved [26:0] : MIU tail address1 of TS recoding buffer for PVR4 1533 REG32 CFG_2A_2B; 1534 #define CFG_2A_2B_PVR4_STR2MI_HEAD2 0xffffffff //[31:27] : reserved [26:0] : MIU start address2 of TS recoding buffer for PVR4 1535 REG32 CFG_2C_2D; 1536 #define CFG_2C_2D_PVR4_STR2MI_MID2 0xffffffff //[31:27] : reserved [26:0] : MIU middle address2 of TS recoding buffer for PVR4 1537 REG32 CFG_2E_2F; 1538 #define CFG_2E_2F_PVR4_STR2MI_TAIL2 0xffffffff //[31:27] : reserved [26:0] : MIU tail address2 of TS recoding buffer for PVR4 1539 1540 REG32 CFG_30_31; 1541 #define CFG_30_31_REG_TSP_FILEIN_RADDR_TSIF1 0xffffffff //Read start address [23:0] (byte unit) in tsif1 and command queue mode 1542 REG32 CFG_32_33; 1543 #define CFG_32_33_REG_TSP_FILEIN_RNUM_TSIF1 0xffffffff //Read number [23:0] (byte unit) in tsif1 and command queue mode 1544 REG16 CFG_34; 1545 #define CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_START 0x0001 //bit[0] Set 1 to start tsif1 in command 1546 #define CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_DONE 0x0002 //bit[1] 1 : FileIn done 1547 #define CFG_34_REG_TSP_FILEIN_INIT_TRUST_TSIF1 0x0004 //bit[2] filein_init_trust for tsif1 1548 #define CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_ABORT 0x0010 //bit[4] Set 1 to abort tsif1 in command queue mode 1549 REG32 CFG_35_36; 1550 #define CFG_35_36_TSP_FILEIN_RADDR_TSIF2 0xffffffff //[31:24] : reserved [23:0] : Read start address [15:0] [23:16](byte unit) in tsif2 and command queue mode 1551 REG32 CFG_37_38; 1552 #define CFG_37_38_TSP_FILEIN_RNUM_TSIF2 0xffffffff //[31:24] : reserved [23:0] : Read number [15:0] [23:16] (byte unit) in tsif2 and command queue mode 1553 REG16 CFG_39; 1554 #define CFG_39_FILEIN_CTRL_TSIF2_START 0x0001 //bit[0] Set 1 to start tsif2 in command 1555 #define CFG_39_FILEIN_CTRL_TSIF2_DONE 0x0002 //bit[1] 1: FileIn done 1556 #define CFG_39_FILEIN_INIT_TRUST_TSIF2 0x0004 //bit[2] filein_init_trust for tsif2 1557 #define CFG_39_FILEIN_CTRL_TSIF2_ABORT 0x0010 //bit[4] Set 1 to abort tsif2 in command queue mode 1558 REG32 CFG_3A_3B; 1559 #define CFG_3A_3B_TSP_FILEIN_RADDR_TSIF3 0xffffffff //[31:24] : reserved [23:0] : Read start address [15:0] [23:16](byte unit) in tsif2 and command queue mode 1560 REG32 CFG_3C_3D; 1561 #define CFG_3C_3D_TSP_FILEIN_RNUM_TSIF3 0xffffffff //[31:24] : reserved [23:0] : Read number [15:0] [23:16] (byte unit) in tsif2 and command queue mode 1562 REG16 CFG_3E; 1563 #define CFG_3E_FILEIN_CTRL_TSIF3_START 0x0001 //bit[0] Set 1 to start tsif2 in command 1564 #define CFG_3E_FILEIN_CTRL_TSIF3_DONE 0x0002 //bit[1] 1: FileIn done 1565 #define CFG_3E_FILEIN_INIT_TRUST_TSIF3 0x0004 //bit[2] filein_init_trust for tsif3 1566 #define CFG_3E_FILEIN_CTRL_TSIF3_ABORT 0x0010 //bit[4] Set 1 to abort tsif2 in command queue mode 1567 REG16 CFG_3F; 1568 #define CFG_3F_REG_TSIF1_CMD_QUEUE_WR_CNT 0x001f 1569 #define CFG_3F_REG_TSIF1_CMD_QUEUE_FIFO_FULL 0x0040 1570 #define CFG_3F_REG_TSIF1_CMD_QUEUE_FIFO_EMPTY 0x0080 1571 #define CFG_3F_REG_TSIF1_CMD_QUEUE_WR_LEVEL 0x0300 1572 #define CFG_3F_REG_TSIF1_CMD_QUEUE_LEVEL_SHIFT 8 1573 #define CFG_3F_REG_TSIF1_CMD_QUEUE_SIZE 16 1574 REG16 CFG_40; 1575 #define CFG_40_REG_TSIF2_CMD_QUEUE_WR_CNT 0x001f 1576 #define CFG_40_REG_TSIF2_CMD_QUEUE_FIFO_FULL 0x0040 1577 #define CFG_40_REG_TSIF2_CMD_QUEUE_FIFO_EMPTY 0x0080 1578 #define CFG_40_REG_TSIF2_CMD_QUEUE_WR_LEVEL 0x0300 1579 #define CFG_40_REG_TSIF2_CMD_QUEUE_LEVEL_SHIFT 8 1580 #define CFG_40_REG_TSIF2_CMD_QUEUE_SIZE 16 1581 REG16 CFG_41; 1582 #define CFG_41_REG_TSIF3_CMD_QUEUE_WR_CNT 0x001f 1583 #define CFG_41_REG_TSIF3_CMD_QUEUE_FIFO_FULL 0x0040 1584 #define CFG_41_REG_TSIF3_CMD_QUEUE_FIFO_EMPTY 0x0080 1585 #define CFG_41_REG_TSIF3_CMD_QUEUE_WR_LEVEL 0x0300 1586 #define CFG_41_REG_TSIF3_CMD_QUEUE_LEVEL_SHIFT 8 1587 #define CFG_41_REG_TSIF3_CMD_QUEUE_SIZE 16 1588 REG32 CFG_42_43; 1589 #define CFG_42_43_REG_TIMESTAMP_TSP_FILEIN_TSIF1 0xffffffff //tsif1 pkt timestamp 1590 REG32 CFG_44_45; 1591 #define CFG_44_45_REG_TIMESTAMP_TSP_FILEIN_TSIF2 0xffffffff //tsif2 pkt timestamp 1592 REG32 CFG_46_47; 1593 #define CFG_46_47_REG_TIMESTAMP_TSP_FILEIN_TSIF3 0xffffffff //tsif3 pkt timestamp 1594 REG16 CFG_48; 1595 #define CFG_48_REG_INT0 0xffff 1596 REG16 CFG_49; 1597 REG16 CFG_4A_4F[6]; 1598 REG32 CFG_50_51; 1599 #define CFG_50_51_LPCR2_TSIF1_RD 0xffffffff //tsif1 90k counter value 1600 REG32 CFG_52_53; 1601 #define CFG_52_53_LPCR2_TSIF2_RD 0xffffffff //tsif2 90k counter value 1602 REG32 CFG_54_55; 1603 #define CFG_54_55_LPCR2_TSIF3_RD 0xffffffff //tsif3 90k counter value 1604 REG32 CFG_56_57; 1605 #define CFG_56_57_LPCR2_BUF0_RD 0xffffffff // pdflt_buf0 90k counter value 1606 REG32 CFG_58_59; 1607 #define CFG_58_59_LPCR2_BUF1_RD 0xffffffff // pdflt_buf1 90k counter value 1608 REG32 CFG_5A_5B; 1609 #define CFG_5A_5B_LPCR2_BUF2_RD 0xffffffff // pdflt_buf2 90k counter value 1610 REG32 CFG_5C_5D; 1611 #define CFG_5C_5D_LPCR2_BUF3_RD 0xffffffff // pdflt_buf3 90k counter value 1612 REG32 CFG_5E_5F; 1613 #define CFG_5E_5F_LPCR2_BUF4_RD 0xffffffff // pdflt_buf4 90k counter value 1614 REG32 CFG_60_61; 1615 #define CFG_60_61_LPCR2_BUF5_RD 0xffffffff // pdflt_buf5 90k counter value 1616 REG32 CFG_62_63; 1617 #define CFG_62_63_LPCR2_PVR3_RD 0xffffffff // PVR3 90k counter value 1618 REG32 CFG_64_65; // Reserved 1619 #define CFG_64_65_LPCR2_PVR4_RD 0xffffffff // PVR4 90k counter value 1620 REG32 CFG_66_67; 1621 #define CFG_66_67_PVR3_STR2MI_WADR_R 0xffffffff // PVR3 write point 1622 REG32 CFG_68_69; 1623 #define CFG_68_69_PVR4_STR2MI_WADR_R 0xffffffff // PVR4 write point 1624 REG32 CFG_6A_6B; 1625 #define CFG_6A_6B_TSP2MI_RADDR_S_TSIF1 0x0fffffff // tsif1 DMA read point 1626 REG32 CFG_6C_6D; 1627 #define CFG_6C_6D_TSP2MI_RADDR_S_TSIF2 0x0fffffff // tsif2 DMA read point 1628 REG32 CFG_6E_6F; 1629 #define CFG_6E_6F_TSP2MI_RADDR_S_TSIF3 0x0fffffff // tsif3 DMA read point 1630 REG16 CFG_70; 1631 #define CFG_70_MATCHECED_VPID_3D_MASK 0x1fff 1632 #define CFG_70_CHANGE_VPID_3D 0x4000 1633 REG16 CFG_71; 1634 #define CFG_71_MATCHECED_APID_B_MASK 0x1fff 1635 #define CFG_71_CHANGE_APID_B 0x4000 1636 REG16 CFG_72; 1637 #define CFG_72_MERGE_FIFO_STATUS 0x1fff 1638 REG16 CFG_73; 1639 #define CFG_73_PVR_STATUS_PVR3_FIFO_MASK 0x000f 1640 #define CFG_73_PVR_STATUS_PVR3_FIFO_SHIFT 0 1641 #define CFG_73_PVR_STATUS_PVR3_EVER_OVERFLOW_MASK 0x0001 1642 #define CFG_73_PVR_STATUS_PVR3_EVER_OVERFLOW_SHIFT 4 1643 #define CFG_73_PVR_STATUS_PVR3_STR2MI_INT_MASK 0x0006 1644 #define CFG_73_PVR_STATUS_PVR3_STR2MI_INT_SHIFT 5 1645 #define CFG_73_PVR_STATUS_PVR4_FIFO_MASK 0x000f 1646 #define CFG_73_PVR_STATUS_PVR4_FIFO_SHIFT 8 1647 #define CFG_73_PVR_STATUS_PVR4_EVER_OVERFLOW_MASK 0x0001 1648 #define CFG_73_PVR_STATUS_PVR4_EVER_OVERFLOW_SHIFT 12 1649 #define CFG_73_PVR_STATUS_PVR4_STR2MI_INT_MASK 0x0006 1650 #define CFG_73_PVR_STATUS_PVR4_STR2MI_INT_SHIFT 13 1651 REG16 CFG_74; 1652 #define CFG_74_MATCHECED_APID_C_MASK 0x1fff 1653 #define CFG_74_CHANGE_APID_C 0x4000 1654 REG16 CFG_75; 1655 #define CFG_75_FI_MOBF_INDEC_TSIF1_MASK 0x0000001F 1656 REG16 CFG_76; 1657 #define CFG_76_FI_MOBF_INDEC_TSIF2_MASK 0x0000001F 1658 REG16 CFG_77; 1659 #define CFG_77_FI_MOBF_INDEC_TSIF3_MASK 0x0000001F 1660 REG16 CFG_78_7B[4]; 1661 #define CFG_78_PVR3_INDEX 0x0000001F 1662 REG16 CFG_7C; 1663 #define CFG_7C_MATCHECED_APID_D_MASK 0x1fff 1664 #define CFG_7C_CHANGE_APID_D 0x4000 1665 REG16 CFG_7D; 1666 #define CFG_7D_MATCHECED_VPID_3_MASK 0x1fff 1667 #define CFG_7D_CHANGE_VPID_3 0x4000 1668 REG16 CFG_7E; 1669 #define CFG_7E_MATCHECED_VPID_4_MASK 0x1fff 1670 #define CFG_7E_CHANGE_VPID_4 0x4000 1671 1672 } REG_Ctrl2; 1673 1674 //TSP 4 1675 typedef struct _REG_Ctrl3 1676 { 1677 REG16 CFG3_00_09[10]; // 0x00 ~ 0x09 1678 REG16 CFG3_0A; // 0x0A 1679 #define CFG3_0A_REG_PDFLT_BF0_CAVID 0x001F 1680 #define CFG3_0A_REG_PDFLT_BF1_CAVID 0x03E0 1681 #define CFG3_0A_REG_PDFLT_BF2_CAVID 0x7C00 1682 REG16 CFG3_0B; // 0x0B 1683 REG16 CFG3_0C; // 0x0C 1684 #define CFG3_0C_RBF0_PASS_MODE 0x0001 1685 #define CFG3_0C_RBF1_PASS_MODE 0x0002 1686 #define CFG3_0C_RBF2_PASS_MODE 0x0004 1687 #define CFG3_0C_RBF3_PASS_MODE 0x0008 1688 1689 #define CFG3_0C_PKTDMX_CC_DROP_MSAK 0x03C0 1690 #define CFG3_0C_PKTDMX_CC_DROP_SHIFT 0x0006 1691 #define CFG3_0C_PIDFLT0_DUP_CC_SKIP 0x0040 1692 #define CFG3_0C_PIDFLT1_DUP_CC_SKIP 0x0080 1693 #define CFG3_0C_PIDFLT2_DUP_CC_SKIP 0x0100 1694 #define CFG3_0C_PIDFLT3_DUP_CC_SKIP 0x0200 1695 1696 REG16 CFG3_0D; // 0x0D 1697 #define CFG3_0D_PIDFLT0_ADP_DUP_CC_SKIP 0x0001 1698 #define CFG3_0D_PIDFLT1_ADP_DUP_CC_SKIP 0x0002 1699 #define CFG3_0D_PIDFLT2_ADP_DUP_CC_SKIP 0x0004 1700 #define CFG3_0D_PIDFLT3_ADP_DUP_CC_SKIP 0x0008 1701 REG16 CFG3_0E; // 0x0E 1702 #define CFG3_0E_PDFBUF_FULL_SEL 0x0007 1703 #define CFG3_0E_PKT_MERGE_TIMESTAMP_SRC_SEL 0x01F8 //reg_pkt_merge_timestamp_src_sel=> 1704 #define CFG3_0E_PIDBUF0_TIMESTAMP_27M 0x0008 //pdflt buffer 0 timestamp sel 1: 27m 0: 90k 1705 #define CFG3_0E_PIDBUF1_TIMESTAMP_27M 0x0010 //pdflt buffer 1 timestamp sel 1: 27m 0: 90k 1706 #define CFG3_0E_PIDBUF2_TIMESTAMP_27M 0x0020 //pdflt buffer 2 timestamp sel 1: 27m 0: 90k 1707 #define CFG3_0E_PIDBUF3_TIMESTAMP_27M 0x0040 //pdflt buffer 3 timestamp sel 1: 27m 0: 90k 1708 #define CFG3_0E_STREAM2MIU1_C27M 0x0200 //reg_stream2miu1_c90k_sel=>Stream2miu1 timestamp sel 1: 27m 0: 90k 1709 #define CFG3_0E_STREAM2MIU2_C27M 0x0400 //reg_stream2miu2_c90k_sel=>Stream2miu2 timestamp sel 1: 27m 0: 90k 1710 #define CFG3_0E_STREAM2MIU3_C27M 0x0800 //reg_stream2miu3_c90k_sel=>Stream2miu3 timestamp sel 1: 27m 0: 90k 1711 #define CFG3_0E_STREAM2MIU4_C27M 0x1000 //reg_stream2miu4_c90k_sel=>Stream2miu4 timestamp sel 1: 27m 0: 90k 1712 REG16 CFG3_0F; // 0x0F 1713 #define CFG3_0F_TSIF0_C27M 0x0001 //reg_tsif0_c90k_sel=>Tsif0 timestamp sel 1: 27m 0: 90k 1714 #define CFG3_0F_TSIF1_C27M 0x0002 //reg_tsif1_c90k_sel=>Tsif1 timestamp sel 1: 27m 0: 90k 1715 #define CFG3_0F_TSIF2_C27M 0x0004 //reg_tsif2_c90k_sel=>Tsif2 timestamp sel 1: 27m 0: 90k 1716 #define CFG3_0F_TSIF3_C27M 0x0008 //reg_tsif3_c90k_sel=>Tsif3 timestamp sel 1: 27m 0: 90k 1717 REG16 CFG3_10; // 0x10 1718 #define CFG3_10_TSO0_SRC 0x0007 //reg_tso0_src 1719 #define CFG3_10_TSO0_SRC_SHIFT 0 1720 #define CFG3_10_TSO0_SRC_PKTDMX0 0x0001 1721 #define CFG3_10_TSO0_SRC_PKTDMX1 0x0002 1722 #define CFG3_10_TSO0_SRC_PKTDMX2 0x0004 1723 #define CFG3_10_TSO1_SRC 0x0038 //reg_tso1_src 1724 #define CFG3_10_TSO1_SRC_SHIFT 3 1725 #define CFG3_10_TSO1_SRC_PKTDMX0 0x0001 1726 #define CFG3_10_TSO1_SRC_PKTDMX1 0x0002 1727 #define CFG3_10_TSO1_SRC_PKTDMX2 0x0004 1728 #define CFG3_10_TSO0_BLOCK_DIS 0x1000 //reg_tso0_block_dis 1729 #define CFG3_10_TSO1_BLOCK_DIS 0x2000 //reg_tso1_block_dis 1730 #define CFG3_10_PS_MODE_SRC_MASK 0x01C0 1731 #define CFG3_10_PS_MODE_SRC_SHIFT 6 1732 1733 REG16 CFG3_11; // 0x11 1734 REG32 CFG3_12_13; // reg_dmaw_lbnd4 1735 REG32 CFG3_14_15; // reg_dmaw_ubnd4 1736 REG16 CFG3_16; // 0x16 1737 #define CFG3_16_FIXED_DMA_RSTART_OTP_ONEWAY_LOAD_FW 0x8000 1738 REG16 CFG3_17; // 0x17 1739 #define CFG3_17_INIT_TIMESTAMP_TSIF_0 0x0040 1740 #define CFG3_17_INIT_TIMESTAMP_TSIF_1 0x0080 1741 #define CFG3_17_INIT_TIMESTAMP_TSIF_2 0x0100 1742 #define CFG3_17_INIT_TIMESTAMP_TSIF_3 0x0200 1743 REG16 CFG3_18_1A[3]; // 0x18 ~ 0x1A 1744 REG16 CFG3_1B; // 0x1B 1745 #define CFG3_1B_VQ_CLR 0x0001 1746 #define CFG3_1B_MINUS_BASE_TIMESTAMPE_PVR1 0x0100 1747 #define CFG3_1B_MINUS_BASE_TIMESTAMPE_PVR2 0x0200 1748 #define CFG3_1B_MINUS_BASE_TIMESTAMPE_PVR3 0x0400 1749 #define CFG3_1B_MINUS_BASE_TIMESTAMPE_PVR4 0x0800 1750 REG16 CFG3_1C_1D[2]; // 0x1C ~ 0x1D 1751 1752 REG16 CFG3_1E; // 0X1E 1753 #define CFG3_1E_TSIF0_SPD_RESET 0x0001 //Tsif0 SPD rest 1754 #define CFG3_1E_TSIF1_SPD_RESET 0x0002 //Tsif1 SPD rest 1755 #define CFG3_1E_TSIF2_SPD_RESET 0x0004 //Tsif2 SPD rest 1756 #define CFG3_1E_TSIF3_SPD_RESET 0x0008 //Tsif3 SPD rest 1757 REG16 CFG3_1F; // 0x1F 1758 REG16 CFG3_20; // 0x20 1759 #define CFG3_20_PIDFLT0_CLR_REPLACE_EN_MASK 0x000F //reg_pdflt0_clear_replace_en=>clear pdflt 0 cc replace function flag 1760 #define CFG3_20_PIDFLT1_CLR_REPLACE_EN_MASK 0x00F0 //reg_pdflt1_clear_replace_en=>clear pdflt 0 cc replace function flag 1761 #define CFG3_20_PIDFLT2_CLR_REPLACE_EN_MASK 0x0F00 //reg_pdflt2_clear_replace_en=>clear pdflt 0 cc replace function flag 1762 #define CFG3_20_PIDFLT3_CLR_REPLACE_EN_MASK 0xF000 //reg_pdflt3_clear_replace_en=>clear pdflt 0 cc replace function flag 1763 REG16 CFG3_21; // 0x21 1764 #define CFG3_21_TSIF0_FILE_PAUSE 0x0100 // Set 1 to inform TSIF(file-in engine) back-end pipe is full 1765 #define CFG3_21_TSIF1_FILE_PAUSE 0x0200 // and don't transmit data 1766 #define CFG3_21_TSIF2_FILE_PAUSE 0x0400 1767 #define CFG3_21_TSIF3_FILE_PAUSE 0x0800 1768 REG16 CFG3_22; 1769 #define CFG3_22_PVR1_PKT_MEET_SIZE_L_MASK 0xFFFF //PVR1 callback PKT Meet Size 1770 REG16 CFG3_23; 1771 #define CFG3_23_PVR1_PKT_MEET_SIZE_H_MASK 0x00FF 1772 #define CFG3_23_PVR1_STR2MI_CNT_CLR 0x0100 1773 #define CFG3_23_PVR1_STR2MI_CNT_INTMODE 0x0200 1774 #define CFG3_23_PVR1_STR2MI_SYNC_INTMODE 0x0400 1775 REG16 CFG3_24; 1776 #define CFG3_24_PVR2_PKT_MEET_SIZE_L_MASK 0xFFFF //PVR2 callback PKT Meet Size 1777 REG16 CFG3_25; 1778 #define CFG3_25_PVR2_PKT_MEET_SIZE_H_MASK 0x00FF 1779 #define CFG3_25_PVR2_STR2MI_CNT_CLR 0x0100 1780 #define CFG3_25_PVR2_STR2MI_CNT_INTMODE 0x0200 1781 #define CFG3_25_PVR2_STR2MI_SYNC_INTMODE 0x0400 1782 REG16 CFG3_26; 1783 #define CFG3_26_PVR3_PKT_MEET_SIZE_L_MASK 0xFFFF //PVR3 callback PKT Meet Size 1784 REG16 CFG3_27; 1785 #define CFG3_27_PVR3_PKT_MEET_SIZE_H_MASK 0x00FF 1786 #define CFG3_27_PVR3_STR2MI_CNT_CLR 0x0100 1787 #define CFG3_27_PVR3_STR2MI_CNT_INTMODE 0x0200 1788 #define CFG3_27_PVR3_STR2MI_SYNC_INTMODE 0x0400 1789 REG16 CFG3_28_29[2]; // 0x28 ~ 0x29 1790 REG16 CFG3_2A; 1791 #define CFG3_2A_PKTDMX0_TRACE_MARK_V_EN 0x0001 1792 #define CFG3_2A_PKTDMX0_TRACE_MARK_V3D_EN 0x0002 1793 #define CFG3_2A_PKTDMX0_TRACE_MARK_A_EN 0x0004 1794 #define CFG3_2A_PKTDMX0_TRACE_MARK_AB_EN 0x0008 1795 #define CFG3_2A_PKTDMX0_TRACE_MARK_AC_EN 0x0010 1796 #define CFG3_2A_PKTDMX1_TRACE_MARK_V_EN 0x0020 1797 #define CFG3_2A_PKTDMX1_TRACE_MARK_V3D_EN 0x0040 1798 #define CFG3_2A_PKTDMX1_TRACE_MARK_A_EN 0x0080 1799 #define CFG3_2A_PKTDMX1_TRACE_MARK_AB_EN 0x0100 1800 #define CFG3_2A_PKTDMX1_TRACE_MARK_AC_EN 0x0200 1801 #define CFG3_2A_PKTDMX2_TRACE_MARK_V_EN 0x0400 1802 #define CFG3_2A_PKTDMX2_TRACE_MARK_V3D_EN 0x0800 1803 #define CFG3_2A_PKTDMX2_TRACE_MARK_A_EN 0x1000 1804 #define CFG3_2A_PKTDMX2_TRACE_MARK_AB_EN 0x2000 1805 #define CFG3_2A_PKTDMX2_TRACE_MARK_AC_EN 0x4000 1806 REG16 CFG3_2B; 1807 #define CFG3_2B_PKTDMX3_TRACE_MARK_V_EN 0x0001 1808 #define CFG3_2B_PKTDMX3_TRACE_MARK_V3D_EN 0x0002 1809 #define CFG3_2B_PKTDMX3_TRACE_MARK_A_EN 0x0004 1810 #define CFG3_2B_PKTDMX3_TRACE_MARK_AB_EN 0x0008 1811 #define CFG3_2B_PKTDMX3_TRACE_MARK_AC_EN 0x0010 1812 #define CFG3_2B_PKTDMX4_TRACE_MARK_V_EN 0x0020 1813 #define CFG3_2B_PKTDMX4_TRACE_MARK_V3D_EN 0x0040 1814 #define CFG3_2B_PKTDMX4_TRACE_MARK_A_EN 0x0080 1815 #define CFG3_2B_PKTDMX4_TRACE_MARK_AB_EN 0x0100 1816 #define CFG3_2B_PKTDMX4_TRACE_MARK_AC_EN 0x0200 1817 REG16 CFG3_2C; 1818 #define CFG3_2C_PDFLT0_NDS_TEST_MODE 0x0001 1819 #define CFG3_2C_PDFLT1_NDS_TEST_MODE 0x0002 1820 #define CFG3_2C_PDFLT2_NDS_TEST_MODE 0x0004 1821 #define CFG3_2C_PDFLT3_NDS_TEST_MODE 0x0008 1822 #define CFG3_2C_AVFIFO_READ_SEL_MASK 0x01C0 1823 #define CFG3_2C_AVFIFO_READ_SEL_SHIFT 6 1824 #define CFG3_2C_AVFIFO_READ_SEL_V 0 1825 #define CFG3_2C_AVFIFO_READ_SEL_A 1 1826 #define CFG3_2C_AVFIFO_READ_SEL_AB 2 1827 #define CFG3_2C_AVFIFO_READ_SEL_V3D 3 1828 #define CFG3_2C_AVFIFO_READ_SEL_AC 4 1829 #define CFG3_2C_AVFIFO_READ_SEL_AD 5 1830 #define CFG3_2C_AVFIFO_READ_SEL_V3 6 1831 #define CFG3_2C_AVFIFO_READ_SEL_V4 7 1832 #define CFG3_2C_DEBUG_WR_SRC_SEL_MASK 0x0E00 1833 REG16 CFG3_2D; 1834 #define CFG3_2D_FIXED_RM_PINPONG_SYCN_IN_ECO 0x0001 // fixed_rm_pinpong_sycn_in_eco 1835 #define CFG3_2D_VPID_3D_BYPASS 0x0002 // reg_vpid_3d_bypass 1836 #define CFG3_2D_APID_B_BYPASS 0x0004 // reg_apid_b_bypass 1837 #define CFG3_2D_APID_C_BYPASS 0x0008 // reg_apid_b_bypass 1838 #define CFG3_2D_APID_D_BYPASS 0x0010 // reg_apid_b_bypass 1839 #define CFG3_2D_PKTDMX0_TRACE_MARK_AD_EN 0x0020 // reg_pkt_demux0_trace_mark_ad_en=>set 1 enable trace mark function in pktdemux0 audio d path 1840 #define CFG3_2D_PKTDMX1_TRACE_MARK_AD_EN 0x0040 // reg_pkt_demux1_trace_mark_ad_en=>set 1 enable trace mark function in pktdemux1 audio d path 1841 #define CFG3_2D_PKTDMX2_TRACE_MARK_AD_EN 0x0080 // reg_pkt_demux2_trace_mark_ad_en=>set 1 enable trace mark function in pktdemux2 audio d path 1842 #define CFG3_2D_PKTDMX3_TRACE_MARK_AD_EN 0x0100 // reg_pkt_demux3_trace_mark_ad_en=>set 1 enable trace mark function in pktdemux3 audio d path 1843 #define CFG3_2D_FILTER_NULL_PKT 0x0800 1844 #define CFG3_2D_CHECK_CA_FULL 0x8000 1845 REG16 CFG3_2E; 1846 #define CFG3_2E_VPID_3_BYPASS 0x0001 // reg_vpid_3_bypass 1847 #define CFG3_2E_PKTDMX0_TRACE_MARK_V3_EN 0x0002 // reg_pkt_demux0_trace_mark_v3_en=>set 1 enable trace mark function in pktdemux0 video 3 path 1848 #define CFG3_2E_PKTDMX1_TRACE_MARK_V3_EN 0x0004 // reg_pkt_demux1_trace_mark_v3_en=>set 1 enable trace mark function in pktdemux1 video 3 path 1849 #define CFG3_2E_PKTDMX2_TRACE_MARK_V3_EN 0x0008 // reg_pkt_demux2_trace_mark_v3_en=>set 1 enable trace mark function in pktdemux2 video 3 path 1850 #define CFG3_2E_PKTDMX3_TRACE_MARK_V3_EN 0x0010 // reg_pkt_demux3_trace_mark_v3_en=>set 1 enable trace mark function in pktdemux3 video 3 path 1851 REG16 CFG3_2F; 1852 #define CFG3_2F_VPID_4_BYPASS 0x0001 // reg_vpid_4_bypass 1853 #define CFG3_2F_PKTDMX0_TRACE_MARK_V4_EN 0x0002 // reg_pkt_demux0_trace_mark_v3_en=>set 1 enable trace mark function in pktdemux0 video 4 path 1854 #define CFG3_2F_PKTDMX1_TRACE_MARK_V4_EN 0x0004 // reg_pkt_demux1_trace_mark_v3_en=>set 1 enable trace mark function in pktdemux1 video 4 path 1855 #define CFG3_2F_PKTDMX2_TRACE_MARK_V4_EN 0x0008 // reg_pkt_demux2_trace_mark_v3_en=>set 1 enable trace mark function in pktdemux2 video 4 path 1856 #define CFG3_2F_PKTDMX3_TRACE_MARK_V4_EN 0x0010 // reg_pkt_demux3_trace_mark_v3_en=>set 1 enable trace mark function in pktdemux3 video 4 path 1857 REG16 CFG3_30; // 0x30 reserved 1858 REG16 CFG3_31; // 0x31 1859 #define CFG3_31_PVR1_MEET_SIZE_CNT_R_MASK 0x00FF 1860 #define CFG3_31_PVR2_MEET_SIZE_CNT_R_MASK 0xFF00 1861 REG16 CFG3_32; // 0x32 1862 #define CFG3_32_PVR3_MEET_SIZE_CNT_R_MASK 0x00FF 1863 #define CFG3_32_PVR4_MEET_SIZE_CNT_R_MASK 0xFF00 1864 REG16 CFG3_33; 1865 #define TSP_AFIFOC_EMPTY 0x0002 1866 #define TSP_AFIFOC_EMPTY_SHFT 1 1867 #define TSP_AFIFOC_FULL 0x0004 1868 #define TSP_AFIFOC_FULL_SHFT 2 1869 #define TSP_AFIFOC_LEVEL 0x0018 1870 #define TSP_AFIFOC_LEVEL_SHFT 3 1871 #define TSP_AFIFOD_EMPTY 0x1000 1872 #define TSP_AFIFOD_EMPTY_SHFT 12 1873 #define TSP_AFIFOD_FULL 0x4000 1874 #define TSP_AFIFOD_FULL_SHFT 13 1875 #define TSP_AFIFOD_LEVEL 0xC000 1876 #define TSP_AFIFOD_LEVEL_SHFT 14 1877 REG16 CFG3_34; // 0x34 1878 #define CFG3_34_DUP_PKT_SKIP_V 0x0001 //reg_dup_pkt_skip_v 1879 #define CFG3_34_DUP_PKT_SKIP_V3D 0x0002 //reg_dup_pkt_skip_v3d 1880 #define CFG3_34_DUP_PKT_SKIP_A 0x0004 //reg_dup_pkt_skip_a 1881 #define CFG3_34_DUP_PKT_SKIP_AB 0x0008 //reg_dup_pkt_skip_ab 1882 #define CFG3_34_DUP_PKT_SKIP_AC 0x0010 //reg_dup_pkt_skip_ac 1883 #define CFG3_34_DUP_PKT_SKIP_AD 0x0020 //reg_dup_pkt_skip_ad 1884 #define CFG3_34_MASK_SRC_V_EN 0x0100 //mask_scr_vid_en 1885 #define CFG3_34_MASK_SRC_V3D_EN 0x0200 //mask_scr_v3d_en 1886 #define CFG3_34_MASK_SRC_A_EN 0x0400 //mask_scr_aud_en 1887 #define CFG3_34_MASK_SRC_AB_EN 0x0800 //mask_scr_aud_b_en 1888 #define CFG3_34_MASK_SRC_AC_EN 0x1000 //mask_scr_aud_c_en 1889 #define CFG3_34_MASK_SRC_AD_EN 0x2000 //mask_scr_aud_d_en 1890 #define CFG3_34_FIX_192_TIMER_0_EN 0x4000 //reg_fix_192_timer_0_en 1891 #define CFG3_34_TSP2MI_REQ_MCM_DISABLE 0x8000 //reg_tsp2mi_req_mcm_disable 1892 REG16 CFG3_35; // 0x35 1893 #define HW4_CFG35_BLK_AD_SCMBTIS_TSP 0x0001 1894 #define HW4_CFG35_PUSI_3BYTE_MODE 0x0002 1895 #define HW4_CFG35_PKT_MERGE_AUTO_RST 0x0004 1896 #define HW4_CFG35_AES_OUT_BT_ORDER 0x0008 1897 #define HW4_CFG35_AES_IN_BT_ORDER 0x0010 1898 #define HW4_CFG35_PREVENT_PID_TABLE_SRAM_COLLISION 0x0020 1899 #define HW4_CFG35_RW_CONDITION_0 0x0040 1900 #define HW4_CFG35_RW_CONDITION_1 0x0080 1901 #define HW4_CFG35_PUSI_UPDATE_SCMB_BIT 0x0100 1902 #define HW4_CFG35_BYPASS_TIMESTAMP_SEL1 0x0200 1903 #define HW4_CFG35_BYPASS_TIMESTAMP_SEL2 0x0400 1904 #define HW4_CFG35_BYPASS_TIMESTAMP_SEL3 0x0800 1905 #define HW4_CFG35_BYPASS_TIMESTAMP_SEL4 0x1000 1906 #define HW4_CFG35_CLR_SRAM_COLLISION 0x2000 1907 #define HW4_CFG35_PREVENT_SRAM_COLLISION 0x4000 1908 #define HW4_CFG35_BYPASS_FILEIN_TO_FIQ 0x8000 1909 REG16 CFG3_36; 1910 #define HW4_CFG36_RVU_PSI_EN0 0x0001 //rvu setting 1911 #define HW4_CFG36_RVU_TEI_EN0 0x0002 1912 #define HW4_CFG36_RVU_ERR_CLR0 0x0004 1913 #define HW4_CFG36_RVU_EN0 0x0008 1914 #define HW4_CFG36_RVU_TIMESTAMP_EN0 0x0010 1915 #define HW4_CFG36_RVU_PID_12_TIE_0_EN0 0x0020 1916 #define HW4_CFG36_PAYLOAD_128_MODE_EN0 0x0040 1917 #define HW4_CFG36_RVU_PSI_EN1 0x0100 1918 #define HW4_CFG36_RVU_TEI_EN1 0x0200 1919 #define HW4_CFG36_RVU_ERR_CLR1 0x0400 1920 #define HW4_CFG36_RVU_EN1 0x0800 1921 #define HW4_CFG36_RVU_TIMESTAMP_EN1 0x1000 1922 REG16 CFG3_37; 1923 #define HW4_CFG37_3WIRE_SERIAL_MODE_TS0 0x0001 1924 #define HW4_CFG37_3WIRE_SERIAL_MODE_TS1 0x0002 1925 #define HW4_CFG37_3WIRE_SERIAL_MODE_TS2 0x0004 1926 #define HW4_CFG37_3WIRE_SERIAL_MODE_TS3 0x0008 1927 #define HW4_CFG37_NON_188_CNT_MODE 0x0100 1928 #define HW4_CFG37_MASK_SCR_PVR1_EN 0x0200 1929 #define HW4_CFG37_MASK_SCR_PVR2_EN 0x0400 1930 #define HW4_CFG37_MASK_SCR_PVR3_EN 0x0800 1931 #define HW4_CFG37_MASK_SCR_PVR4_EN 0x1000 1932 #define HW4_CFG37_RST_CC_MODE 0x2000 1933 #define HW4_CFG37_DIS_CNTR_INC_BY_PL 0x4000 // 1=without payload 0=with payload ??? 1934 REG16 CFG3_38; 1935 #define HW4_CFG38_LOAD_SPS_KEY1 0x0001 1936 #define HW4_CFG38_LOAD_SPS_KEY2 0x0002 1937 #define HW4_CFG38_LOAD_SPS_KEY3 0x0004 1938 #define HW4_CFG38_LOAD_SPS_KEY4 0x0008 1939 #define HW4_CFG38_PKT192_SPS_EN1 0x0010 1940 #define HW4_CFG38_PKT192_SPS_EN2 0x0020 1941 #define HW4_CFG38_PKT192_SPS_EN3 0x0040 1942 #define HW4_CFG38_PKT192_SPS_EN4 0x0080 1943 #define HW4_CFG38_CA_PVR1_SEL_MASK 0x0300 1944 #define HW4_CFG38_CA_PVR1_SEL_SHIFT 8 1945 #define HW4_CFG38_CA_PVR2_SEL_MASK 0x0C00 1946 #define HW4_CFG38_CA_PVR2_SEL_SHIFT 10 1947 #define HW4_CFG38_CA_PVR3_SEL_MASK 0x3000 1948 #define HW4_CFG38_CA_PVR3_SEL_SHIFT 12 1949 #define HW4_CFG38_CA_PVR4_SEL_MASK 0xC000 1950 #define HW4_CFG38_CA_PVR4_SEL_SHIFT 14 1951 REG16 CFG3_39; 1952 #define HW4_CFG39_FLUSH_PVR_DATA 0x0001 1953 #define HW4_CFG39_FLUSH_PVR1_DATA 0x0002 1954 #define HW4_CFG39_FLUSH_PVR2_DATA 0x0004 1955 #define HW4_CFG39_FLUSH_PVR3_DATA 0x0008 1956 REG16 CFG3_3A; 1957 #define HW4_CFG3A_LOAD_SPD_KEY0 0x0001 1958 #define HW4_CFG3A_LOAD_SPD_KEY1 0x0002 1959 #define HW4_CFG3A_LOAD_SPD_KEY2 0x0004 1960 #define HW4_CFG3A_LOAD_SPD_KEY3 0x0008 1961 #define HW4_CFG3A_LOAD_SPD_KEY4 0x0010 1962 #define HW4_CFG3A_LOAD_SPD_KEY5 0x0020 1963 REG16 CFG3_3B_3F[5]; 1964 REG16 CFG3_40; 1965 #define HW4_CFG40_HW_SEMAPHORE0_MASK 0xFFFF 1966 REG16 CFG3_41; 1967 #define HW4_CFG41_HW_SEMAPHORE1_MASK 0xFFFF 1968 REG16 CFG3_42; 1969 #define HW4_CFG42_HW_SEMAPHORE2_MASK 0xFFFF 1970 REG16 CFG3_43; 1971 #define HW4_CFG43_SRC_AES_PVR_KEY_MASK 0x0007 1972 #define HW4_CFG43_SRC_AES_PVR1_KEY 0x0000 1973 #define HW4_CFG43_SRC_AES_PVR2_KEY 0x0001 1974 #define HW4_CFG43_SRC_AES_PVR3_KEY 0x0002 1975 #define HW4_CFG43_SRC_AES_PVR4_KEY 0x0003 1976 #define HW4_CFG43_SRC_AES_FI_KEY_MASK 0x0038 1977 #define HW4_CFG43_SRC_AES_FI_KEY_SHIFT 3 1978 #define HW4_CFG43_SRC_AES_FI0_KEY 0x0000 1979 #define HW4_CFG43_SRC_AES_FI1_KEY 0x0001 1980 #define HW4_CFG43_SRC_AES_FI2_KEY 0x0002 1981 #define HW4_CFG43_SRC_AES_FI3_KEY 0x0003 1982 REG32 CFG3_44_45; //pause time0 for PVR1+ FIQ application 1983 REG32 CFG3_46_47; //pause time1 for PVR2+ FIQ application 1984 REG32 CFG3_48_49; //pause time2 for PVR3+ FIQ application 1985 REG32 CFG3_4A_4B; //pause time3 for PVR4+ FIQ application 1986 REG16 CFG3_4C; 1987 #define CFG3_4C_TSP_VFIFO3_EMPTY 0x0001 1988 #define CFG3_4C_TSP_VFIFO3_EMPTY_SHFT 0 1989 #define CFG3_4C_TSP_VFIFO3_FULL 0x0002 1990 #define CFG3_4C_TSP_VFIFO3_FULL_SHFT 1 1991 #define CFG3_4C_TSP_VFIFO3_LEVEL 0x000C 1992 #define CFG3_4C_TSP_VFIFO3_LEVEL_SHFT 2 1993 #define CFG3_4C_TSP_VD3_FIFO_DISCON 0x0100 1994 #define CFG3_4C_TSP_VD3_FIFO_OVERFLOW 0x0200 1995 REG16 CFG3_4D; 1996 #define CFG3_4D_TSP_VFIFO4_EMPTY 0x0001 1997 #define CFG3_4D_TSP_VFIFO4_EMPTY_SHFT 0 1998 #define CFG3_4D_TSP_VFIFO4_FULL 0x0002 1999 #define CFG3_4D_TSP_VFIFO4_FULL_SHFT 1 2000 #define CFG3_4D_TSP_VFIFO4_LEVEL 0x000C 2001 #define CFG3_4D_TSP_VFIFO4_LEVEL_SHFT 2 2002 #define CFG3_4D_TSP_VD4_FIFO_DISCON 0x0100 2003 #define CFG3_4D_TSP_VD4_FIFO_OVERFLOW 0x0200 2004 REG16 CFG3_4E_4F[2]; 2005 REG32 CFG3_50_51; 2006 REG16 CFG3_52; 2007 #define CFG3_52_SPD_TSIF0_BYPASS 0x0001 2008 #define CFG3_52_SPD_TSIF1_BYPASS 0x0002 2009 #define CFG3_52_SPD_TSIF2_BYPASS 0x0004 2010 #define CFG3_52_SPD_TSIF3_BYPASS 0x0008 2011 REG16 CFG3_53; 2012 #define CFG3_53_WB_FSM_RESET 0x0001 2013 REG16 CFG3_54_57[4]; 2014 REG16 CFG3_58_5F[8]; 2015 REG16 CFG3_60_67[8]; //AES KEY PVR 2016 REG16 CFG3_68_6F[8]; //AES KEY FILEIN 2017 REG16 CFG3_70_71[2]; //BIST fail status 2018 REG16 CFG3_72; 2019 #define CFG3_72_PIDFLT_PCR0_SRC_ID_MASK 0x000F 2020 #define CFG3_72_PIDFLT_PCR0_SRC_ID_SHIFT 0 2021 #define CFG3_72_PIDFLT_PCR1_SRC_ID_MASK 0x0F00 2022 #define CFG3_72_PIDFLT_PCR1_SRC_ID_SHIFT 8 2023 REG16 CFG3_73; 2024 #define CFG3_73_PVR1_DMAW_PROTECT_EN 0x0001 2025 #define CFG3_73_PVR2_DMAW_PROTECT_EN 0x0002 2026 #define CFG3_73_PVR3_DMAW_PROTECT_EN 0x0004 2027 #define CFG3_73_PVR4_DMAW_PROTECT_EN 0x0008 2028 #define CFG3_73_FILEIN0_DMAR_PROTECT_EN 0x0010 2029 #define CFG3_73_FILEIN1_DMAR_PROTECT_EN 0x0020 2030 #define CFG3_73_FILEIN2_DMAR_PROTECT_EN 0x0040 2031 #define CFG3_73_FILEIN3_DMAR_PROTECT_EN 0x0080 2032 #define CFG3_73_MMFI0_DMAR_PROTECT_EN 0x0400 2033 #define CFG3_73_MMFI1_DMAR_PROTECT_EN 0x0800 2034 #define CFG3_73_FILEIN0_ILLEGAL_ADDR_0 0x1000 2035 #define CFG3_73_FILEIN1_ILLEGAL_ADDR_0 0x2000 2036 #define CFG3_73_FILEIN2_ILLEGAL_ADDR_0 0x4000 2037 #define CFG3_73_FILEIN3_ILLEGAL_ADDR_0 0x8000 2038 REG16 CFG3_74; 2039 #define CFG3_74_MMFI0_ILLEGAL_ADDR_0 0x0004 2040 #define CFG3_74_MMFI1_ILLEGAL_ADDR_0 0x0008 2041 #define CFG3_74_FILEIN0_ILLEGAL_MIU_NS_EN 0x0010 2042 #define CFG3_74_FILEIN1_ILLEGAL_MIU_NS_EN 0x0020 2043 #define CFG3_74_FILEIN2_ILLEGAL_MIU_NS_EN 0x0040 2044 #define CFG3_74_FILEIN3_ILLEGAL_MIU_NS_EN 0x0080 2045 #define CFG3_74_MMFI0_ILLEGAL_MIU_NS_EN 0x0400 2046 #define CFG3_74_MMFI1_ILLEGAL_MIU_NS_EN 0x0800 2047 #define CFG3_74_DIS_FILEIN0_ADDR_LEN_BY_TEE 0x1000 2048 #define CFG3_74_DIS_FILEIN1_ADDR_LEN_BY_TEE 0x2000 2049 #define CFG3_74_DIS_FILEIN2_ADDR_LEN_BY_TEE 0x4000 2050 #define CFG3_74_DIS_FILEIN3_ADDR_LEN_BY_TEE 0x8000 2051 REG16 CFG3_75; 2052 #define CFG3_75_DIS_MMFI0_ADDR_LEN_BY_TEE 0x0004 2053 #define CFG3_75_DIS_MMFI1_ADDR_LEN_BY_TEE 0x0008 2054 REG16 CFG3_76_7B[6]; 2055 REG16 CFG3_7C; 2056 #define CFG3_7C_PRIVILEGE_FLAG 0x0001 2057 2058 REG16 CFG3_7D; 2059 #define CFG3_7D_REG_CA_PVR1_SEL 0x0001 2060 #define CFG3_7D_REG_CA_PVR2_SEL 0x0002 2061 #define CFG3_7D_REG_CA_PVR3_SEL 0x0004 2062 #define CFG3_7D_REG_CA_PVR4_SEL 0x0008 2063 2064 } REG_Ctrl3; 2065 2066 //@TODO There is FIQ Bank in TSP6 bank 2067 //TSP 6 2068 typedef struct _REG_Ctrl4 2069 { 2070 REG16 CFG4_00_53[84]; 2071 REG16 CFG4_54; 2072 #define CFG4_54_RVU_PSI_EN2 0x0001 2073 #define CFG4_54_RVU_TEI_EN2 0x0002 2074 #define CFG4_54_RVU_ERR_CLR2 0x0004 2075 #define CFG4_54_RVU_EN2 0x0008 2076 #define CFG4_54_RVU_TIMESTAMP_EN2 0x0010 2077 #define CFG4_54_RVU_PID_12_TIE_0_EN2 0x0020 2078 #define CFG4_54_PAYLOAD_128_MODE_EN2 0x0040 2079 2080 #define CFG4_54_RVU_PSI_EN3 0x0100 2081 #define CFG4_54_RVU_TEI_EN3 0x0200 2082 #define CFG4_54_RVU_ERR_CLR3 0x0400 2083 #define CFG4_54_RVU_EN3 0x0800 2084 #define CFG4_54_RVU_TIMESTAMP_EN3 0x1000 2085 #define CFG4_54_RVU_PID_12_TIE_0_EN3 0x2000 2086 #define CFG4_54_PAYLOAD_128_MODE_EN3 0x4000 2087 REG16 CFG4_55; 2088 #define CFG4_55_RVU_PSI_EN4 0x0001 2089 #define CFG4_55_RVU_TEI_EN4 0x0002 2090 #define CFG4_55_RVU_ERR_CLR4 0x0004 2091 #define CFG4_55_RVU_EN4 0x0008 2092 #define CFG4_55_RVU_TIMESTAMP_EN4 0x0010 2093 #define CFG4_55_RVU_PID_12_TIE_0_EN4 0x0020 2094 #define CFG4_55_PAYLOAD_128_MODE_EN4 0x0040 2095 }REG_Ctrl4; 2096 2097 //TSP 7 2098 typedef struct _REG_Ctrl5 2099 { 2100 REG16 CFG5_00; 2101 REG16 CFG5_01; 2102 REG16 CFG5_02; 2103 REG16 CFG5_03; 2104 REG16 CFG5_04; 2105 REG16 Drop_Dis_PKT_Cnt_0; 2106 REG16 Drop_Dis_PKT_Cnt_1; 2107 REG16 Drop_Dis_PKT_Cnt_2; 2108 REG16 Drop_Dis_PKT_Cnt_3; 2109 REG16 CFG5_09; 2110 REG16 CFG5_0A; 2111 REG16 CFG5_0B; 2112 REG16 CFG5_0C; 2113 REG16 Locked_PKT_Cnt; //0x0D : reg_locked_pkt_cnt 2114 REG16 Av_PKT_Cnt; //0x0E : aud_pkt /vid_pkt 2115 REG16 CFG5_0F_16[8]; 2116 REG16 Av_PKT_Cnt1; //0x17 : aud_b_pkt /vid_3d_pkt 2117 REG16 CFG5_18; 2118 REG16 Err_PKT_Cnt; //0x19 : reg_err_pkt_cnt 2119 REG16 CFG5_1A_1C[3]; 2120 REG16 Input_PKT_Cnt; //0x1D : reg_input_pkt_cnt 2121 REG16 CFG5_1E_6F[82]; 2122 REG16 CFG5_70; 2123 #define CFG5_70_ERR_PKT_SRC_SEL_SHIFT 0 2124 #define CFG5_70_ERR_PKT_SRC_SEL_MASK 0x0007 2125 #define CFG5_70_INPUT_PKT_SRC_SEL_SHIT 3 2126 #define CFG5_70_INPUT_PKT_SRC_SEL_MASK 0x0038 2127 REG16 CFG5_71; 2128 #define CFG5_71_ERR_PKT_CNT_0_LOAD 0x0001 2129 #define CFG5_71_ERR_PKT_CNT_1_LOAD 0x0002 2130 #define CFG5_71_ERR_PKT_CNT_2_LOAD 0x0004 2131 #define CFG5_71_ERR_PKT_CNT_3_LOAD 0x0008 2132 #define CFG5_71_INPUT_PKT_CNT_0_LOAD 0x0100 2133 #define CFG5_71_INPUT_PKT_CNT_1_LOAD 0x0200 2134 #define CFG5_71_INPUT_PKT_CNT_2_LOAD 0x0400 2135 #define CFG5_71_INPUT_PKT_CNT_3_LOAD 0x0800 2136 REG16 CFG5_72; 2137 #define CFG5_72_ERR_PKT_CNT_0_CLR 0x0001 2138 #define CFG5_72_ERR_PKT_CNT_1_CLR 0x0002 2139 #define CFG5_72_ERR_PKT_CNT_2_CLR 0x0004 2140 #define CFG5_72_ERR_PKT_CNT_3_CLR 0x0008 2141 #define CFG5_72_INPUT_PKT_CNT_0_CLR 0x0100 2142 #define CFG5_72_INPUT_PKT_CNT_1_CLR 0x0200 2143 #define CFG5_72_INPUT_PKT_CNT_2_CLR 0x0400 2144 #define CFG5_72_INPUT_PKT_CNT_3_CLR 0x0800 2145 REG16 Av_PKT_Cnt2; //0x73 : vid_3_pkt /vid_4_pkt 2146 REG16 CFG5_74; 2147 #define CFG5_74_V3_PKT_CNT_LOAD 0x0001 2148 #define CFG5_74_V3_PKT_CNT_CLR 0x0002 2149 #define CFG5_74_DROP_PKT_CNT_V3_LOAD 0x0004 2150 #define CFG5_74_DROP_PKT_CNT_V3_CLR 0x0008 2151 #define CFG5_74_DIS_PKT_CNT_V3_LOAD 0x0010 2152 #define CFG5_74_DIS_PKT_CNT_V3_CLR 0x0020 2153 REG16 CFG5_75; 2154 #define CFG5_75_V4_PKT_CNT_LOAD 0x0001 2155 #define CFG5_75_V4_PKT_CNT_CLR 0x0002 2156 #define CFG5_75_DROP_PKT_CNT_V4_LOAD 0x0004 2157 #define CFG5_75_DROP_PKT_CNT_V4_CLR 0x0008 2158 #define CFG5_75_DIS_PKT_CNT_V4_LOAD 0x0010 2159 #define CFG5_75_DIS_PKT_CNT_V4_CLR 0x0020 2160 REG16 CFG5_76; 2161 REG16 CFG5_77; 2162 #define CFG5_77_PIDFLT_SRC_SEL2_SHIFT 0 //pkt dmx 2 2163 #define CFG5_77_PIDFLT_SRC_SEL2_MASK 0x0007 2164 #define CFG5_77_PIDFLT_SRC_SEL3_SHIFT 3 //pkt dmx 3 2165 #define CFG5_77_PIDFLT_SRC_SEL3_MASK 0x0038 2166 REG16 CFG5_78; 2167 #define CFG5_78_AUDC_SRC_MASK 0x0007 2168 #define CFG5_78_AUDC_SRC_SHIFT 0 2169 #define CFG5_78_AUDD_SRC_MASK 0x0038 2170 #define CFG5_78_AUDD_SRC_SHIFT 3 2171 #define CFG5_78_PIDFLT_SRC_SEL_MMFI0_SHIFT 6 // MMFI0 2172 #define CFG5_78_PIDFLT_SRC_SEL_MMFI0_MASK 0x01C0 2173 #define CFG5_78_PIDFLT_SRC_SEL_MMFI1_SHIFT 9 // MMFI1 2174 #define CFG5_78_PIDFLT_SRC_SEL_MMFI1_MASK 0x0E00 2175 #define CFG5_78_VID_4_SRC_MASK 0x7000 2176 #define CFG5_78_VID_4_SRC_SHIFT 12 2177 REG16 CFG5_79; 2178 REG16 CFG5_7A; 2179 #define CFG5_7A_LOCKED_PKT_CNT_0_LOAD 0x0001 2180 #define CFG5_7A_LOCKED_PKT_CNT_1_LOAD 0x0002 2181 #define CFG5_7A_LOCKED_PKT_CNT_2_LOAD 0x0004 2182 #define CFG5_7A_LOCKED_PKT_CNT_3_LOAD 0x0008 2183 #define CFG5_7A_A_PKT_CNT_LOAD 0x0100 2184 #define CFG5_7A_V_PKT_CNT_LOAD 0x0200 2185 #define CFG5_7A_AD_PKT_CNT_LOAD 0x0400 2186 #define CFG5_7A_V3D_PKT_CNT_LOAD 0x0800 2187 #define CFG5_7A_ADC_PKT_CNT_LOAD 0x1000 2188 #define CFG5_7A_ADD_PKT_CNT_LOAD 0x2000 2189 REG16 CFG5_7B; 2190 #define CFG5_7B_DROP_PKT_CNT_V_LOAD 0x0001 2191 #define CFG5_7B_DROP_PKT_CNT_V3D_LOAD 0x0002 2192 #define CFG5_7B_DROP_PKT_CNT_A_LOAD 0x0004 2193 #define CFG5_7B_DROP_PKT_CNT_AD_LOAD 0x0008 2194 #define CFG5_7B_DROP_PKT_CNT_ADC_LOAD 0x0010 2195 #define CFG5_7B_DROP_PKT_CNT_ADD_LOAD 0x0020 2196 #define CFG5_7B_DIS_PKT_CNT_V_LOAD 0x0100 2197 #define CFG5_7B_DIS_PKT_CNT_V3D_LOAD 0x0200 2198 #define CFG5_7B_DIS_PKT_CNT_A_LOAD 0x0400 2199 #define CFG5_7B_DIS_PKT_CNT_AD_LOAD 0x0800 2200 #define CFG5_7B_DIS_PKT_CNT_ADC_LOAD 0x1000 2201 #define CFG5_7B_DIS_PKT_CNT_ADD_LOAD 0x2000 2202 REG16 CFG5_7C; 2203 #define CFG5_7C_LOCKED_PKT_CNT_0_CLR 0x0001 2204 #define CFG5_7C_LOCKED_PKT_CNT_1_CLR 0x0002 2205 #define CFG5_7C_LOCKED_PKT_CNT_2_CLR 0x0004 2206 #define CFG5_7C_LOCKED_PKT_CNT_3_CLR 0x0008 2207 #define CFG5_7C_A_PKT_CNT_CLR 0x0100 2208 #define CFG5_7C_V_PKT_CNT_CLR 0x0200 2209 #define CFG5_7C_AD_PKT_CNT_CLR 0x0400 2210 #define CFG5_7C_V3D_PKT_CNT_CLR 0x0800 2211 #define CFG5_7C_ADC_PKT_CNT_CLR 0x1000 2212 #define CFG5_7C_ADD_PKT_CNT_CLR 0x2000 2213 REG16 CFG5_7D; 2214 #define CFG5_7D_DROP_PKT_CNT_V_CLR 0x0001 2215 #define CFG5_7D_DROP_PKT_CNT_V3D_CLR 0x0002 2216 #define CFG5_7D_DROP_PKT_CNT_A_CLR 0x0004 2217 #define CFG5_7D_DROP_PKT_CNT_AD_CLR 0x0008 2218 #define CFG5_7D_DROP_PKT_CNT_ADC_CLR 0x0010 2219 #define CFG5_7D_DROP_PKT_CNT_ADD_CLR 0x0020 2220 #define CFG5_7D_DIS_PKT_CNT_V_CLR 0x0100 2221 #define CFG5_7D_DIS_PKT_CNT_V3D_CLR 0x0200 2222 #define CFG5_7D_DIS_PKT_CNT_A_CLR 0x0400 2223 #define CFG5_7D_DIS_PKT_CNT_AD_CLR 0x0800 2224 #define CFG5_7D_DIS_PKT_CNT_ADC_CLR 0x1000 2225 #define CFG5_7D_DIS_PKT_CNT_ADD_CLR 0x2000 2226 REG16 CFG5_7E; 2227 #define CFG5_7E_AUDA_SRC_MASK 0x0007 2228 #define CFG5_7E_AUDA_SRC_SHIFT 0 2229 #define CFG5_7E_VID_SRC_MASK 0x0038 2230 #define CFG5_7E_VID_SRC_SHIFT 3 2231 #define CFG5_7E_AUDB_SRC_MASK 0x01C0 2232 #define CFG5_7E_AUDB_SRC_SHIFT 6 2233 #define CFG5_7E_VID_3D_SRC_MASK 0x0E00 2234 #define CFG5_7E_VID_3D_SRC_SHIFT 9 2235 #define CFG5_7E_VID_3_SRC_MASK 0x7000 2236 #define CFG5_7E_VID_3_SRC_SHIFT 12 2237 #define AV_PKT_SRC_PKTDMX0 0x0000 2238 #define AV_PKT_SRC_PKTDMX1 0x0001 2239 #define AV_PKT_SRC_PKTDMX2 0x0002 2240 #define AV_PKT_SRC_PKTDMX3 0x0003 2241 #define AV_PKT_SRC_PKTDMX4 0x0004 2242 #define AV_PKT_SRC_PKTDMX5 0x0005 2243 #define AV_PKT_SRC_MMFI0 0x0006 2244 #define AV_PKT_SRC_MMFI1 0x0007 2245 2246 REG16 CFG5_7F; 2247 #define CFG5_7F_DROP_PKT_MODE 0x0002 //choose the source of the reg_pkt_cnt 0: dis_cont_pkt 1: drop_pkt_cnt 2248 #define CFG5_7F_PIDFLT_SRC_SEL_SHIFT 2 //pkt dmx 0 2249 #define CFG5_7F_PIDFLT_SRC_SEL_MASK 0x001C 2250 #define CFG5_7F_TSIF_SRC_SEL_SHIFT 5 2251 #define CFG5_7F_TSIF_SRC_SEL_MASK 0x00E0 2252 #define TSIF_SRC_SEL_TSIF0 0x000 2253 #define TSIF_SRC_SEL_TSIF1 0x001 2254 #define TSIF_SRC_SEL_TSIF2 0x002 2255 #define TSIF_SRC_SEL_TSIF3 0x003 2256 2257 #define CFG5_7F_AV_PKT_SRC_SEL 0x0100 //choose the source of the Av_PKT_Cnt 0 : vid_pkt_cnt/vid_3d_pkt_cnt 1 : aud_pkt_cnt/aud_b_pkt_cnt 2258 #define CFG5_7F_CLR_SRC_SHIFT 9 2259 #define CFG5_7F_CLR_SRC_MASK 0x0E00 2260 #define CFG5_7F_CLR_SRC_PKTDMX0 0x0000 2261 #define CFG5_7F_CLR_SRC_PKTDMX1 0x0001 2262 #define CFG5_7F_CLR_SRC_PKTDMX2 0x0002 2263 #define CFG5_7F_CLR_SRC_PKTDMX3 0x0003 2264 #define CFG5_7F_CLR_SRC_PKTDMX4 0x0004 2265 #define CFG5_7F_CLR_SRC_PKTDMX5 0x0005 2266 #define CFG5_7F_CLR_SRC_MMFI0 0x0006 2267 #define CFG5_7F_CLR_SRC_MMFI1 0x0007 2268 2269 #define CFG5_7F_PIDFLT_SRC_SEL1_SHIFT 13 //pkt dmx 1 2270 #define CFG5_7F_PIDFLT_SRC_SEL1_MASK 0xE000 2271 #define DIS_DROP_CNT_V 0 2272 #define DIS_DROP_CNT_V3D 1 2273 #define DIS_DROP_CNT_A 2 2274 #define DIS_DROP_CNT_AD 3 2275 #define DIS_DROP_CNT_ADC 4 2276 #define DIS_DROP_CNT_ADD 5 2277 2278 } REG_Ctrl5; 2279 2280 //TSP 8 2281 typedef struct _REG_Ctrl6 2282 { 2283 REG16 SyncByte_tsif0[4]; //0x00~0x03 2284 #define TSP_SYNC_BYTE_MAASK0 0x00FF //byte 0 2285 #define TSP_SYNC_BYTE_MAASK1 0xFF00 //byte 1 2286 #define TSP_SYNC_BYTE_SHIFT0 0 2287 #define TSP_SYNC_BYTE_SHIFT1 8 2288 REG16 SourceId_tsif0[2]; //0x04~0x05 2289 #define TSP_SRCID_MASK0 0x000F //soruce 0 2290 #define TSP_SRCID_MASK1 0x00F0 //soruce 1 2291 #define TSP_SRCID_MASK2 0x0F00 //soruce 2 2292 #define TSP_SRCID_MASK3 0xF000 //soruce 3 2293 #define TSP_SRCID_SHIFT0 0 2294 #define TSP_SRCID_SHIFT1 4 2295 #define TSP_SRCID_SHIFT2 8 2296 #define TSP_SRCID_SHIFT3 12 2297 REG16 SyncByte_tsif1[4]; //0x06~0x09 2298 REG16 SourceId_tsif1[2]; //0x0a~0x0b 2299 REG16 SyncByte_tsif2[4]; //0x0c~0x0f 2300 REG16 SourceId_tsif2[2]; //0x10~0x11 2301 REG16 SyncByte_tsif3[4]; //0x12~0x15 2302 REG16 SourceId_tsif3[2]; //0x16~0x17 2303 REG16 CFG6_18_23[12]; //0x18~0x23 2304 REG16 pkt_converter[4]; //0x24~0x27 2305 #define TSP_PKT_CONVERTER_MODE_MASK 0x0007 2306 #define TSP_PKT_188Mode 0 2307 #define TSP_PKT_CIMode 1 2308 #define TSP_PKT_OpenCableMode 2 2309 #define TSP_PKT_ATSMode 3 2310 #define TSP_PKT_MxLMode 4 2311 #define TSP_PKT_NagraDongleMode 5 2312 #define TSP_PKT_FORCE_SYNC_47 0x0008 2313 #define TSP_BYPASS_PKT_CONVERTER 0x0010 2314 #define TSP_BYPASS_SRC_ID_PARSER 0x0020 2315 #define TSP_SRC_ID_FLT_EN 0x0040 2316 #define TSP_MXL_PKT_HEADER_MASK 0x0F80 //add pkt num 2317 #define TSP_MXL_PKT_HEADER_SHIFT 7 2318 REG16 CFG6_28_29[2]; 2319 REG16 CFG6_2A; 2320 #define CLR_PKT_CONVERTER_OVERFLOW 0x0001 2321 #define TSP_TSIF0_TSO_BLK_EN 0x0002 2322 #define TSP_TSIF0_TS1_BLK_EN 0x0004 2323 #define TSP_TSIF0_TS2_BLK_EN 0x0008 2324 #define TSP_TSIF0_TS3_BLK_EN 0x0010 2325 #define FIXED_TIMESTAMP_RING_BACK_EN 0x0080 2326 #define FIXED_LPCR_RING_BACK_EN 0x0400 2327 #define PVR_WRITE_POINTER_TO_NEXT_ADDRESS_EN 0x0800 2328 #define FIXED_VQ_MIU_REG_FLUSH 0x2000 2329 REG16 CFG6_2B; 2330 #define TSP_RESET_WB_DMA_FSM_TSIF1 0x0001 2331 #define TSP_RESET_WB_DMA_FSM_TSIF2 0x0002 2332 #define TSP_RESET_WB_DMA_FSM_TSIF3 0x0004 2333 #define TSP_RESET_WB_DMA_FSM_TSIF4 0x0008 2334 #define TSP_ECO_FIQ_INPUT 0x0100 2335 #define TSP_ECO_TS_SYNC_OUT_DELAY 0x0200 2336 #define TSP_ECO_TS_SYNC_OUT_REVERSE_BLOCK 0x0400 2337 #define TSP_FIX_FILTER_NULL_PKT 0x4000 2338 REG16 CFG6_2C_2F[4]; 2339 REG32 CFG6_30_31; // filein0 lower DMA read bound 2340 REG32 CFG6_32_33; // filein0 upper DMA read bound 2341 REG32 CFG6_34_35; // filein1 lower DMA read bound 2342 REG32 CFG6_36_37; // filein1 upper DMA read bound 2343 REG32 CFG6_38_39; // filein2 lower DMA read bound 2344 REG32 CFG6_3A_3B; // filein2 upper DMA read bound 2345 REG32 CFG6_3C_3D; // filein3 lower DMA read bound 2346 REG32 CFG6_3E_3F; // filein3 upper DMA read bound 2347 #define TSP_FILEIN_DMAR_BND_MASK 0x0FFFFFFFUL 2348 REG16 CFG6_40_47[8]; // @Not used 2349 REG32 CFG6_48_49; // mmfi0 lower DMA read bound 2350 REG32 CFG6_4A_4B; // mmfi0 upper DMA read bound 2351 REG32 CFG6_4C_4D; // mmfi1 lower DMA read bound 2352 REG32 CFG6_4E_4F; // mmfi1 upper DMA read bound 2353 #define TSP_MMFI_DMAR_BND_MASK 0x0FFFFFFFUL 2354 REG32 CFG6_50_51; // initial packet timestamp value (tsif0) 2355 REG32 CFG6_52_53; // initial packet timestamp value (tsif1) 2356 REG32 CFG6_54_55; // initial packet timestamp value (tsif2) 2357 REG32 CFG6_56_57; // initial packet timestamp value (tsif3) 2358 REG16 CFG6_58_5B[4]; // @Not used 2359 REG32 CFG6_5C_5D; // initial packet timestamp value (mmfi0) 2360 REG32 CFG6_5E_5F; // initial packet timestamp value (mmfi1) 2361 2362 REG16 CFG6_60; 2363 #define TSP_INIT_TIMESTAMP_RESTART_EN 0x0008 2364 2365 REG16 CFG6_61_6B[11]; // @Not used 2366 2367 2368 REG16 CFG6_6C; // reg_reset_ctrl5 2369 #define CFG6_6C_REG_RESET_PATH0 0x0001 2370 #define CFG6_6C_REG_RESET_PATH1 0x0002 2371 #define CFG6_6C_REG_RESET_PATH2 0x0004 2372 #define CFG6_6C_REG_RESET_PATH3 0x0008 2373 #define CFG6_6C_REG_RESET_PATH4 0x0010 2374 #define CFG6_6C_REG_RESET_PATH5 0x0020 2375 2376 #define CFG6_6C_REG_RESET_OTV 0x0100 2377 #define CFG6_6C_REG_RESET_DEBUG_TABLE 0x0200 2378 #define CFG6_6C_REG_RESET_DMA_ENG 0x0400 2379 #define CFG6_6C_REG_RESET_SEC_CMP 0x0800 2380 #define CFG6_6C_REG_RESET_SECFLT_REG 0x1000 2381 #define CFG6_6C_REG_RESET_SEC 0x2000 2382 #define CFG6_6C_REG_RESET_PID_TABLE 0x4000 2383 2384 REG16 CFG6_6D; // reg_clk_gating_fiq 2385 #define CFG6_6D_REG_CLK_GATING_FIQ0 0x0001 2386 #define CFG6_6D_REG_CLK_GATING_FIQ1 0x0002 2387 #define CFG6_6D_REG_CLK_GATING_FIQ2 0x0004 2388 #define CFG6_6D_REG_CLK_GATING_FIQ3 0x0008 2389 #define CFG6_6D_REG_CLK_GATING_FIQ4 0x0010 2390 #define CFG6_6D_REG_CLK_GATING_FIQ5 0x0020 2391 2392 #define CFG6_6D_REG_MIU_CLK_GATING_FIQ0 0x0100 2393 #define CFG6_6D_REG_MIU_CLK_GATING_FIQ1 0x0200 2394 #define CFG6_6D_REG_MIU_CLK_GATING_FIQ2 0x0400 2395 #define CFG6_6D_REG_MIU_CLK_GATING_FIQ3 0x0800 2396 #define CFG6_6D_REG_MIU_CLK_GATING_FIQ4 0x1000 2397 #define CFG6_6D_REG_MIU_CLK_GATING_FIQ5 0x2000 2398 2399 REG16 CFG6_6E_78[11]; // @Not used 2400 2401 REG16 CFG6_79; //reg_clk_gating 2402 #define CFG6_79_REG_CLK_GATING_PATH0 0x0001 2403 #define CFG6_79_REG_CLK_GATING_PATH1 0x0002 2404 #define CFG6_79_REG_CLK_GATING_PATH2 0x0004 2405 #define CFG6_79_REG_CLK_GATING_PATH3 0x0008 2406 #define CFG6_79_REG_CLK_GATING_PATH4 0x0010 2407 #define CFG6_79_REG_CLK_GATING_PATH5 0x0020 2408 #define CFG6_79_REG_CLK_GATING_TSP_ENG 0x0040 2409 2410 #define CFG6_79_REG_CLK_GATING_FIQ 0x0080 2411 #define CFG6_79_REG_CLK_GATING_PVR1 0x0100 2412 #define CFG6_79_REG_CLK_GATING_PVR2 0x0200 2413 #define CFG6_79_REG_CLK_GATING_PVR3 0x0400 2414 #define CFG6_79_REG_CLK_GATING_PVR4 0x0800 2415 REG16 CFG6_7A; //reg_reset_ctrl0 2416 #define CFG6_7A_REG_CLK_RESET_PKT_CONVERTER0 0x0001 2417 #define CFG6_7A_REG_CLK_RESET_PKT_CONVERTER1 0x0002 2418 #define CFG6_7A_REG_CLK_RESET_PKT_CONVERTER2 0x0004 2419 #define CFG6_7A_REG_CLK_RESET_PKT_CONVERTER3 0x0008 2420 #define CFG6_7A_REG_CLK_RESET_PKT_CONVERTER4 0x0010 2421 #define CFG6_7A_REG_CLK_RESET_PKT_CONVERTER5 0x0020 2422 2423 #define CFG6_7A_REG_CLK_RESET_FIQ0 0x0100 2424 #define CFG6_7A_REG_CLK_RESET_FIQ1 0x0200 2425 #define CFG6_7A_REG_CLK_RESET_FIQ2 0x0400 2426 #define CFG6_7A_REG_CLK_RESET_FIQ3 0x0800 2427 #define CFG6_7A_REG_CLK_RESET_FIQ4 0x1000 2428 #define CFG6_7A_REG_CLK_RESET_FIQ5 0x2000 2429 REG16 CFG6_7B; //reg_reset_ctrl1 2430 #define CFG6_7B_REG_RESET_VQ_TX0 0x0001 2431 #define CFG6_7B_REG_RESET_VQ_TX1 0x0002 2432 #define CFG6_7B_REG_RESET_VQ_TX2 0x0004 2433 #define CFG6_7B_REG_RESET_VQ_TX3 0x0008 2434 #define CFG6_7B_REG_RESET_VQ_TX4 0x0010 2435 #define CFG6_7B_REG_RESET_VQ_TX5 0x0020 2436 #define CFG6_7B_REG_RESET_VQ_RX 0x0040 2437 #define CFG6_7B_REG_RESET_VQ_TOP 0x0080 2438 2439 #define CFG6_7B_REG_RESET_PKT_DEMUX0 0x0100 2440 #define CFG6_7B_REG_RESET_PKT_DEMUX1 0x0200 2441 #define CFG6_7B_REG_RESET_PKT_DEMUX2 0x0400 2442 #define CFG6_7B_REG_RESET_PKT_DEMUX3 0x0800 2443 #define CFG6_7B_REG_RESET_PKT_DEMUX4 0x1000 2444 #define CFG6_7B_REG_RESET_PKT_DEMUX5 0x2000 2445 REG16 CFG6_7C; //reg_reset_ctrl2 2446 #define CFG6_7C_REG_RESET_PVR1 0x0001 2447 #define CFG6_7C_REG_RESET_PVR2 0x0002 2448 #define CFG6_7C_REG_RESET_PVR3 0x0004 2449 #define CFG6_7C_REG_RESET_PVR4 0x0008 2450 2451 #define CFG6_7C_REG_RESET_TIMESTAMP_SEL_PVR1 0x0010 2452 #define CFG6_7C_REG_RESET_TIMESTAMP_SEL_PVR2 0x0020 2453 #define CFG6_7C_REG_RESET_TIMESTAMP_SEL_PVR3 0x0040 2454 #define CFG6_7C_REG_RESET_TIMESTAMP_SEL_PVR4 0x0080 2455 2456 #define CFG6_7C_REG_RESET_SP_D0 0x0100 2457 #define CFG6_7C_REG_RESET_SP_D1 0x0200 2458 #define CFG6_7C_REG_RESET_SP_D2 0x0400 2459 #define CFG6_7C_REG_RESET_SP_D3 0x0800 2460 #define CFG6_7C_REG_RESET_SP_D4 0x1000 2461 #define CFG6_7C_REG_RESET_SP_D5 0x2000 2462 REG16 CFG6_7D; //reg_reset_ctrl3 2463 #define CFG6_7D_REG_RESET_FILTER_NULL_PKT0 0x0001 2464 #define CFG6_7D_REG_RESET_FILTER_NULL_PKT1 0x0002 2465 #define CFG6_7D_REG_RESET_FILTER_NULL_PKT2 0x0004 2466 #define CFG6_7D_REG_RESET_FILTER_NULL_PKT3 0x0008 2467 #define CFG6_7D_REG_RESET_FILTER_NULL_PKT4 0x0010 2468 #define CFG6_7D_REG_RESET_FILTER_NULL_PKT5 0x0020 2469 2470 #define CFG6_7D_REG_RESET_DIRECTV_130_188_0 0x0100 2471 #define CFG6_7D_REG_RESET_DIRECTV_130_188_1 0x0200 2472 #define CFG6_7D_REG_RESET_DIRECTV_130_188_2 0x0400 2473 #define CFG6_7D_REG_RESET_DIRECTV_130_188_3 0x0800 2474 #define CFG6_7D_REG_RESET_DIRECTV_130_188_4 0x1000 2475 #define CFG6_7D_REG_RESET_DIRECTV_130_188_5 0x2000 2476 REG16 CFG6_7E; //reg_reset_ctrl4 2477 #define CFG6_7E_REG_RESET_SRC_ID_PARSER0 0x0001 2478 #define CFG6_7E_REG_RESET_SRC_ID_PARSER1 0x0002 2479 #define CFG6_7E_REG_RESET_SRC_ID_PARSER2 0x0004 2480 #define CFG6_7E_REG_RESET_SRC_ID_PARSER3 0x0008 2481 #define CFG6_7E_REG_RESET_SRC_ID_PARSER4 0x0010 2482 #define CFG6_7E_REG_RESET_SRC_ID_PARSER5 0x0020 2483 2484 #define CFG6_7E_REG_RESET_PCRFLT_0 0x0100 2485 #define CFG6_7E_REG_RESET_PCRFLT_1 0x0200 2486 #define CFG6_7E_REG_RESET_PCRFLT_2 0x0400 2487 #define CFG6_7E_REG_RESET_PCRFLT_3 0x0800 2488 #define CFG6_7E_REG_RESET_PCRFLT_4 0x1000 2489 #define CFG6_7E_REG_RESET_PCRFLT_5 0x2000 2490 REG16 CFG6_7F; //reg_miu_clk_gating 2491 #define CFG6_7F_REG_MIU_CLK_GATING_PATH0 0x0001 // no use 2492 #define CFG6_7F_REG_MIU_CLK_GATING_PATH1 0x0002 2493 #define CFG6_7F_REG_MIU_CLK_GATING_PATH2 0x0004 2494 #define CFG6_7F_REG_MIU_CLK_GATING_PATH3 0x0008 2495 #define CFG6_7F_REG_MIU_CLK_GATING_PATH4 0x0010 2496 #define CFG6_7F_REG_MIU_CLK_GATING_PATH5 0x0020 2497 #define CFG6_7F_REG_MIU_CLK_GATING_TSP_ENG 0x0040 // only for section 2498 2499 #define CFG6_7F_REG_MIU_CLK_GATING_FIQ 0x0080 // TBD no use in k6lite 2500 #define CFG6_7F_REG_MIU_CLK_GATING_PVR1 0x0100 // TBD no use in k6lite 2501 #define CFG6_7F_REG_MIU_CLK_GATING_PVR2 0x0200 // TBD no use in k6lite 2502 #define CFG6_7F_REG_MIU_CLK_GATING_PVR3 0x0400 // TBD no use in k6lite 2503 #define CFG6_7F_REG_MIU_CLK_GATING_PVR4 0x0800 // TBD no use in k6lite 2504 #define CFG6_7F_REG_MIU_CLK_GATING_MMFI0 0x1000 // TBD no use in k6lite 2505 #define CFG6_7F_REG_MIU_CLK_GATING_MMFI1 0x2000 // TBD no use in k6lite 2506 } REG_Ctrl6; 2507 2508 //TSP9 2509 typedef struct _REG_Ctrl7 2510 { 2511 REG16 CFG7_00_03[4]; //SPD CTR mode counter IV 2512 REG16 CFG7_04; //SPD CTR mode IV MAX (FILEIN) 2513 #define CFG7_04_CTR_IV_SPD_MAX_1K 0x0001 2514 #define CFG7_04_CTR_IV_SPD_MAX_2K 0x0002 2515 #define CFG7_04_CTR_IV_SPD_MAX_4K 0x0004 2516 #define CFG7_04_CTR_IV_SPD_MAX_8K 0x0008 2517 #define CFG7_04_CTR_IV_SPD_MAX_16K 0x0010 2518 #define CFG7_04_CTR_IV_SPD_MAX_32K 0x0020 2519 #define CFG7_04_CTR_IV_SPD_MAX_64K 0x0040 2520 #define CFG7_04_CTR_IV_SPD_MAX_128K 0x0080 2521 REG16 CFG7_05; //SPD CTR mode control (FILEIN) 2522 #define CFG7_05_CTR_MODE_SPD_FILEIN 0x0001 2523 #define CFG7_05_UPDATE_CTR_MODE_CNT_IV_SPD_FILEIN 0x0002 2524 #define CFG7_05_LOAD_INIT_CNT_SPD 0x0004 2525 #define CFG7_05_SPD_ONEWAY 0x8000 2526 REG16 CFG7_06_0F[10]; 2527 } REG_Ctrl7; 2528 2529 //TSP10 2530 typedef struct _REG_Ctrl8 2531 { 2532 REG16 CFG8_00_03[4]; //SPS CTR mode counter IV 2533 REG16 CFG8_04; //SPS CTR mode IV MAX (PVR 1) 2534 #define CFG8_04_CTR_IV_SPS_MAX_1K 0x0001 2535 #define CFG8_04_CTR_IV_SPS_MAX_2K 0x0002 2536 #define CFG8_04_CTR_IV_SPS_MAX_4K 0x0004 2537 #define CFG8_04_CTR_IV_SPS_MAX_8K 0x0008 2538 #define CFG8_04_CTR_IV_SPS_MAX_16K 0x0010 2539 #define CFG8_04_CTR_IV_SPS_MAX_32K 0x0020 2540 #define CFG8_04_CTR_IV_SPS_MAX_64K 0x0040 2541 #define CFG8_04_CTR_IV_SPS_MAX_128K 0x0080 2542 REG16 CFG8_05; //SPS CTR mode control (PVR 1) 2543 #define CFG8_05_CTR_MODE_SPS_PVR1 0x0001 2544 #define CFG8_05_UPDATE_CTR_MODE_CNT_IV_SPS_PVR1 0x0002 2545 #define CFG8_05_LOAD_INIT_CNT_SPS1 0x0004 2546 #define CFG8_05_SPS_ONEWAY1 0x8000 2547 REG16 CFG8_06_0F[10]; 2548 } REG_Ctrl8; 2549 2550 typedef struct _REG_Ctrl8_1 2551 { 2552 REG16 CFG8_40; //reg_hw10_config0 2553 #define CFG8_40_REG_VID3_SRC_MASK 0x0007 2554 #define CFG8_40_REG_VID3_SRC_SHIFT 0 2555 #define CFG8_40_VPES3_ERR_RM_EN 0x0008 2556 #define CFG8_40_DUP_PKT_SKIP_V3 0x0010 2557 #define CFG8_40_MASK_SCR_V3_EN 0x0020 2558 #define CFG8_40_PS_VID3_EN 0x0040 2559 #define CFG8_40_V3_BLOCK_DIS 0x0080 2560 #define CFG8_40_RESET_VFIFO_3 0x0100 2561 REG16 CFG8_41; //reg_hw10_config1 2562 #define CFG8_41_REG_VID4_SRC_MASK 0x0007 2563 #define CFG8_41_REG_VID4_SRC_SHIFT 0 2564 #define CFG8_41_VPES4_ERR_RM_EN 0x0008 2565 #define CFG8_41_DUP_PKT_SKIP_V4 0x0010 2566 #define CFG8_41_MASK_SCR_V4_EN 0x0020 2567 #define CFG8_41_PS_VID4_EN 0x0040 2568 #define CFG8_41_V4_BLOCK_DIS 0x0080 2569 #define CFG8_41_RESET_VFIFO_4 0x0100 2570 REG16 CFG8_42; 2571 //reg_pcr2_src 2572 #define CFG8_42_PCR2_SRC_MASK 0x000F 2573 #define CFG8_42_PCR2_SRC_SHIFT 0 2574 #define CFG8_42_PCR2_SRC_TSIF0 0x0 2575 #define CFG8_42_PCR2_SRC_TSIF1 0x1 2576 #define CFG8_42_PCR2_SRC_TSIF2 0x2 2577 #define CFG8_42_PCR2_SRC_TSIF3 0x3 2578 #define CFG8_42_PCR2_SRC_TSIF4 0x4 2579 #define CFG8_42_PCR2_SRC_TSIF5 0x5 2580 #define CFG8_42_PCR2_SRC_PKT_MERGE0 0x8 2581 #define CFG8_42_PCR2_SRC_PKT_MERGE1 0x9 2582 #define CFG8_42_PCR2_SRC_MM_FILEIN0 0xa 2583 #define CFG8_42_PCR2_SRC_MM_FILEIN1 0xb 2584 #define CFG8_42_PCR2_SRC_FIQ0 0xc 2585 #define CFG8_42_PCR2_SRC_FIQ1 0xd 2586 //reg_tei_skip_pkt_pcr2 2587 #define CFG8_42_REG_TEI_SKIP_PKT_PCR2 0x0010 2588 //reg_pcr2_id_sel 2589 #define CFG8_42_REG_PCR2_ID_SEL_MASK 0x00E0 2590 #define CFG8_42_REG_PCR2_ID_SEL_SHIFT 5 2591 //reg_pcr2_reset 2592 #define CFG8_42_REG_PCR2_RESET 0x0100 2593 //reg_pcr2_read 2594 #define CFG8_42_REG_PCR2_READ 0x0200 2595 REG16 CFG8_43; 2596 //reg_pcr3_src 2597 #define CFG8_43_PCR3_SRC_MASK 0x000F 2598 #define CFG8_43_PCR3_SRC_SHIFT 0 2599 #define CFG8_43_PCR3_SRC_TSIF0 0x0 2600 #define CFG8_43_PCR3_SRC_TSIF1 0x1 2601 #define CFG8_43_PCR3_SRC_TSIF2 0x2 2602 #define CFG8_43_PCR3_SRC_TSIF3 0x3 2603 #define CFG8_43_PCR3_SRC_TSIF4 0x4 2604 #define CFG8_43_PCR3_SRC_TSIF5 0x5 2605 #define CFG8_43_PCR3_SRC_PKT_MERGE0 0x8 2606 #define CFG8_43_PCR3_SRC_PKT_MERGE1 0x9 2607 #define CFG8_43_PCR3_SRC_MM_FILEIN0 0xa 2608 #define CFG8_43_PCR3_SRC_MM_FILEIN1 0xb 2609 #define CFG8_43_PCR3_SRC_FIQ0 0xc 2610 #define CFG8_43_PCR3_SRC_FIQ1 0xd 2611 //reg_tei_skip_pkt_pcr3 2612 #define CFG8_43_REG_TEI_SKIP_PKT_PCR3 0x0010 2613 //reg_pcr3_id_sel 2614 #define CFG8_43_REG_PCR3_ID_SEL_MASK 0x00E0 2615 #define CFG8_43_REG_PCR3_ID_SEL_SHIFT 5 2616 //reg_pcr3_reset 2617 #define CFG8_43_REG_PCR3_RESET 0x0100 2618 //reg_pcr3_read 2619 #define CFG8_43_REG_PCR3_READ 0x0200 2620 REG16 CFG8_44; //reg_pidflt_pcr2 2621 #define CFG8_44_PIDFLT_PCR2_PID_MASK 0x1FFF 2622 #define CFG8_44_PIDFLT_PCR2_EN 0x8000 2623 REG16 CFG8_45; //reg_pidflt_pcr3 2624 #define CFG8_45_PIDFLT_PCR3_PID_MASK 0x1FFF 2625 #define CFG8_45_PIDFLT_PCR3_EN 0x8000 2626 REG16 CFG8_46; 2627 //reg_pidflt_pcr2_scr_id 2628 #define CFG8_46_REG_PIDFLT_PCR2_SRC_ID_MASK 0x000F 2629 #define CFG8_46_REG_PIDFLT_PCR2_SRC_ID_SHIFT 0 2630 //reg_pidflt_pcr3_scr_id 2631 #define CFG8_46_REG_PIDFLT_PCR3_SRC_ID_MASK 0x0F00 2632 #define CFG8_46_REG_PIDFLT_PCR3_SRC_ID_SHIFT 8 2633 REG16 CFG8_47; //reg_hw10_config2 2634 //reg_ps_mode_src_a 2635 #define CFG8_47_REG_PS_MODE_SRC_A_MASK 0x0007 2636 #define CFG8_47_REG_PS_MODE_SRC_A_SHIFT 0 2637 //reg_ps_mode_src_ad 2638 #define CFG8_47_REG_PS_MODE_SRC_AD_MASK 0x0070 2639 #define CFG8_47_REG_PS_MODE_SRC_AD_SHIFT 4 2640 //reg_ps_mode_src_ac 2641 #define CFG8_47_REG_PS_MODE_SRC_AC_MASK 0x0700 2642 #define CFG8_47_REG_PS_MODE_SRC_AC_SHIFT 8 2643 //reg_ps_mode_src_add 2644 #define CFG8_47_REG_PS_MODE_SRC_ADD_MASK 0x7000 2645 #define CFG8_47_REG_PS_MODE_SRC_ADD_SHIFT 12 2646 REG16 CFG8_48; //reg_hw10_config3 2647 //reg_ps_mode_src_v 2648 #define CFG8_48_REG_PS_MODE_SRC_V_MASK 0x0007 2649 #define CFG8_48_REG_PS_MODE_SRC_V_SHIFT 0 2650 //reg_ps_mode_src_v3d 2651 #define CFG8_48_REG_PS_MODE_SRC_V3D_MASK 0x0070 2652 #define CFG8_48_REG_PS_MODE_SRC_V3D_SHIFT 4 2653 //reg_ps_mode_src_v3 2654 #define CFG8_48_REG_PS_MODE_SRC_V3_MASK 0x0700 2655 #define CFG8_48_REG_PS_MODE_SRC_V3_SHIFT 8 2656 //reg_ps_mode_src_v4 2657 #define CFG8_48_REG_PS_MODE_SRC_V4_MASK 0x7000 2658 #define CFG8_48_REG_PS_MODE_SRC_V4_SHIFT 12 2659 REG16 CFG8_49_4F[7]; 2660 REG32 CFG8_50_51; //reg_synth0 2661 REG32 CFG8_52_53; //reg_synth1 2662 REG32 CFG8_54_55; //reg_pcr64_3_riu(Low) 2663 REG32 CFG8_56_57; //reg_pcr64_3_riu(High) 2664 REG32 CFG8_58_59; //reg_synth2 2665 REG32 CFG8_5A_5B; //reg_pcr64_4_riu(Low) 2666 REG32 CFG8_5C_5D; //reg_pcr64_4_riu(High) 2667 REG32 CFG8_5E_5F; //reg_synth3 2668 REG32 CFG8_60_61; //reg_pcr2_valid 2669 REG16 CFG8_62; //reg_pcr2_valid_33 2670 REG32 CFG8_63_64; //reg_pcr3_valid 2671 REG16 CFG8_65; //reg_pcr3_valid_33 2672 2673 } REG_Ctrl8_1; 2674 2675 2676 #endif 2677