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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regTSP.h 98 // Description: Transport Stream Processor (TSP) Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _TSP_REG_H_ 103 #define _TSP_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 #define TS_PACKET_SIZE 188UL 137 138 139 //-------------------------------------------------------------------------------------------------- 140 // Compliation Option 141 //-------------------------------------------------------------------------------------------------- 142 #define TSP_LIVE_AV_BLOCK_EN //for maserati , live path should enable AV fifo block, since dscmb behavior change 143 144 145 //[CMODEL][FWTSP] 146 // When enable, interrupt will not lost, CModel will block next packet 147 // and FwTSP will block until interrupt status is clear by MIPS. 148 // (For firmware and cmodel only) 149 #define TSP_DBG_SAFE_MODE_ENABLE 0UL 150 151 //------------------------------------------------------------------------------------------------- 152 // Harware Capability 153 //------------------------------------------------------------------------------------------------- 154 #define TSP_PIDFLT_NUM 128UL 155 #define TSP_PIDFLT_EXT_NUM 16UL 156 157 #define TSP_PVR_IF_NUM 2UL 158 #define TSP_MMFI0_FILTER_NUM 4UL 159 #define TSP_MMFI1_FILTER_NUM 4UL 160 #define TSP_IF_NUM 4UL 161 #define TSP_DEMOD_NUM 2UL 162 #define TSP_VFIFO_NUM 2UL 163 #define TSP_AFIFO_NUM 4UL 164 #define TSP_TS_PAD_NUM 6UL // 4P+2S or 5P 165 #define TSP_VQ_NUM 4UL //VQ0, VQ_file, VQ1, VQ_2 166 #define TSP_VQ_PITCH 208UL 167 #define TSP_CA_ENGINE_NUM 4UL 168 #define TSP_CA_KEY_NUM 8UL 169 #define TSP_CA0_FLT_NUM 144UL 170 #define TSP_CA1_FLT_NUM 144UL 171 #define TSP_CA_FLT_NUM 144UL 172 #define TSP_MERGESTR_MUM 8UL 173 #define TSP_ENGINE_NUM 1UL 174 #define TSP_SECFLT_NUM 128UL 175 #define TSP_PCRFLT_NUM 4UL 176 #define TSP_STC_NUM 4UL 177 178 #ifdef HWPCR_ENABLE 179 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM+TSP_PIDFLT_EXT_NUM+TSP_PCRFLT_NUM) 180 #else 181 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM+TSP_PIDFLT_EXT_NUM) 182 #endif 183 184 #define TSP_SECBUF_NUM TSP_SECFLT_NUM 185 #define TSP_FILTER_DEPTH 16UL 186 187 #define TSP_WP_SET_NUM 4UL 188 189 #define DSCMB_FLT_START_ID 16UL 190 #define DSCMB_FLT_END_ID 31UL 191 #define DSCMB_FLT_NUM 16UL 192 193 #define DSCMB1_FLT_START_ID 32UL 194 #define DSCMB1_FLT_END_ID 47UL 195 #define DSCMB1_FLT_NUM 16UL 196 197 #define DSCMB2_FLT_START_ID 48UL 198 #define DSCMB2_FLT_END_ID 63UL 199 #define DSCMB2_FLT_NUM 16UL 200 201 #define DSCMB3_FLT_START_ID 64UL 202 #define DSCMB3_FLT_END_ID 95UL 203 #define DSCMB3_FLT_NUM 16UL 204 205 #define DSCMB_FLT_SHAREKEY_START_ID 96UL 206 #define DSCMB_FLT_SHAREKEY_END_ID 143UL 207 #define DSCMB_FLT_SHAREKEY_NUM 144UL 208 209 #define DSCMB_FLT_SHAREKEY1_START_ID 96UL 210 #define DSCMB_FLT_SHAREKEY1_END_ID 143UL 211 #define DSCMB_FLT_SHAREKEY1_NUM 144UL 212 213 #define DSCMB_FLT_SHAREKEY2_START_ID 96UL 214 #define DSCMB_FLT_SHAREKEY2_END_ID 143UL 215 #define DSCMB_FLT_SHAREKEY2_NUM 144UL 216 217 #define TSP_NMATCH_FLTID 17UL 218 219 220 //PAD MUX definition 221 #define TSP_MUX_TS0 0UL 222 #define TSP_MUX_TS1 1UL 223 #define TSP_MUX_TS2 2UL 224 #define TSP_MUX_TS3 3UL 225 #define TSP_MUX_TS4 4UL 226 #define TSP_MUX_TS5 5UL 227 #define TSP_MUX_TSO 6UL 228 #define TSP_MUX_INDEMOD 7UL 229 #define TSP_MUX_3WIRE_MASK 0x80UL 230 #define TSP_MUX_TSCB 0xFFUL //not support 231 #define TSP_MUX_NONE 0xFF 232 233 //Clk source definition 234 #define TSP_CLK_DISABLE 0x01UL 235 #define TSP_CLK_INVERSE 0x02UL 236 #define TSP_CLK_TS0 0x00UL 237 #define TSP_CLK_TS1 0x04UL 238 #define TSP_CLK_TS2 0x08UL 239 #define TSP_CLK_TS3 0x0CUL 240 #define TSP_CLK_TS4 0x10UL 241 #define TSP_CLK_TS5 0x14UL 242 #define TSP_CLK_TSOOUT 0x18UL 243 #define TSP_CLK_INDEMOD 0x1CUL 244 #define CLKGEN0_TSP_CLK_MASK 0x1CUL 245 #define TSP_CLK_TSCB 0xFFUL //not support 246 247 //PIDFLT1,2 source definition 248 #define TSP_PIDFLT1_USE_TSIF1 0UL 249 #define TSP_PIDFLT2_USE_TSIF2 1UL 250 #define TSP_PIDFLT1_USE_TSIF_MMFI0 2UL 251 #define TSP_PIDFLT2_USE_TSIF_MMFI1 3UL 252 253 254 #define TSP_FW_DEVICE_ID 0x67UL 255 256 #define STC_SYNTH_DEFAULT 0x14000000UL 257 258 #define DRAM_SIZE (0x80000000UL) 259 #define TSP_FW_BUF_SIZE (0x4000UL) 260 #define TSP_FW_BUF_LOW_BUD 0UL 261 #define TSP_FW_BUF_UP_BUD DRAM_SIZE 262 263 #define TSP_VQ_BUF_LOW_BUD 0UL 264 #define TSP_VQ_BUF_UP_BUD (0xFFFFFFFFUL) 265 266 #define TSP_SEC_BUF_LOW_BUD 0UL 267 #define TSP_SEC_BUF_UP_BUD (0xFFFFFFFFUL) 268 #define TSP_SEC_FLT_DEPTH 32UL 269 #define TSP_FIQ_NUM 1UL 270 271 //QMEM Setting 272 #define _TSP_QMEM_I_MASK 0xffff8000UL //total: 0x4000 273 #define _TSP_QMEM_I_ADDR_HIT 0x00000000UL 274 #define _TSP_QMEM_I_ADDR_MISS 0xffffffffUL 275 #define _TSP_QMEM_D_MASK 0xffff8000UL 276 #define _TSP_QMEM_D_ADDR_HIT 0x00000000UL 277 #define _TSP_QMEM_D_ADDR_MISS 0xffffffffUL 278 #define _TSP_QMEM_SIZE 0x1000UL // 16K bytes, 32bit aligment //0x4000 279 280 //------------------------------------------------------------------------------------------------- 281 // Type and Structure 282 //------------------------------------------------------------------------------------------------- 283 284 // Software 285 #define REG_PIDFLT_L_BASE (0x00210000UL << 1UL) // Fit the size of REG32, 0~127 286 #define REG_PIDFLT_H_BASE (0x00210800UL << 1UL) // Fit the size of REG32, 0~127 287 288 #define REG_PIDFLT_L_EXT_BASE (0x00210400UL << 1UL) // Fit the size of REG32, 128~143 289 #define REG_PIDFLT_H_EXT_BASE (0x00210C00UL << 1UL) // Fit the size of REG32, 128~143 290 291 #define REG_SECFLT_BASE1 (0x00211000UL << 1UL) // Fix the size of REG32 292 #define REG_SECFLT_BASE2 (0x00215000UL << 1UL) // Fix the size of REG32 293 294 #define REG_CTRL_BASE (0x2A00UL) // 0xBF800000+(1500/2)*4 295 #define REG_CTRL_MMFIBASE (0x39C0UL) // 0xBF800000+(3800/2)*4 (TSP2: debug table), from 0x70 296 #define REG_CTRL_TSP3 (0xC1440UL) // 0xBF800000+(60a20/2)*4 297 #define REG_CTRL_TSP4 (0xC2E00UL) // 0xBF800000+(61700/2)*4 298 #define REG_CTRL_TSP5 (0xC7600UL) // 0xBF800000+(63b00/2)*4 299 #define REG_CTRL_TSP6 (0xC3E00UL) // 0xBF800000+(61f00/2)*4 300 #define REG_CTRL_TS_SAMPLE (0x21400UL) // 0xBF800000+(10A00/2)*4 301 302 typedef struct _REG32 303 { 304 volatile MS_U16 L; 305 volatile MS_U16 empty_L; 306 volatile MS_U16 H; 307 volatile MS_U16 empty_H; 308 } REG32; 309 310 typedef struct _REG32_L 311 { 312 volatile MS_U32 data; 313 volatile MS_U32 _resv; 314 } REG32_L; 315 316 typedef struct _REG16 317 { 318 volatile MS_U16 u16data; 319 volatile MS_U16 _null; 320 } REG16; 321 322 typedef REG32 REG_PidFlt; 323 324 //******************** PIDFLT DEFINE START ********************// 325 // PID 326 #define TSP_PIDFLT_PID_MASK 0x00001FFFUL 327 #define TSP_PIDFLT_PID_SHFT 0UL 328 329 // PIDFLT SRC 330 #define TSP_PIDFLT_IN_MASK 0x0000E000UL 331 #define TSP_PIDFLT_IN_NONE 0x00000000UL 332 #define TSP_PIDFLT_IN_PIDFLT0 0x00002000UL 333 #define TSP_PIDFLT_IN_PIDFLT_FILE 0x00004000UL 334 #define TSP_PIDFLT_IN_PIDFLT1 0x00006000UL 335 #define TSP_PIDFLT_IN_PIDFLT2 0x00008000UL 336 #define TSP_PIDFLT_IN_PIDFLT_CB 0UL //not support 337 #define TSP_PIDFLT_IN_SHIFT 13UL 338 339 // Section filter Id (0~128) 340 #define TSP_PIDFLT_SECFLT_MASK 0x000007F0UL // [38:32] secflt id 341 #define TSP_PIDFLT_SECFLT_SHFT 4UL 342 343 // Stream source ID 344 #define TSP_PIDFLT_IN_SRC_MASK 0x0000000FUL // [42:39] stream source id 345 #define TSP_PIDFLT_IN_SRC_SHFT 0UL 346 347 // AF/Sec/Video/V3D/Audio/Audio-second/PVR1/PVR2 348 #define TSP_PIDFLT_OUT_MASK 0xFFE00000UL 349 #define TSP_PIDFLT_OUT_NONE 0x00000000UL 350 #define TSP_PIDFLT_RUSH_PASS 0x00100000UL 351 #define TSP_PIDFLT_OUT_AFIFO4 0x00200000UL 352 #define TSP_PIDFLT_OUT_AFIFO3 0x00400000UL 353 #define TSP_PIDFLT_OUT_SECFLT_AF 0x01000000UL 354 #define TSP_PIDFLT_OUT_SECFLT 0x02000000UL 355 #define TSP_PIDFLT_OUT_VFIFO 0x04000000UL 356 #define TSP_PIDFLT_OUT_VFIFO3D 0x08000000UL 357 #define TSP_PIDFLT_OUT_AFIFO 0x10000000UL 358 #define TSP_PIDFLT_OUT_AFIFO2 0x20000000UL 359 #define TSP_PIDFLT_OUT_PVR1 0x80000000UL 360 #define TSP_PIDFLT_OUT_PVR2 0x40000000UL 361 362 #define TSP_PIDFLT_SECFLT_NULL 0x7FUL // software usage clean selected section filter 363 //******************** PIDFLT DEFINE END ********************// 364 365 typedef struct _REG_SecFlt 366 { 367 REG32 Ctrl; 368 // SW flag 369 #define TSP_SECFLT_TYPE_MASK 0x01000007UL 370 #define TSP_SECFLT_TYPE_SHFT 0UL 371 #define TSP_SECFLT_TYPE_SEC 0x00000000UL 372 #define TSP_SECFLT_TYPE_PES 0x00000001UL 373 #define TSP_SECFLT_TYPE_PKT 0x00000002UL 374 #define TSP_SECFLT_TYPE_PCR 0x00000003UL 375 #define TSP_SECFLT_TYPE_TTX 0x00000004UL 376 #define TSP_SECFLT_TYPE_VER 0x00000005UL 377 #define TSP_SECFLT_TYPE_EMM 0x00000006UL 378 #define TSP_SECFLT_TYPE_ECM 0x00000007UL 379 #define TSP_SECFLT_TYPE_SEC_NO_PUSI 0x01000000UL 380 381 #define TSP_SECFLT_PCRRST 0x00000010UL // for TSP_SECFLT_TYPE_PCR 382 383 #define TSP_SECFLT_MODE_MASK 0x00000030UL // software implementation 384 #define TSP_SECFLT_MODE_SHFT 4UL 385 #define TSP_SECFLT_MODE_CONTI 0x0UL 386 #define TSP_SECFLT_MODE_ONESHOT 0x1UL 387 #define TSP_SECFLT_MODE_CRCCHK 0x2UL 388 #define TSP_SECFLT_MODE_PESSCMCHK 0x3UL //Only for PES type checking SCMB status 389 390 #define TSP_SECFLT_STATE_MASK 0x000000C0UL // software implementation 391 #define TSP_SECFLT_STATE_SHFT 6UL 392 #define TSP_SECFLT_STATE_OVERFLOW 0x1UL 393 #define TSP_SECFLT_STATE_DISABLE 0x2UL 394 395 REG32 Match[TSP_FILTER_DEPTH/sizeof(MS_U32)]; 396 397 REG32 Mask[TSP_FILTER_DEPTH/sizeof(MS_U32)]; 398 399 REG32 BufStart; 400 #define TSP_SECFLT_BUFSTART_MASK 0xFFFFFFFFUL 401 402 REG32 BufEnd; 403 404 REG32 BufRead; 405 406 REG32 BufWrite; 407 408 REG32 BufCur; 409 410 REG32 RmnReqCnt; 411 #define TSP_SECFLT_OWNER_MASK 0x80000000UL 412 #define TSP_SECFLT_OWNER_SHFT 31UL 413 #define TSP_SECFLT_REQCNT_MASK 0x7FFF0000UL 414 #define TSP_SECFLT_REQCNT_SHFT 16UL 415 #define TSP_SECFLT_RMNCNT_MASK 0x0000FFFFUL 416 #define TSP_SECFLT_RMNCNT_SHFT 0UL 417 418 REG32 CRC32; 419 420 REG32 _x50[16]; // (0x210080-0x210050)/4 421 } REG_SecFlt; 422 423 424 typedef struct _REG_Stc 425 { 426 REG32 ML; 427 REG32_L H32; 428 } REG_Stc; 429 430 typedef struct _REG_Pid 431 { // Index(word) CPU(byte) Default 432 REG_PidFlt Flt[TSP_PIDFLT_NUM]; 433 } REG_Pid; 434 435 typedef struct _REG_Sec 436 { // Index(word) CPU(byte) Default 437 REG_SecFlt Flt[TSP_SECFLT_NUM]; 438 } REG_Sec; 439 440 typedef struct _REG_Ctrl 441 { 442 //---------------------------------------------- 443 // 0xBF802A00 MIPS direct access 444 //---------------------------------------------- 445 // Type Name Index(word) CPU(byte) MIPS(0x1500/2+index)*4 446 REG32 TsRec_Head20; // 0xbf802a00 0x00 447 #define TSP_HW_PVR_BUF_HEAD20_MASK 0xFFFF0000UL 448 #define TSP_HW_PVR_BUF_HEAD20_SHFT 16UL 449 450 REG32 TsRec_Head21_Mid20_Wptr; // 0xbf802a08 0x02 ,wptr & mid share same register 451 #define TSP_HW_PVR_BUF_HEAD21_MASK 0x000007FFUL 452 #define TSP_HW_PVR_BUF_HEAD21_SHFT 0UL 453 #define TSP_HW_PVR_BUF_MID20_MASK 0xFFFF0000UL 454 #define TSP_HW_PVR_BUF_MID20_SHFT 16UL 455 456 REG32 TsRec_Mid21_Tail20; // 0xbf802a10 0x04 457 #define TSP_HW_PVR_BUF_MID21_MASK 0x000007FFUL 458 #define TSP_HW_PVR_BUF_MID21_SHFT 0UL 459 #define TSP_HW_PVR_BUF_TAIL20_MASK 0xFFFF0000UL 460 #define TSP_HW_PVR_BUF_TAIL20_SHFT 16UL 461 462 REG32 TsRec_Tail2_Pcr1; // 0xbf802a18 0x06 463 #define TSP_HW_PVR_BUF_TAIL21_MASK 0x000007FFUL 464 #define TSP_HW_PVR_BUF_TAIL21_SHFT 0UL // PCR64 L16 465 #define TSP_PCR64_L16_MASK 0xFFFF0000UL 466 #define TSP_PCR64_L16_SHFT 16UL 467 468 REG32 Pcr1; // 0xbf802a20 0x08 469 #define TSP_PCR64_MID32_MASK 0xFFFFFFFFUL // PCR64 Middle 64 470 #define TSP_PCR64_MID32_SHFT 0UL 471 472 REG32 Pcr64_H; // 0xbf802a28 0x0a 473 #define TSP_PCR64_H16_MASK 0x0000FFFFUL 474 #define TSP_PCR64_H16_SHFT 0UL 475 #define TSP_MOBF_FILE_INDEX_MASK 0x001F0000UL // MOBF file index 476 #define TSP_MOBF_FILE_INDEX_SHIFT 16UL 477 478 REG16 _xbf202a30; // 0xbf802a30 0x0c 479 480 REG16 SW_Mail_Box0; // 0xbf802a34 0x0d 481 482 REG32 PVR2_Config; // 0xbf802a38 0x0e 483 #define TSP_PVR2_LPCR1_WLD 0x00000001UL 484 #define TSP_PVR2_LPCR1_RLD 0x00000002UL 485 #define TSP_PVR2_STR2MIU_DSWAP 0x00000004UL 486 #define TSP_PVR2_STR2MIU_EN 0x00000008UL 487 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010UL 488 #define TSP_PVR2_STR2MIU_BT_ORDER 0x00000020UL 489 #define TSP_PVR2_STR2MIU_PAUSE 0x00000040UL 490 #define TSP_PVR2_REG_PINGPONG_EN 0x00000080UL 491 #define TSP_PVR2_PVR_ALIGN_EN 0x00000100UL 492 #define TSP_PVR2_DMA_FLUSH_EN 0x00000200UL 493 #define TSP_PVR2_PKT192_EN 0x00000400UL 494 #define TSP_PVR2_BURST_LEN_MASK 0x00001800UL 495 #define TSP_PVR2_BURST_LEN_4 0x00000800UL 496 #define TSP_REC_DATA2_INV 0x00002000UL 497 #define TSP_V_BLOCK_DIS 0x00004000UL 498 #define TSP_V3D_BLOCK_DIS 0x00008000UL 499 #define TSP_AUD_BLOCK_DIS 0x00010000UL 500 #define TSP_AUDB_BLOCK_DIS 0x00020000UL 501 #define TSP_PVR1_BLOCK_DIS 0x00040000UL 502 #define TSP_PVR2_BLOCK_DIS 0x00080000UL 503 #define TSP_TSIF2_ENABLE 0x00100000UL 504 #define TSP_TSIF2_DATASWAP 0x00200000UL 505 #define TSP_TSIF2_SERL 0x00000000UL 506 #define TSP_TSIF2_PARL 0x00400000UL 507 #define TSP_TSIF2_EXTSYNC 0x00800000UL 508 #define TSP_TSIF2_BYPASS 0x01000000UL 509 #define TSP_TEI_SKIP_PKT2 0x02000000UL 510 #define TSP_AUDC_BLOCK_DIS 0x04000000UL 511 #define TSP_AUDD_BLOCK_DIS 0x08000000UL 512 #define TSP_DIS_LOCKED_PKT_CNT 0x10000000UL 513 #define TSP_CLR_LOCKED_PKT_CNT 0x20000000UL 514 #define TSP_CLR_AV_PKT_CNT 0x40000000UL 515 #define TSP_CLR_PVR_OVERFLOW 0x80000000UL 516 517 REG32 PVR2_LPCR1; // 0xbf802a40 0x10 518 519 #define TSP_STR2MI2_ADDR_MASK 0x07FFFFFFUL 520 REG32 Str2mi_head1_pvr2; // 0xbf802a48 0x12 521 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14 522 REG32 Str2mi_tail1_pvr2; // 0xbf802a58 0x16 523 REG32 Str2mi_head2_pvr2; // 0xbf802a60 0x18 524 REG32 Str2mi_mid2_pvr2; // 0xbf802a68 0x1a, PVR2 mid address & write point 525 REG32 Str2mi_tail2_pvr2; // 0xbf802a70 0x1c 526 REG32 SyncByte2_ChkSize; // 0xbf802a78 0x1e 527 #define TSP_SYNC_BYTE2_MASK 0x000000FFUL 528 #define TSP_PKT_SIZE2_MASK 0x0000FF00UL 529 #define TSP_PKT_SIZE2_SHIFT 8UL 530 #define TSP_PKT_CHK_SIZE2_MASK 0x00FF0000UL 531 #define TSP_PKT_CHK_SIZE2_SHIFT 16UL 532 REG32 Pkt_CacheW0; // 0xbf802a80 0x20 533 534 REG32 Pkt_CacheW1; // 0xbf802a88 0x22 535 536 REG32 Pkt_CacheW2; // 0xbf802a90 0x24 537 538 REG32 Pkt_CacheW3; // 0xbf802a98 0x26 539 540 REG32_L Pkt_CacheIdx; // 0xbf802aa0 0x28 541 542 REG32 Pkt_DMA; // 0xbf802aa8 0x2a 543 #define TSP_SEC_DMAFIL_NUM_MASK 0x000000FFUL 544 #define TSP_SEC_DMAFIL_NUM_SHIFT 0UL 545 #define TSP_SEC_DMASRC_OFFSET_MASK 0x0000FF00UL 546 #define TSP_SEC_DMASRC_OFFSET_SHIFT 8UL 547 #define TSP_SEC_DMASRC_OFFSET_MASK 0x0000FF00UL 548 #define TSP_SEC_DMADES_LEN_MASK 0x00FF0000UL 549 #define TSP_SEC_DMADES_LEN_SHIFT 16UL 550 551 REG32 Hw_Config0; // 0xbf802ab0 0x2c 552 #define TSP_HW_CFG0_DATA_PORT_EN 0x00000001UL 553 #define TSP_HW_CFG0_TSIFO_SERL 0x00000000UL 554 #define TSP_HW_CFG0_TSIF0_PARL 0x00000002UL 555 #define TSP_HW_CFG0_TSIF0_EXTSYNC 0x00000004UL 556 #define TSP_HW_CFG0_TSIF0_TS_BYPASS 0x00000008UL 557 #define TSP_HW_CFG0_TSIF0_VPID_BYPASS 0x00000010UL 558 #define TSP_HW_CFG0_TSIF0_APID_BYPASS 0x00000020UL 559 #define TSP_HW_CFG0_WB_DMA_RESET 0x00000040UL 560 #define TSP_HW_CFG0_TSIF0_APID_B_BYPASS 0x00000080UL 561 #define TSP_HW_CFG0_PACKET_BUF_SIZE_MASK 0x0000FF00UL 562 #define TSP_HW_CFG0_PACKET_BUF_SIZE_SHIFT 8UL 563 #define TSP_HW_CFG0_PACKET_PIDFLT0_SIZE_MASK 0x00FF0000UL 564 #define TSP_HW_CFG0_PACKET_PIDFLT0_SIZE_SHIFT 16UL 565 #define TSP_HW_CFG0_PACKET_CHK_SIZE_MASK 0xFF000000UL 566 #define TSP_HW_CFG0_PACKET_CHK_SIZE_SHFT 24UL 567 568 REG32 TSP_DBG_PORT; // 0xbf802ab8 0x2e 569 #define TSP_PCR64_3_SET 0x00000001UL 570 #define TSP_PCR64_3_EN 0x00000002UL 571 #define TSP_PCR64_3_LD 0x00000004UL 572 #define TSP_PCR64_4_SET 0x00000010UL 573 #define TSP_PCR64_4_EN 0x00000020UL 574 #define TSP_PCR64_4_LD 0x00000040UL 575 #define TSP_DNG_DATA_PORT_MASK 0x00FF0000UL 576 #define TSP_DNG_DATA_PORT_SHIFT 16UL 577 578 REG_Stc Pcr; // 0xbf802ac0 0x30 & 0x32 579 580 REG32 Pkt_Info; // 0xbf802ad0 0x34 581 #define TSP_APID_L_MASK 0x000000FFUL 582 #define TSP_APID_L_SHIFT 0UL 583 #define TSP_APID_H_MASK 0x00001F00UL 584 #define TSP_APID_H_SHIFT 8UL 585 #define TSP_PKT_PID_8_12_CP_MASK 0x001F0000UL 586 #define TSP_PKT_PID_8_12_CP_SHIFT 16UL 587 #define TSP_PKT_PRI_MASK 0x00200000UL 588 #define TSP_PKT_PRI_SHIFT 21UL 589 #define TSP_PKT_PLST_MASK 0x00400000UL 590 #define TSP_PKT_PLST_SHIFT 22UL 591 #define TSP_PKT_ERR 0x00800000UL 592 #define TSP_PKT_ERR_SHIFT 23UL 593 #define TSP_DMAW_NO_HIT_INT 0x0F000000UL 594 #define TSP_DMAW_NO_HIT_INT_SHIFT 24UL 595 596 REG32 Pkt_Info2; // 0xbf802ad8 0x36 597 #define TSP_PKT_INFO_CC_MASK 0x0000000FUL 598 #define TSP_PKT_INFO_CC_SHFT 0UL 599 #define TSP_PKT_INFO_ADPCNTL_MASK 0x00000030UL 600 #define TSP_PKT_INFO_ADPCNTL_SHFT 4UL 601 #define TSP_PKT_INFO_SCMB 0x000000C0UL 602 #define TSP_PKT_INFO_SCMB_SHFT 6UL 603 #define TSP_PKT_PID_0_7_CP_MASK 0x0000FF00UL 604 #define TSP_PKT_PID_0_7_CP_SHIFT 8UL 605 #define TSP_VFIFO3D_STATUS 0x000F0000UL 606 #define TSP_VFIFO3D_STATUS_SHFT 16UL 607 #define TSP_VFIFO_STATUS 0x00F00000UL 608 #define TSP_VFIFO_STATUS_SHFT 20UL 609 #define TSP_AFIFO_STATUS 0x0F000000UL 610 #define TSP_AFIFO_STATUS_SHFT 24UL 611 #define TSP_AFIFOB_STATUS 0xF0000000UL 612 #define TSP_AFIFOB_STATUS_SHFT 28UL 613 614 REG32 SwInt_Stat; // 0xbf802ae0 0x38 615 #define TSP_SWINT_INFO_SEC_MASK 0x000000FFUL 616 #define TSP_SWINT_INFO_SEC_SHFT 0UL 617 #define TSP_SWINT_INFO_ENG_MASK 0x0000FF00UL 618 #define TSP_SWINT_INFO_ENG_SHFT 8UL 619 #define TSP_SWINT_STATUS_CMD_MASK 0x7FFF0000UL 620 #define TSP_SWINT_STATUS_CMD_SHFT 16UL 621 #define TSP_SWINT_STATUS_SEC_RDY 0x0001UL 622 #define TSP_SWINT_STATUS_REQ_RDY 0x0002UL 623 #define TSP_SWINT_STATUS_BUF_OVFLOW 0x0006UL 624 #define TSP_SWINT_STATUS_SEC_CRCERR 0x0007UL 625 #define TSP_SWINT_STATUS_SEC_ERROR 0x0008UL 626 #define TSP_SWINT_STATUS_SYNC_LOST 0x0010UL 627 #define TSP_SWINT_STATUS_PKT_OVRUN 0x0020UL 628 #define TSP_SWINT_STATUS_DEBUG 0x0030UL 629 #define TSP_SWINT_CMD_DMA_PAUSE 0x0100UL 630 #define TSP_SWINT_CMD_DMA_RESUME 0x0200UL 631 #define TSP_SWINT_STATUS_SEC_GROUP 0x000FUL 632 #define TSP_SWINT_STATUS_GROUP 0x00FFUL 633 #define TSP_SWINT_CMD_GROUP 0x7F00UL 634 #define TSP_SWINT_CMD_STC_UPD 0x0400UL 635 #define TSP_SWINT_CTRL_FIRE 0x80000000UL 636 637 REG32 TsDma_Addr; // 0xbf802ae8 0x3a 638 639 REG32 TsDma_Size; // 0xbf802af0 0x3c 640 641 REG32 TsDma_Ctrl_CmdQ; // 0xbf802af8 0x3e 642 643 #define TSP_TSDMA_CTRL_VPES0 0x00000004UL 644 #define TSP_TSDMA_CTRL_APES0 0x00000008UL 645 #define TSP_TSDMA_CTRL_A2PES0 0x00000010UL 646 #define TSP_TSDMA_CTRL_V3DPES0 0x00000020UL 647 #define TSP_TSDMA_CTRL_A3PES0 0x00000040UL 648 #define TSP_TSDMA_CTRL_A4PES0 0x00000080UL 649 650 #define TSP_TSDMA_CTRL_START 0x00000001UL 651 #define TSP_TSDMA_CTRL_DONE 0x00000002UL 652 #define TSP_TSDMA_STAT_ABORT 0x00000080UL 653 #define TSP_CMDQ_CNT_MASK 0x001F0000UL 654 #define TSP_CMDQ_CNT_SHFT 16UL 655 #define TSP_CMDQ_FULL 0x00400000UL 656 #define TSP_CMDQ_EMPTY 0x00800000UL 657 #define TSP_CMDQ_SIZE 16UL 658 #define TSP_CMDQ_WR_LEVEL_MASK 0x03000000UL 659 #define TSP_CMDQ_WR_LEVEL_SHFT 24UL 660 661 REG32 MCU_Cmd; // 0xbf802b00 0x40 662 #define TSP_MCU_CMD_MASK 0xFF000000UL 663 #define TSP_MCU_CMD_NULL 0x00000000UL 664 #define TSP_MCU_CMD_ALIVE 0x01000000UL 665 #define TSP_MCU_CMD_NMATCH 0x02000000UL 666 #define TSP_MCU_CMD_NMATCH_FLT_MASK 0x000000FFUL 667 #define TSP_MCU_CMD_NMATCH_FLT_SHFT 0x00000000UL 668 #define TSP_MCU_CMD_PCR_GET 0x03000000UL 669 #define TSP_MCU_CMD_VER_RESET 0x04000000UL 670 #define TSP_MCU_CMD_VER_RESET_FLT_MASK 0x000000FFUL 671 #define TSP_MCU_CMD_VER_RESET_FLT_SHFT 0x00000000UL 672 #define TSP_MCU_CMD_MEM_HIGH_ADDR 0x05000000UL 673 #define TSP_MCU_CMD_MEM_LOW_ADDR 0x06000000UL 674 #define TSP_MCU_CMD_MEM_ADDR_SHFT 0x00000000UL 675 #define TSP_MCU_CMD_MEM_ADDR_MASK 0x0000FFFFUL 676 #define TSP_MCU_CMD_VERSION_GET 0x07000000UL 677 #define TSP_MCU_CMD_DBG_MEM 0x08000000UL 678 #define TSP_MCU_CMD_DBG_WORD 0x09000000UL 679 #define TSP_MCU_CMD_HWPCR_REG_SET 0x0A000000UL 680 #define TSP_MCU_CMD_SCMSTS_GET 0x0B000000UL 681 #define TSP_MCU_CMD_CTRL_STC_UPDATE 0x0C000000UL 682 #define TSP_MCU_CMD_CTRL_STC1_UPDATE 0x0D000000UL 683 #define TSP_MCU_CMD_CTRL_STC_UPDATE_OPTION_MASK 0x00FF0000UL 684 #define TSP_MCU_CMD_CTRL_STC_UPDATE_ONCE 0x00010000UL 685 #define TSP_MCU_CMD_TEI_COUNT_GET 0x0E000000UL 686 #define TSP_MCU_CMD_TEI_COUNT_SRC_MASK 0x0000FFFFUL 687 #define TSP_MCU_CMD_TEI_COUNT_SRC_LIVE 0x00000000UL 688 #define TSP_MCU_CMD_TEI_COUNT_SRC_FILE 0x00000001UL 689 #define TSP_MCU_CMD_TEI_COUNT_OPTION_MASK 0x00FF0000UL 690 #define TSP_MCU_CMD_TEI_COUNT_OPTION_RESET 0x00800000UL 691 #define TSP_MCU_CMD_DISCONT_COUNT_GET 0x0F000000UL 692 #define TSP_MCU_CMD_DISCONT_COUNT_FLT_MASK 0x0000FFFFUL 693 #define TSP_MCU_CMD_DISCONT_COUNT_OPTION_MASK 0x00FF0000UL 694 #define TSP_MCU_CMD_DISCONT_COUNT_OPTION_RESET 0x00800000UL 695 #define TSP_MCU_CMD_SET_STC_OFFSET 0x10000000UL 696 #define TSP_MCU_CMD_SET_STC_OFFSET_OPTION_MASK 0x00FF0000UL 697 #define TSP_MCU_CMD_SET_STC_OFFSET_OPTION_SHIFT 16UL 698 #define TSP_MCU_CMD_SEL_STC_ENG 0x20000000UL 699 #define TSP_MCU_SEL_STC_ENG_ID_MASK 0x000000FFUL 700 #define TSP_MCU_SEL_STC_ENG_ID_SHIFT 0UL 701 #define TSP_MCU_CMD_SEL_STC_ENG_FLTSRC_MASK 0x0000FF00UL 702 #define TSP_MCU_CMD_SEL_STC_ENG_FLTSRC_SHIFT 8UL 703 704 REG32 Hw_Config2; // 0xbf802b08 0x42 705 #define TSP_HW_CFG2_PACKET_CHK_SIZE1_MASK 0x000000FFUL 706 #define TSP_HW_CFG2_PACKET_CHK_SIZE1_SHFT 0UL 707 #define TSP_HW_CFG2_PACKET_SYNCBYTE1_MASK 0x0000FF00UL 708 #define TSP_HW_CFG2_PACKET_SYNCBYTE1_SHFT 8UL 709 #define TSP_HW_CFG2_PACKET_SIZE1_MASK 0x00FF0000UL 710 #define TSP_HW_CFG2_PACKET_SIZE1_SHFT 16UL 711 #define TSP_HW_CFG2_TSIF1_SERL 0x00000000UL 712 #define TSP_HW_CFG2_TSIF1_PARL 0x01000000UL 713 #define TSP_HW_CFG2_TSIF1_EXTSYNC 0x02000000UL 714 #define TSP_HW_CFG2_PIDFLT1_SOURCE_TSIF_MMFI0 0x20000000UL // Switch source of PIDFLT1 to MMFI0 715 #define TSP_HW_CFG2_PIDFLT2_SOURCE_TSIF_MMFI1 0x40000000UL // Switch source of PIDFLT2 to MMFI1 716 717 REG32 Hw_Config4; // 0xbf802b10 0x44 718 #define TSP_HW_CFG4_PVR_ENABLE 0x00000002UL 719 #define TSP_HW_CFG4_PVR_ENDIAN_BIG 0x00000004UL // 1: record TS to MIU with big endian, 0: record TS to MIU with little endian 720 #define TSP_HW_CFG4_TSIF1_ENABLE 0x00000008UL // 1: enable ts interface 1 and vice versa 721 #define TSP_HW_CFG4_PVR_FLUSH 0x00000010UL // 1: str2mi_wadr <- str2mi_miu_head 722 #define TSP_HW_CFG4_PVRBUF_BYTEORDER_BIG 0x00000020UL // Byte order of 8-byte recoding buffer to MIU. 723 #define TSP_HW_CFG4_PVR_PAUSE 0x00000040UL 724 #define TSP_HW_CFG4_MEMTSDATA_ENDIAN_BIG 0x00000080UL // 32-bit data byte order read from 8x64 FIFO when playing file. 725 #define TSP_HW_CFG4_TSIF0_ENABLE 0x00000100UL // 1: enable ts interface 0 and vice versa 726 #define TSP_VALID_FALLING_DETECT 0x00000200UL // Reset bit count when data valid signal of TS interface is low. 727 #define TSP_SYNC_RISING_DETECT 0x00000400UL // Reset bit count on the rising sync signal of TS interface. 728 #define TSP_HW_CFG4_TS_DATA0_SWAP 0x00000800UL // Set 1 to swap the bit order of TS0 DATA bus 729 #define TSP_HW_CFG4_TS_DATA1_SWAP 0x00001000UL // Set 1 to swap the bit order of TS1 DATA bus 730 #define TSP_HW_TSP2OUTAEON_INT_EN 0x00004000UL // Set 1 to force interrupt to outside AEON 731 #define TSP_HW_HK_INT_FORCE 0x00008000UL // Set 1 to force interrupt to HK_MCU 732 #define TSP_HW_CFG4_BYTE_ADDR_DMA 0x000F0000UL // prevent from byte enable bug, bit1~3 must enable togather 733 #define TSP_HW_CFG4_ALT_TS_SIZE 0x00010000UL // enable TS packets in 204 mode 734 #define TSP_HW_DMA_MODE_MASK 0x00300000UL // Section filter DMA mode, 2'b00: Single.2'b01: Burst 2 bytes.2'b10: Burst 4 bytes.2'b11: Burst 8 bytes. 735 #define TSP_HW_DMA_MODE_SHIFT 20UL 736 #define TSP_HW_CFG4_WSTAT_CH_EN 0x00400000UL 737 #define TSP_HW_CFG4_PS_VID_EN 0x00800000UL // program stream video enable 738 #define TSP_HW_CFG4_PS_AUD_EN 0x01000000UL // program stream audio enable 739 #define TSP_HW_CFG4_PS_AUD2_EN 0x02000000UL // program stream audioB enable 740 #define TSP_HW_CFG4_APES_ERR_RM_EN 0x04000000UL // Set 1 to enable removing APES error packet 741 #define TSP_HW_CFG4_VPES_ERR_RM_EN 0x08000000UL // Set 1 to enable removing VPES error packet 742 #define TSP_HW_CFG4_SEC_ERR_RM_EN 0x10000000UL // Set 1 to enable removing section error packet 743 #define TSP_HW_CFG4_VID_ERR 0x20000000UL // Set 1 to mask the error packet interrupt 744 #define TSP_HW_CFG4_AUD_ERR 0x40000000UL // Set 1 to mask the error packet interrupt 745 #define TSP_HW_CFG4_ISYNC_PATCH_EN 0x80000000UL // Set 1 to enable the patch of internal sync in "tsif" 746 747 REG32 NOEA_PC; // 0xbf802b18 0x46 748 749 REG32 Idr_Ctrl_Addr0; // 0xbf802b20 0x48 750 #define TSP_IDR_START 0x00000001UL 751 #define TSP_IDR_READ 0x00000000UL 752 #define TSP_IDR_WRITE 0x00000002UL 753 #define TSP_IDR_WR_ENDIAN_BIG 0x00000004UL 754 #define TSP_IDR_WR_ADDR_AUTO_INC 0x00000008UL // Set 1 to enable address auto-increment after finishing read/write 755 #define TSP_IDR_WDAT0_TRIG_EN 0x00000010UL // WDAT0_TRIG_EN 756 #define TSP_IDR_MCUWAIT 0x00000020UL 757 #define TSP_IDR_SOFT_RST 0x00000080UL // Set 1 to soft-reset the IND32 module 758 #define TSP_IDR_AUTO_INC_VAL_MASK 0x00000F00UL 759 #define TSP_IDR_AUTO_INC_VAL_SHIFT 8UL 760 #define TSP_IDR_ADDR_MASK0 0xFFFF0000UL 761 #define TSP_IDR_ADDR_SHFT0 16UL 762 763 REG32 Idr_Addr1_Write0; // 0xbf802b28 0x4a 764 #define TSP_IDR_ADDR_MASK1 0x0000FFFFUL 765 #define TSP_IDR_ADDR_SHFT1 0UL 766 #define TSP_IDR_WRITE_MASK0 0xFFFF0000UL 767 #define TSP_IDR_WRITE_SHFT0 16UL 768 769 REG32 Idr_Write1_Read0; // 0xbf802b30 0x4c 770 #define TSP_IDR_WRITE_MASK1 0x0000FFFFUL 771 #define TSP_IDR_WRITE_SHFT1 0UL 772 #define TSP_IDR_READ_MASK0 0xFFFF0000UL 773 #define TSP_IDR_READ_SHFT0 16UL 774 775 REG32 Idr_Read1; // 0xbf802b38 0x4e 776 #define TSP_IDR_READ_MASK1 0x0000FFFFUL 777 #define TSP_IDR_READ_SHFT1 0UL 778 #define TSP_V3D_FIFO_DISCON 0x00100000UL 779 #define TSP_V3D_FIFO_OVERFLOW 0x00200000UL 780 #define TSP_VD_FIFO_DISCON 0x02000000UL 781 #define TSP_VD_FIFO_OVERFLOW 0x08000000UL 782 #define TSP_AUB_FIFO_OVERFLOW 0x10000000UL 783 #define TSP_AU_FIFO_OVERFLOW 0x20000000UL 784 #define TSP_AUD_FIFO_OVERFLOW 0x40000000UL 785 #define TSP_AUC_FIFO_OVERFLOW 0x80000000UL 786 787 REG32 TsRec_Head; // 0xbf802b40 0x50 788 REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid address & write point 789 REG32 TsRec_Tail; // 0xbf802b50 0x54 790 791 REG16 SW_Mail_Box1; // 0xbf802b58 0x56 792 REG16 SW_Mail_Box2; // 0xbf802b5C 0x57 793 REG32 _xbf802b60; // 0xbf802b60 ~ 0xbf802b64 0x58~0x59 794 795 REG32 reg15b4; // 0xbf802b68 0x5a 796 #define TSP_SEC_DMAW_PROTECT_EN 0x00000001UL 797 #define TSP_PVR1_DAMW_PROTECT_EN 0x00000002UL 798 #define TSP_PVR2_DAMW_PROTECT_EN 0x00000004UL 799 #define TSP_PVR_PID_BYPASS 0x00000008UL // Set 1 to bypass PID in record 800 #define TSP_PVR_PID_BYPASS2 0x00000010UL // Set 1 to bypass PID in record2 801 #define TSP_BD_AUD_EN 0x00000020UL // Set 1 to enable the BD audio stream recognization ( core /extend audio stream) to Audio A/B 802 #define TSP_BD_AUD_EN2 0x00000040UL // Set 1 to enable the BD audio stream recognization ( core /extend audio stream) to Audio C/D 803 #define TSP_AVFIFO_RD_EN 0x00000080UL // 0: AFIFO and VFIFO read are connected to MVD and MAD, 1: AFIFO and VFIFO read are controlled by registers (0x15B5[2:0]) 804 #define TSP_AVFIFO_RD 0x00000100UL // If AVFIFO_RD_EN is 1, set to 1, then set to 0 would issue a read strobe to AFIFO or VFIFO 805 #define TSP_AVFIFO_SEL_VIDEO 0x00000000UL 806 #define TSP_AVFIFO_SEL_AUDIO 0x00000200UL 807 #define TSP_AVFIFO_SEL_AUDIOB 0x00000400UL 808 #define TSP_AVFIFO_SEL_V3D 0x00000600UL 809 #define TSP_PVR_INVERT 0x00001000UL // Set 1 to enable data payload invert for PVR record 810 #define TSP_PLY_FILE_INV_EN 0x00002000UL // Set 1 to enable data payload invert in pidflt0 file path 811 #define TSP_PLY_TS_INV_EN 0x00004000UL // Set 1 to enable data payload invert in pidflt0 TS path 812 #define TSP_FILEIN_BYTETIMER_ENABLE 0x00008000UL // Set 1 to enable byte timer in ts_if0 TS path 813 #define TSP_PVR1_PINGPONG 0x00010000UL // Set 1 to enable MIU addresses with pinpon mode 814 #define TSP_TEI_SKIPE_PKT_PID0 0x00040000UL // Set 1 to skip error packets in pidflt0 TS path 815 #define TSP_TEI_SKIPE_PKT_FILE 0x00080000UL // Set 1 to skip error packets in pidflt0 file path 816 #define TSP_TEI_SKIPE_PKT_PID1 0x00100000UL // Set 1 to skip error packets in pidflt1 TS path 817 #define TSP_DUP_PKT_SKIP 0x00400000UL 818 #define TSP_64bit_PCR2_ld 0x00800000UL // Set 1 to load CNT_64B_2 (the second STC) 819 #define TSP_cnt_33b_ld 0x01000000UL // Set 1 to load cnt_33b 820 #define TSP_FORCE_SYNCBYTE 0x02000000UL // Set 1 to force sync byte (8'h47) in ts_if0 and ts_if1 path. 821 #define TSP_SERIAL_EXT_SYNC_LT 0x04000000UL // Set 1 to detect serial-in sync without 8-cycle mode 822 #define TSP_BURST_LEN_MASK 0x18000000UL // 00,01: burst length = 4; 10,11: burst length = 1 823 #define TSP_BURST_LEN_4 0x08000000UL 824 #define TSP_BURST_LEN_SHIFT 27UL 825 #define TSP_MATCH_PID_SRC_MASK 0x60000000UL // Select the source of pid filter number with hit pid and match pid number with scramble information, 00 : from pkt_demux0, 01 : from pkt_demux_file, 10 : from pkt_demux1, 11 : from pkt_demux2 826 #define TSP_MATCH_PID_SRC_SHIFT 29UL 827 #define TSP_MATCH_PID_SRC_PKTDMX0 0UL 828 #define TSP_MATCH_PID_SRC_PKTDMXFL 1UL 829 #define TSP_MATCH_PID_SRC_PKTDMX1 2UL 830 #define TSP_MATCH_PID_SRC_PKTDMX2 3UL 831 #define TSP_MATCH_PID_LD 0x80000000UL 832 833 REG32 TSP_MATCH_PID_NUM; // 0xbf802b70 0x5c 834 835 REG32 TSP_IWB_WAIT; // 0xbf802b78 0x5e // Wait count settings for IWB when TSP CPU i-cache is enabled. 836 837 REG32 Cpu_Base; // 0xbf802b80 0x60 838 #define TSP_CPU_BASE_ADDR_MASK 0x01FFFFFFUL 839 840 REG32 Qmem_Ibase; // 0xbf802b88 0x62 841 842 REG32 Qmem_Imask; // 0xbf802b90 0x64 843 844 REG32 Qmem_Dbase; // 0xbf802b98 0x66 845 846 REG32 Qmem_Dmask; // 0xbf802ba0 0x68 847 848 REG32 TSP_Debug; // 0xbf802ba8 0x6a 849 #define TSP_DEBUG_MASK 0x00FFFFFFUL 850 851 REG32 _xbf802bb0; // 0xbf802bb0 0x6c 852 853 REG32 TsFileIn_RPtr; // 0xbf802bb8 0x6e 854 855 REG32 TsFileIn_Timer; // 0xbf802bc0 0x70 856 #define TSP_FILE_TIMER_MASK 0x00FFFFFFUL 857 REG32 TsFileIn_Head; // 0xbf802bc8 0x72 858 #define TSP_FILE_ADDR_MASK 0x07FFFFFFUL 859 REG32 TsFileIn_Mid; // 0xbf802bd0 0x74 860 861 REG32 TsFileIn_Tail; // 0xbf802bd8 0x76 862 863 REG32 Dnld_Ctrl; // 0xbf802be0 0x78 864 #define TSP_DNLD_ADDR_MASK 0x0000FFFFUL 865 #define TSP_DNLD_ADDR_SHFT 0UL 866 #define TSP_DNLD_ADDR_ALI_SHIFT 4UL // Bit [11:4] of DMA_RADDR[19:0] 867 #define TSP_DNLD_NUM_MASK 0xFFFF0000UL 868 #define TSP_DNLD_NUM_SHFT 16UL 869 870 REG32 TSP_Ctrl; // 0xbf802be8 0x7a 871 #define TSP_CTRL_CPU_EN 0x00000001UL 872 #define TSP_CTRL_SW_RST 0x00000002UL 873 #define TSP_CTRL_DNLD_START 0x00000004UL 874 #define TSP_CTRL_DNLD_DONE 0x00000008UL // See 0x78 for related information 875 #define TSP_CTRL_TSFILE_EN 0x00000010UL 876 #define TSP_CTRL_R_PRIO 0x00000020UL 877 #define TSP_CTRL_W_PRIO 0x00000040UL 878 #define TSP_CTRL_ICACHE_EN 0x00000100UL 879 #define TSP_CTRL_CPU2MI_R_PRIO 0x00000400UL 880 #define TSP_CTRL_CPU2MI_W_PRIO 0x00000800UL 881 #define TSP_CTRL_I_EL 0x00000000UL 882 #define TSP_CTRL_I_BL 0x00001000UL 883 #define TSP_CTRL_D_EL 0x00000000UL 884 #define TSP_CTRL_D_BL 0x00002000UL 885 #define TSP_CTRL_NOEA_QMEM_ACK_DIS 0x00004000UL 886 #define TSP_CTRL_MEM_TS_WORDER 0x00008000UL 887 #define TSP_SYNC_BYTE_MASK 0x00FF0000UL 888 #define TSP_SYNC_BYTE_SHIFT 16UL 889 890 REG32 PKT_CNT; // 0xbf802bf0 0x7c 891 #define TSP_PKT_CNT_MASK 0x000000FFUL 892 #define TSP_DBG_SEL_MASK 0xFFFF0000UL 893 #define TSP_DBG_SEL_SHIFT 16UL 894 895 REG16 HwInt_Stat; // 0xbf802bf8 0x7e 896 #define TSP_HWINT_STATUS_MASK 0xFF00UL // Tsp2hk_int enable bits. 897 #define TSP_HWINT_TSP_PVR_TAIL0_STATUS 0x0100UL 898 #define TSP_HWINT_TSP_PVR_MID0_STATUS 0x0200UL 899 #define TSP_HWINT_TSP_HK_INT_FORCE_STATUS 0x0400UL 900 #define TSP_HWINT_TSP_FILEIN_MID_INT_STATUS 0x0800UL 901 #define TSP_HWINT_TSP_FILEIN_TAIL_INT_STATUS 0x1000UL 902 #define TSP_HWINT_TSP_SW_INT_STATUS 0x2000UL 903 #define TSP_HWINT_TSP_DMA_READ_DONE 0x4000UL 904 #define TSP_HWINT_TSP_AV_PKT_ERR 0x8000UL 905 906 #define TSP_HWINT_HW_PVR1_MASK (TSP_HWINT_TSP_PVR_TAIL0_STATUS | TSP_HWINT_TSP_PVR_MID0_STATUS) 907 #define TSP_HWINT_ALL (TSP_HWINT_HW_PVR1_MASK | TSP_HWINT_TSP_SW_INT_STATUS) 908 909 // 0x7f: TSP_CTRL1: hidden in HwInt_Stat 910 REG16 TSP_Ctrl1; // 0xbf802bfc 0x7f 911 #define TSP_CTRL1_FILEIN_TIMER_ENABLE 0x0001UL 912 #define TSP_CTRL1_TSP_FILE_NON_STOP 0x0002UL //Set 1 to enable TSP file data read without timer check 913 #define TSP_CTRL1_FILEIN_PAUSE 0x0004UL 914 #define TSP_CTRL1_STANDBY 0x0080UL 915 #define TSP_CTRL1_INT2NOEA 0x0100UL 916 #define TSP_CTRL1_INT2NOEA_FORCE 0x0200UL 917 #define TSP_CTRL1_FORCE_XIU_WRDY 0x0400UL 918 #define TSP_CTRL1_CMDQ_RESET 0x0800UL 919 #define TSP_CTRL1_DLEND_EN 0x1000UL // Set 1 to enable little-endian mode in TSP CPU 920 #define TSP_CTRL1_PVR_CMD_QUEUE_ENABLE 0x2000UL 921 #define TSP_CTRL1_DMA_RST 0x8000UL 922 923 //---------------------------------------------- 924 // 0xBF802C00 MIPS direct access 925 //---------------------------------------------- 926 REG32 MCU_Data0; // 0xbf802c00 0x00 927 #define TSP_MCU_DATA_ALIVE TSP_MCU_CMD_ALIVE 928 929 REG32 PVR1_LPcr1; // 0xbf802c08 0x02 930 931 REG32 LPcr2; // 0xbf802c10 0x04 932 933 REG32 reg160C; // 0xbf802c18 0x06 934 #define TSP_PVR1_LPCR1_WLD 0x00000001UL // Set 1 to load LPCR1 value 935 #define TSP_PVR1_LPCR1_RLD 0x00000002UL // Set 1 to read LPCR1 value (Default: 1) 936 #define TSP_LPCR2_WLD 0x00000004UL // Set 1 to load LPCR2 value 937 #define TSP_LPCR2_RLD 0x00000008UL // Set 1 to read LPCR2 value (Default: 1) 938 #define TSP_RECORD192_EN 0x00000010UL // 160C bit(5)enable TS packets with 192 bytes on record mode 939 #define TSP_FILEIN192_EN 0x00000020UL // 160C bit(5)enable TS packets with 192 bytes on file-in mode 940 #define TSP_RVU_TIMESTAMP_EN 0x00000040UL 941 #define TSP_ORZ_DMAW_PROT_EN 0x00000080UL // 160C bit(7) open RISC DMA write protection 942 #define TSP_CLR_PIDFLT_BYTE_CNT 0x00000100UL // Clear pidflt0_file byte counter 943 #define TSP_DOUBLE_BUF_DESC 0x00004000UL // 160d bit(6) remove buffer limitation, Force pinpong buffer to flush 944 #define TSP_TIMESTAMP_RESET 0x00008000UL // 160d bit(7) reset timestamp, reset all file in path 945 #define TSP_VQTX0_BLOCK_DIS 0x00010000UL 946 #define TSP_VQTX1_BLOCK_DIS 0x00020000UL 947 #define TSP_VQTX2_BLOCK_DIS 0x00040000UL 948 #define TSP_VQTX3_BLOCK_DIS 0x00080000UL 949 #define TSP_DIS_MIU_RQ 0x00100000UL // Disable miu R/W request for reset TSP usage 950 #define TSP_RM_DMA_GLITCH 0x00800000UL // Fix sec_dma overflow glitch 951 #define TSP_RESET_VFIFO 0x01000000UL // Reset VFIFO -- ECO Done 952 #define TSP_RESET_AFIFO 0x02000000UL // Reset AFIFO -- ECO Done 953 #define TSP_RESET_GDMA 0x04000000UL // Set 1 to reset GDMA bridge 954 #define TSP_CLR_ALL_FLT_MATCH 0x08000000UL // Set 1 to clean all flt_match in a packet 955 #define TSP_RESET_AFIFO2 0x10000000UL 956 #define TSP_RESET_VFIFO3D 0x20000000UL 957 #define TSP_PVR_WPRI_HIGH 0x20000000UL 958 #define TSP_OPT_ORACESS_TIMING 0x80000000UL 959 960 REG32 PktChkSizeFilein; // 0xbf802c20 0x08 961 #define TSP_PKT_SIZE_MASK 0x000000ffUL 962 #define TSP_PKT192_BLK_DIS_FIN 0x00000100UL // Set 1 to disable file-in timestamp block scheme 963 #define TSP_AV_CLR 0x00000200UL // Clear AV FIFO overflow flag and in/out counter 964 #define TSP_HW_STANDBY_MODE 0x00000400UL // Set 1 to disable all SRAM in TSP for low power mode automatically 965 #define TSP_CNT_34B_DEFF_EN 0x00020000UL // Switch STC DIFF Mode (Output STC+DIFF to MVD and MAD) 966 #define TSP_SYSTIME_MODE_STC64 0x00080000UL // Switch normal STC or STC diff 967 #define TSP_SEC_DMA_BURST_EN 0x00800000UL // ECO bit for section DMA burst mode 968 #define TSP_REMOVE_DUP_VIDEO_PKT 0x02000000UL // Set 1 to remove duplicate video packet 969 #define TSP_REMOVE_DUP_VIDEO3D_PKT 0x04000000UL // Set 1 to remove duplicate video 3D packet 970 #define TSP_REMOVE_DUP_AUDIO_PKT 0x08000000UL // Set 1 to remove duplicate audio packet 971 #define TSP_REMOVE_DUP_AUDIOB_PKT 0x10000000UL // Set 1 to remove duplicate audio description packet 972 #define TSP_REMOVE_DUP_AUDIOC_PKT 0x20000000UL // Set 1 to remove duplicate third audio fifo packet 973 #define TSP_REMOVE_DUP_AUDIOD_PKT 0x40000000UL // Set 1 to remove duplicate fourth audio fifo packet 974 975 #define TSP_REMOVE_DUP_AV_PKT (TSP_REMOVE_DUP_VIDEO_PKT | \ 976 TSP_REMOVE_DUP_VIDEO3D_PKT | \ 977 TSP_REMOVE_DUP_AUDIO_PKT | \ 978 TSP_REMOVE_DUP_AUDIOB_PKT | \ 979 TSP_REMOVE_DUP_AUDIOC_PKT | \ 980 TSP_REMOVE_DUP_AUDIOD_PKT) 981 982 REG32 Dnld_Ctrl2; // 0xbf802c28 0x0a 983 #define TSP_DMA_RADDR_MSB_MASK 0x000000FFUL 984 #define TSP_DMA_RADDR_MSB_SHIFT 0UL 985 //#define TSP_CMQ_WORD_EN 0x00400000UL // Set 1 to access CMDQ related registers in word. 986 //#define TSP_RESET_PVR_MOBF 0x04000000UL 987 //#define TSP_RESET_FILEIN_MOBF 0x08000000UL 988 #define TSP_TSIF0_VPID_3D_BYPASS 0x08000000UL // bypass TS for matched video 3D pid 989 #define TSP_VPID_3D_ERR_RM_EN 0x10000000UL // enable removing v3d err pkt 990 #define TSP_PS_VID3D_EN 0x40000000UL 991 992 REG32 TsPidScmbStatTsin; // 0xbf802c30 0x0c 993 994 REG32 _xbf802c38; // 0xbf802c38 0x0e 995 996 REG32 PCR64_2_L; // 0xbf802c40 0x10 997 998 REG32 PCR64_2_H; // 0xbf802c48 0x12 999 1000 #define TSP_DMAW_BND_MASK 0xFFFFFFFFFUL 1001 REG32 DMAW_LBND0; // 0xbf802c50 0x14 1002 1003 REG32 DMAW_UBND0; // 0xbf802c58 0x16 1004 1005 REG32 DMAW_LBND1; // 0xbf802c60 0x18 1006 1007 REG32 DMAW_UBND1; // 0xbf802c68 0x1A 1008 1009 REG32 DMAW_ERR_WADDR_SRC_SEL; // 0xbf802c70 0x1C 1010 #define TSP_CLR_NO_HIT_INT 0x00000001UL // set 1 clear all dma write function not hit interrupt 1011 #define DMAW_ERR_WADDR_SRC_SEL_MASK 0x0000001EUL 1012 #define DMAW_ERR_WADDR_SRC_SEL_SHIFT 1UL 1013 #define TSP_PVR1_DWMA_WADDR_ERR 0x0UL 1014 #define TSP_SEC_DWMA_WADDR_ERR 0x1UL 1015 #define TSP_PVR_CB_DWMA_WADDR_ERR 0x2UL 1016 #define TSP_VQTX0_DWMA_WADDR_ERR 0x3UL 1017 #define TSP_VQTX1_DWMA_WADDR_ERR 0x4UL 1018 #define TSP_ORZ_DWMA_WADDR_ERR 0x5UL 1019 #define TSP_VQTX2_DWMA_WADDR_ERR 0x6UL 1020 #define TSP_VQTX3_DWMA_WADDR_ERR 0x7UL 1021 #define TSP_PVR2_DWMA_WADDR_ERR 0x8UL 1022 #define TSP_CLR_SEC_DMAW_OVERFLOW 0x00000040UL 1023 #define TSP_APES_B_ERR_RM_EN 0x00000080UL 1024 #define TSP_APES_C_ERR_RM_EN 0x00000100UL 1025 #define TSP_APES_D_ERR_RM_EN 0x00000200UL 1026 #define TSP_BLK_AF_SCRMB_BIT 0x00000400UL 1027 #define TSP_PKTSIZE_FI_MASK 0x00FF0000UL 1028 #define TSP_PKTSIZE_FI_SHIFT 16 1029 1030 REG32 reg163C; // 0xbf802c78 0x1e 1031 #define TSP_AUDC_SRC_MASK 0x00000007UL 1032 #define TSP_AUDC_SRC_SHIFT 0UL 1033 #define TSP_AUDD_SRC_MASK 0x00000038UL 1034 #define TSP_AUDD_SRC_SHIFT 3UL 1035 #define TSP_CLR_SRC_MASK 0x00070000UL 1036 #define TSP_CLR_SRC_SHIFT 16UL 1037 #define TSP_DISCONTI_VD_CLR 0x00080000UL //Set 1 to clear video discontinuity count 1038 #define TSP_DISCONTI_V3D_CLR 0x00100000UL //Set 1 to clear v3D discontinuity count 1039 #define TSP_DISCONTI_AUD_CLR 0x00200000UL //Set 1 to clear audio discontinuity count 1040 #define TSP_DISCONTI_AUDB_CLR 0x00400000UL //Set 1 to clear videoB discontinuity count 1041 #define TSP_DISCONTI_AUDC_CLR 0x00800000UL //Set 1 to clear videoC discontinuity count 1042 #define TSP_DISCONTI_AUDD_CLR 0x01000000UL //Set 1 to clear videoD discontinuity count 1043 #define TSL_CLR_SRAM_COLLISION 0x02000000UL 1044 #define TSP_TS_OUT_EN 0x04000000UL //set 1 to enable ts_out 1045 1046 #define TSP_ALL_VALID_EN 0x08000000UL 1047 #define TSP_PKT130_PUSI_EN 0x10000000UL 1048 #define TSP_PKT130_TEI_EN 0x20000000UL 1049 #define TSP_PKT130_ERR_CLR 0x40000000UL 1050 #define TSP_PKT130_EN 0x80000000UL // file in only 1051 1052 REG32 VQ0_BASE; // 0xbf802c80 0x20 1053 REG32 VQ0_CTRL; // 0xbf802c88 0x22 1054 #define TSP_VQ0_SIZE_208PK_MASK 0x0000FFFFUL 1055 #define TSP_VQ0_SIZE_208PK_SHIFT 0UL 1056 #define TSP_VQ0_WR_THRESHOLD_MASK 0x000F0000UL 1057 #define TSP_VQ0_WR_THRESHOLD_SHIFT 16UL 1058 #define TSP_VQ0_PRIORTY_THRESHOLD_MASK 0x00F00000UL 1059 #define TSP_VQ0_PRIORTY_THRESHOL_SHIFT 20UL 1060 #define TSP_VQ0_FORCE_FIRE_CNT_1K_MASK 0x0F000000UL 1061 #define TSP_VQ0_FORCE_FIRE_CNT_1K_SHIFT 24UL 1062 #define TSP_VQ0_RESET 0x10000000UL 1063 #define TSP_VQ0_OVERFLOW_INT_EN 0x40000000UL // Enable the interrupt for overflow happened on Virtual Queue path 1064 #define TSP_VQ0_CLR_OVERFLOW_INT 0x80000000UL // Clear the interrupt and the overflow flag 1065 1066 REG32 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 1067 #define TSP_REQ_VQ_RX_THRESHOLD_MASKE 0x000E0000UL 1068 #define TSP_REQ_VQ_RX_THRESHOLD_SHIFT 17UL 1069 #define TSP_REQ_VQ_RX_THRESHOLD_LEN1 0x00000000UL 1070 #define TSP_REQ_VQ_RX_THRESHOLD_LEN2 0x00020000UL 1071 #define TSP_REQ_VQ_RX_THRESHOLD_LEN4 0x00040000UL 1072 #define TSP_REQ_VQ_RX_THRESHOLD_LEN8 0x00060000UL 1073 #define TSP_PIDFLT0_OVF_INT_EN 0x00400000UL 1074 #define TSP_PIDFLT0_CLR_OVF_INT 0x00800000UL 1075 #define TSP_PIDFLT0_FILE_OVF_INT_EN 0x01000000UL 1076 #define TSP_PIDFLT0_FILE_CLR_OVF_INT 0x02000000UL 1077 #define TSP_PIDFLT1_OVF_INT_EN 0x04000000UL 1078 #define TSP_PIDFLT1_CLR_OVF_INT 0x08000000UL 1079 #define TSP_PIDFLT2_OVF_INT_EN 0x10000000UL 1080 #define TSP_PIDFLT2_CLR_OVF_INT 0x20000000UL 1081 1082 REG32 MOBF_PVR1_Index; // 0xbf3a2c98 0x26 1083 #define TSP_MOBF_PVR1_INDEX0_MASK 0x0000000FUL 1084 #define TSP_MOBF_PVR1_INDEX0_SHIFT 0UL 1085 #define TSP_MOBF_PVR1_INDEX1_MASK 0x000F0000UL 1086 #define TSP_MOBF_PVR1_INDEX1_SHIFT 16UL 1087 1088 REG32 MOBF_PVR2_Index; // 0xbf3a2cA0 0x28 1089 #define TSP_MOBF_PVR2_INDEX0_MASK 0x0000000FUL 1090 #define TSP_MOBF_PVR2_INDEX0_SHIFT 0UL 1091 #define TSP_MOBF_PVR2_INDEX1_MASK 0x000F0000UL 1092 #define TSP_MOBF_PVR2_INDEX1_SHIFT 16UL 1093 1094 REG32 DMAW_LBND2; // 0xbf802ca8 0x2a 1095 1096 REG32 DMAW_UBND2; // 0xbf802cb0 0x2c 1097 1098 REG32 DMAW_LBND3; // 0xbf802cb8 0x2e //reserved 1099 1100 REG32 DMAW_UBND3; // 0xbf802cc0 0x30 //reserved 1101 1102 REG32 DMAW_LBND4; // 0xbf802cc8 0x32 1103 1104 REG32 DMAW_UBND4; // 0xbf802cd0 0x34 1105 1106 REG32 ORZ_DMAW_LBND; // 0xbf802cd8 0x36 1107 #define TSP_ORZ_DMAW_LBND_MASK 0xffffffffUL 1108 REG32 ORZ_DMAW_UBND; // 0xbf802ce0 0x38 1109 #define TSP_ORZ_DMAW_UBND_MASK 0xffffffffUL 1110 REG32 _xbf802ce8_xbf802cec; // 0xbf802ce8_0xbf802cec 0x3a~0x3b 1111 1112 REG32 HWPCR0_L; // 0xbf802cf0 0x3c 1113 REG32 HWPCR0_H; // 0xbf802cf8 0x3e 1114 1115 REG32 CA_CTRL; // 0xbf802d00 0x40 1116 #define TSP_CA_CTRL_MASK 0xffffffffUL 1117 #define TSP_CA0_CTRL_MASK 0x00007077UL 1118 #define TSP_CA0_INPUT_TSIF0_LIVEIN 0x00000001UL 1119 #define TSP_CA0_INPUT_TSIF0_FILEIN 0x00000002UL 1120 #define TSP_CA0_INPUT_TSIF1 0x00000004UL 1121 #define TSP_CA0_OUTPUT_PKTDMX0_LIVE 0x00000010UL 1122 #define TSP_CA0_OUTPUT_PKTDMX0_FILE 0x00000020UL 1123 #define TSP_CA0_OUTPUT_PKTDMX1 0x00000040UL 1124 #define TSP_CA0_INPUT_TSIF2 0x00001000UL 1125 #define TSP_CA0_OUTPUT_PKTDMX2 0x00002000UL 1126 #define TSP_CA0_OUTPUT_CA2 0x00004000UL 1127 1128 #define TSP_CA1_CTRL_MASK 0x77308000UL 1129 #define TSP_CA1_OUTPUT_CA2 0x00008000UL 1130 #define TSP_CA1_INPUT_TSIF2 0x00100000UL 1131 #define TSP_CA1_OUTPUT_PKTDMX2 0x00200000UL 1132 1133 #define TSP_CA2_CTRL_MASK_L 0x00C00000UL 1134 #define TSP_CA2_INPUT_TSIF2 0x00400000UL 1135 #define TSP_CA2_OUTPUT_PKTDMX2 0x00800000UL 1136 1137 #define TSP_CA1_INPUT_TSIF0_LIVEIN 0x01000000UL 1138 #define TSP_CA1_INPUT_TSIF0_FILEIN 0x02000000UL 1139 #define TSP_CA1_INPUT_TSIF1 0x04000000UL 1140 #define TSP_CA1_OUTPUT_PKTDMX0_LIVE 0x10000000UL 1141 #define TSP_CA1_OUTPUT_PKTDMX0_FILE 0x20000000UL 1142 #define TSP_CA1_OUTPUT_PKTDMX1 0x40000000UL 1143 1144 REG32 REG_ONEWAY; // 0xbf802d08 0x42 1145 #define TSP_ONEWAY_REC_DISABLE 0x00000001UL // Disable PVR 1146 #define TSP_ONEWAY_PVR1_PORT 0x00000002UL // Oneway for PVR1 buffer 1147 #define TSP_ONEWAY_PVR2_PORT 0x00000004UL // Oneway for PVR2 buffer 1148 #define TSP_ONEWAY_LOAD_FW_PORT 0x00000008UL // Oneway for f/w load address 1149 #define TSP_ONEWAY_QMEM 0x00000010UL 1150 #define TSP_ONEWAY_AV_NOT_TO_SEC 0x00000020UL // Oneway for block av packet to section 1151 1152 #define TSP_CA2_CTRL_MASK_H 0x00770000UL 1153 #define TSP_CA2_CTRL_SHIFT_H 16UL 1154 #define TSP_CA2_INPUT_TSIF0_LIVEIN 0x00000001UL 1155 #define TSP_CA2_INPUT_TSIF0_FILEIN 0x00000002UL 1156 #define TSP_CA2_INPUT_TSIF1 0x00000004UL 1157 #define TSP_CA2_OUTPUT_PKTDMX0_LIVE 0x00000010UL 1158 #define TSP_CA2_OUTPUT_PKTDMX0_FILE 0x00000020UL 1159 #define TSP_CA2_OUTPUT_PKTDMX1 0x00000040UL 1160 1161 #define TSP_CA3_CTRL_MASK 0x7F800000UL 1162 #define TSP_CA3_INPUT_TSIF0_LIVEIN 0x00800000UL 1163 #define TSP_CA3_INPUT_TSIF0_FILEIN 0x01000000UL 1164 #define TSP_CA3_INPUT_TSIF1 0x02000000UL 1165 #define TSP_CA3_INPUT_TSIF2 0x04000000UL 1166 #define TSP_CA3_OUTPUT_PKTDMX0_LIVE 0x08000000UL 1167 #define TSP_CA3_OUTPUT_PKTDMX0_FILE 0x10000000UL 1168 #define TSP_CA3_OUTPUT_PKTDMX1 0x20000000UL 1169 #define TSP_CA3_OUTPUT_PKTDMX2 0x40000000UL 1170 REG32 HWPCR1_L; // 0xbf802d10 0x44 1171 REG32 HWPCR1_H; // 0xbf802d18 0x46 1172 1173 REG32 _xbf802d20[4]; // 0xbf802d20~0xbf802d3c 0x48~0x4f //LPCR_CB 1174 1175 REG32 FIFO_Src; // 0xbf802d40 0x50 1176 #define TSP_AUD_SRC_MASK 0x00000007UL 1177 #define TSP_AUD_SRC_SHIFT 0UL 1178 #define TSP_SRC_FROM_PKTDMX0 0x00000001UL 1179 #define TSP_SRC_FROM_PKTDMXFL 0x00000002UL 1180 #define TSP_SRC_FROM_PKTDMX1 0x00000003UL 1181 #define TSP_SRC_FROM_PKTDMX2 0x00000004UL 1182 #define TSP_SRC_FROM_MMFI0 0x00000006UL 1183 #define TSP_SRC_FROM_MMFI1 0x00000007UL 1184 #define TSP_AUDB_SRC_MASK 0x00000038UL 1185 #define TSP_AUDB_SRC_SHIFT 3UL 1186 #define TSP_VID_SRC_MASK 0x000001C0UL 1187 #define TSP_VID_SRC_SHIFT 6UL 1188 #define TSP_VID3D_SRC_MASK 0x00000E00UL 1189 #define TSP_VID3D_SRC_SHIFT 9UL 1190 #define TSP_PVR1_SRC_MASK 0x00007000UL 1191 #define TSP_PVR1_SRC_SHIFT 12UL 1192 #define TSP_PCR0_SRC_MASK 0x001C0000UL 1193 #define TSP_PCR0_SRC_SHIFT 18UL 1194 #define TSP_PCR1_SRC_MASK 0x00E00000UL 1195 #define TSP_PCR1_SRC_SHIFT 21UL 1196 #define TSP_TEI_SKIP_PKT_PCR0 0x01000000UL 1197 #define TSP_PCR0_RESET 0x02000000UL 1198 #define TSP_PCR0_READ 0x08000000UL 1199 #define TSP_TEI_SKIP_PKT_PCR1 0x10000000UL 1200 #define TSP_PCR1_RESET 0x20000000UL 1201 #define TSP_PCR1_READ 0x80000000UL 1202 1203 REG32 STC_DIFF_BUF; // 0xbf802d48 0x52 1204 1205 REG32 STC_DIFF_BUF_H; // 0xbf802d50 0x54 1206 #define TSP_STC_DIFF_BUF_H_MASK 0x0000007FUL 1207 #define TSP_STC_DIFF_BUF_H_AHIFT 0UL 1208 #define TSP_PVR2_SRC_MASK 0x00070000UL 1209 #define TSP_PVR2_SRC_SHIFT 16UL 1210 1211 1212 REG32 VQ1_Base; // 0xbf802d58 0x56 1213 1214 REG32 _rbf802d60; // 0xbf802d60 0x58 1215 1216 REG32 CH_BW_CTRL; // 0xbf802d68 0x5a 1217 #define TSP_CH_BW_WP_LD 0x00000100UL 1218 1219 REG32 VQ1_Config; // 0xbf802d70 0x5C 1220 #define TSP_VQ1_SIZE_208BYTE_MASK 0x0000ffffUL 1221 #define TSP_VQ1_SIZE_208BYTE_SHIFT 0UL 1222 #define TSP_VQ1_WR_THRESHOLD_MASK 0x000F0000UL 1223 #define TSP_VQ1_WR_THRESHOLD_SHIFT 16UL 1224 #define TSP_VQ1_PRI_THRESHOLD_MASK 0x00F00000UL 1225 #define TSP_VQ1_PRI_THRESHOLD_SHIFT 20UL 1226 #define TSP_VQ1_FORCEFIRE_CNT_1K_MASK 0x0F000000UL 1227 #define TSP_VQ1_FORCEFIRE_CNT_1K_SHIFT 24UL 1228 #define TSP_VQ1_RESET 0x10000000UL 1229 #define TSP_VQ1_OVF_INT_EN 0x40000000UL 1230 #define TSP_VQ1_CLR_OVF_INT 0x80000000UL 1231 1232 REG32 VQ2_Base; // 0xbf802d78 0x5E 1233 1234 REG32 Pkt_Info3; // 0xbf802d80 0x60 1235 #define TSP_AFIFOC_STATUS 0x0000000FUL 1236 #define TSP_AFIFOC_STATUS_SHFT 0UL 1237 #define TSP_AFIFOD_STATUS 0x000000F0UL 1238 #define TSP_AFIFOD_STATUS_SHFT 4UL 1239 1240 REG32 Bist_Fail; // 0xbf802d88 0x62 1241 #define TSP_BIST_FAIL_STATUS_MASK 0x00FF0000UL 1242 #define TSP_BIST_FAIL_STATUS_SRAM1P192x8_MASK 0x00070000UL 1243 #define TSP_BIST_FAIL_STATUS_SRAM2P512x32w8 0x00080000UL 1244 #define TSP_BIST_FAIL_STATUS_SRAM2P16x128_MASK 0x00600000UL 1245 #define TSP_BIST_FAIL_STATUS_SRAM1P2048x32w8 0x00800000UL 1246 #define TSP_BIST_FAIL_STATUS_SRAM1P1024x32w8 0x01000000UL 1247 #define TSP_BIST_FAIL_STATUS_SRAM1P512x20 0x00200000UL 1248 1249 REG32 VQ2_Config; // 0xbf802d90 0x64 1250 #define TSP_VQ2_SIZE_208BYTE_MASK 0x0000ffffUL 1251 #define TSP_VQ2_SIZE_208BYTE_SHIFT 0UL 1252 #define TSP_VQ2_WR_THRESHOLD_MASK 0x000F0000UL 1253 #define TSP_VQ2_WR_THRESHOLD_SHIFT 16UL 1254 #define TSP_VQ2_PRI_THRESHOLD_MASK 0x00F00000UL 1255 #define TSP_VQ2_PRI_THRESHOLD_SHIFT 20UL 1256 #define TSP_VQ2_FORCEFIRE_CNT_1K_MASK 0x0F000000UL 1257 #define TSP_VQ2_FORCEFIRE_CNT_1K_SHIFT 24UL 1258 #define TSP_VQ2_RESET 0x10000000UL 1259 #define TSP_VQ2_OVF_INT_EN 0x40000000UL 1260 #define TSP_VQ2_CLR_OVF_INT 0x80000000UL 1261 1262 REG32 VQ_STATUS; // 0xbf802d98 0x66 1263 #define TSP_VQ_STATUS_MASK 0xFFFFFFFFUL 1264 #define TSP_VQ_STATUS_SHIFT 0UL 1265 #define TSP_VQ0_STATUS_READ_EVER_FULL 0x00001000UL 1266 #define TSP_VQ0_STATUS_READ_EVER_OVERFLOW 0x00002000UL 1267 #define TSP_VQ0_STATUS_EMPTY 0x00004000UL 1268 #define TSP_VQ0_STATUS_READ_BUSY 0x00008000UL 1269 #define TSP_VQ1_STATUS_READ_EVER_FULL 0x00010000UL 1270 #define TSP_VQ1_STATUS_READ_EVER_OVERFLOW 0x00020000UL 1271 #define TSP_VQ1_STATUS_EMPTY 0x00040000UL 1272 #define TSP_VQ1_STATUS_READ_BUSY 0x00080000UL 1273 #define TSP_VQ2_STATUS_READ_EVER_FULL 0x00100000UL 1274 #define TSP_VQ2_STATUS_READ_EVER_OVERFLOW 0x00200000UL 1275 #define TSP_VQ2_STATUS_EMPTY 0x00400000UL 1276 #define TSP_VQ2_STATUS_READ_BUSY 0x00800000UL 1277 #define TSP_VQ3_STATUS_READ_EVER_FULL 0x01000000UL 1278 #define TSP_VQ3_STATUS_READ_EVER_OVERFLOW 0x02000000UL 1279 #define TSP_VQ3_STATUS_EMPTY 0x04000000UL 1280 #define TSP_VQ3_STATUS_READ_BUSY 0x08000000UL 1281 #define TSP_VQ0_STATUS_TX_OVERFLOW 0x10000000UL 1282 #define TSP_VQ1_STATUS_TX_OVERFLOW 0x20000000UL 1283 #define TSP_VQ2_STATUS_TX_OVERFLOW 0x40000000UL 1284 #define TSP_VQ3_STATUS_TX_OVERFLOW 0x80000000UL 1285 1286 REG32 DM2MI_WAddr_Err; // 0xbf802da0 0x68 , DM2MI_WADDR_ERR0 1287 1288 REG32 ORZ_DMAW_WAddr_Err; // 0xbf802da8 0x6a , ORZ_WADDR_ERR0 1289 1290 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c 1291 #define TSP_HWINT2_EN_MASK 0x00FFUL 1292 #define TSP_HWINT2_EN_SHIFT 0UL 1293 #define TSP_HWINT2_STATUS_MASK 0xFF00UL 1294 #define TSP_HWINT2_STATUS_SHIFT 8UL 1295 #define TSP_HWINT2_PCR1_UPDATE_END 0x0400UL 1296 #define TSP_HWINT2_PCR0_UPDATE_END 0x0800UL 1297 #define TSP_HWINT2_PVRCB_MEET_MID_TAIL 0x1000UL 1298 #define TSP_HWINT2_ALL_DMA_WADDR_NOT_IN_PROCT_Z 0x2000UL 1299 #define TSP_HWINT2_VQ0_VQ1_VQ2_VQ3_OVERFLOW 0x4000UL 1300 #define TSP_HWINT2_PVR2_MID_TAIL_STATUS 0x8000UL 1301 1302 #define TSP_HWINT_HW_PVRCB_MASK TSP_HWINT2_PVRCB_MEET_MID_TAIL 1303 #define TSP_HWINT_HW_PVR2_MASK TSP_HWINT2_PVR2_MID_TAIL_STATUS 1304 #define TSP_HWINT2_ALL (TSP_HWINT_HW_PVRCB_MASK|TSP_HWINT_HW_PVR2_MASK|TSP_HWINT2_PCR0_UPDATE_END|TSP_HWINT2_PCR1_UPDATE_END) 1305 1306 #define TSP_SWINT1_L_SHFT 16UL 1307 #define TSP_SWINT1_L_MASK 0xFFFF0000UL 1308 1309 REG16 SwInt_Stat1_M; 1310 REG32 SwInt_Stat1_H; // 0xbf802dB8 0x6e 1311 #define TSP_SWINT1_H_SHFT 0UL 1312 #define TSP_SWINT1_H_MASK 0x0000FFFFUL 1313 1314 REG32 TimeStamp_FileIn; // 0xbf802dC0 0x70 1315 1316 REG32 HW2_Config3; // 0xbf802dC0 0x72 1317 #define TSP_WADDR_ERR_SRC_SEL_MASK 0x00000006UL 1318 #define TSP_WADDR_ERR_SRC_SEL_SHIFT 1UL 1319 #define TSP_WADDR_ERR_SRC_PVR 0x00000000UL 1320 #define TSP_WADDR_ERR_SRC_VQ 0x00000002UL 1321 #define TSP_WADDR_ERR_SRC_SEC_CB 0x00000004UL 1322 #define TSP_RM_OVF_GLITCH 0x00000008UL 1323 #define TSP_FILEIN_RADDR_READ 0x00000010UL 1324 #define TSP_DUP_PKT_CNT_CLR 0x00000040UL 1325 #define TSP_DMA_FLUSH_EN 0x00000080UL //PVR1, PVR2 dma flush 1326 #define TSP_REC_AT_SYNC_DIS 0x00000100UL 1327 #define TSP_PVR1_ALIGN_EN 0x00000200UL 1328 #define TSP_REC_FORCE_SYNC_EN 0x00000400UL 1329 #define TSP_RM_PKT_DEMUX_PIPE 0x00000800UL 1330 #define TSP_VQ_EN 0x00004000UL 1331 #define TSP_VQ2PINGPONG_EN 0x00008000UL 1332 #define TSP_PVR1_REC_ALL_EN 0x00010000UL 1333 #define TSP_PVR2_REC_ALL_EN 0x00020000UL 1334 #define TSP_REC_NULL 0x00040000UL 1335 #define TSP_REC_ALL_OLD 0x00080000UL 1336 #define TSP_RESET_AFIFO3 0x00400000UL 1337 #define TSP_RESET_AFIFO4 0x00800000UL 1338 #define TSP_TSIF0_CLK_STAMP_27_EN 0x01000000UL 1339 #define TSP_PVR1_CLK_STAMP_27_EN 0x02000000UL 1340 #define TSP_PVR2_CLK_STAMP_27_EN 0x04000000UL 1341 #define TSP_HW_CFG3_PS_AUDC_EN 0x10000000UL 1342 #define TSP_HW_CFG3_PS_AUDD_EN 0x20000000UL 1343 1344 REG32 VQ3_BASE; // 0xbf802dC0 0x74 1345 1346 REG32 VQ3_Config; // 0xbf802dC0 0x76 1347 #define TSP_VQ3_SIZE_208BYTE_MASK 0x0000ffffUL 1348 #define TSP_VQ3_SIZE_208BYTE_SHIFT 0UL 1349 #define TSP_VQ3_WR_THRESHOLD_MASK 0x000F0000UL 1350 #define TSP_VQ3_WR_THRESHOLD_SHIFT 16UL 1351 #define TSP_VQ3_PRI_THRESHOLD_MASK 0x00F00000UL 1352 #define TSP_VQ3_PRI_THRESHOLD_SHIFT 20UL 1353 #define TSP_VQ3_FORCEFIRE_CNT_1K_MASK 0x0F000000UL 1354 #define TSP_VQ3_FORCEFIRE_CNT_1K_SHIFT 24UL 1355 #define TSP_VQ3_RESET 0x10000000UL 1356 #define TSP_VQ3_OVF_INT_EN 0x40000000UL 1357 #define TSP_VQ3_CLR_OVF_INT 0x80000000UL 1358 1359 REG32 VQ_RX_Status; // 0xbf802dC0 0x78 1360 #define VQ_RX_ARBITER_MODE_MASK 0x0000000FUL 1361 #define VQ_RX_ARBITER_MODE_SHIFT 0UL 1362 #define VQ_RX0_PRI_MASK 0x000000F0UL 1363 #define VQ_RX0_PRI_SHIFT 4UL 1364 #define VQ_RX1_PRI_MASK 0x00000F00UL 1365 #define VQ_RX1_PRI_SHIFT 8UL 1366 #define VQ_RX2_PRI_MASK 0x0000F000UL 1367 #define VQ_RX2_PRI_SHIFT 12UL 1368 #define VQ_RX3_PRI_MASK 0x000F0000UL 1369 #define VQ_RX3_PRI_SHIFT 16UL 1370 1371 REG32 _xbf802dC0; // 0xbf802dC0 0x7a 1372 1373 REG32 MCU_Data1; // 0xbf802dC0 0x7c 1374 } REG_Ctrl; 1375 1376 // TSP part 2 1377 typedef struct _REG_Ctrl2 1378 { 1379 REG16 Qmem_Dbg; // 0xbf803ac0 0x70 1380 #define QMEM_DBG_MODE 0x0001 1381 #define QMEM_DBG_TSP_SEL_SRAM 0x0002 1382 REG16 Qmem_Dbg_RAddr; // 0xbf803ac4 0x71 1383 #define QMEM_DBG_RADDR_MASK 0xFFFF 1384 REG32 Qmem_Dbg_RD ; // 0xbf803ac8~0xbf803acc 0x72~0x73 1385 1386 } REG_Ctrl2; 1387 1388 typedef struct _REG_Ctrl3 1389 { 1390 REG16 PktConverterCfg[4]; // 0x10~13 1391 #define INPUT_MODE_MASK 0x0007UL 1392 #define INPUT_MODE_SHIF 0UL 1393 // input mode of pkt_converter0(need to turn on reg_eco_fiq_input(TSP5,0c[7]) when flow through FIQ) 1394 // 0: normal 188 1395 // 1:CI+1.4 188 1396 // 2.Opencable 1397 // 3:192 mode 1398 // 4:MxL mode (192 / 196 / 200 bytes, but flexible by pkt_header_len) 1399 // 3. reg_filter_null_pkt(TSP5,06[2]) 1400 // 5:Nagra Dongle mode (192 bytes, but flexible by pkt_header_len & sync_byte_position) 1401 #define FORCE_SYNC_0X47 0x0008UL 1402 #define BYPASS_PKT_CONVERTER 0x0010UL 1403 #define BYPASS_SRC_ID_PARSER 0x0020UL 1404 #define SRC_ID_FLT_EN 0x0040UL 1405 #define MXL_TS_HEADER_LEN_MASK 0x0F80UL 1406 #define MXL_TS_HEADER_LEN_SHFT 0x7UL 1407 // 4 : Mxl 192 or Nagra Dongle 192 1408 // 8 : Mxl 196 1409 // 12 : Mxl 200 1410 #define SYNC_BYTE_POS_MASK 0xF000UL 1411 #define SYNC_BYTE_POS_SHFT 0x12UL 1412 // 1 : Nagra Dongle 192 1413 1414 REG16 HW3_Cfg0; //0x14 1415 #define PREVENT_SRAM_COLLISION 0x0001UL 1416 #define PUSI_THREE_BYTE_MODE 0x0002UL 1417 #define PVR1_TIMESTAMP_SRC 0x0004UL // 1: FIQ 0: LPCR 1418 #define PVR2_TIMESTAMP_SRC 0x0004UL 1419 #define PCR0_SRC_MASK 0x0F00UL 1420 #define PCR0_SRC_SHIFT 8UL 1421 #define PCR1_SRC_MASK 0xF000UL 1422 #define PCR1_SRC_SHIFT 12UL 1423 1424 REG16 HW3_Cfg1; //0x15 1425 #define MASK_SCR_VID_EN 0x0001UL 1426 #define MASK_SCR_VID_3D_EN 0x0002UL 1427 #define MASK_SCR_AUD_EN 0x0004UL 1428 #define MASK_SCR_AUD_B_EN 0x0008UL 1429 #define MASK_SCR_AUD_C_EN 0x0010UL 1430 #define MASK_SCR_AUD_D_EN 0x0020UL 1431 #define MASK_SCR_PVR1_EN 0x0040UL 1432 #define MASK_SCR_PVR2_EN 0x0080UL 1433 #define RST_CC_MODE 0x0100UL 1434 #define DIS_CNTR_INC_BY_PL 0x0200UL 1435 #define BYPASS_TIMESTAMP_SEL0 0x0400UL 1436 #define BYPASS_TIMESTAMP_SEL1 0x0800UL 1437 #define APID_C_BYPASS 0x1000UL 1438 #define APID_D_BYPASS 0x2000UL 1439 REG32 PauseTime[2]; // 0x16~17, 0x18~19 1440 REG32 PIDFLR_PCR[2]; 1441 #define TSP_PIDFLT_PCR_PID_MASK 0x00001fffUL 1442 #define TSP_PIDFLT_PCR_EN 0x00008000UL 1443 #define TSP_PIDFLT_PCR_SOURCE_MASK 0x000F0000UL 1444 #define TSP_PIDFLT_PCR_SOURCE_SHIFT 16UL 1445 REG32 Reserve; // 0x1e 1446 REG16 HW_Semaphore0; // 0x20 1447 REG16 HW_Semaphore1; // 0x21 1448 REG16 HW_Semaphore2; // 0x22 1449 1450 REG16 HWeco0; // 0x23 1451 #define HW_ECO_RVU 0x0001UL //RVU, reg_start_read_bypass_en, set 1 to fix start_read hang when unexpected writes 1452 #define HW_ECO_NEW_SYNCP_IN_ECO 0x0002UL // fixed_rm_pinpong_limation_en 1453 #define HW_ECO_SEC_DMA_BURST_NEWMODE 0x000CUL // fixed bust length 2 /4 issue 1454 #define HW_ECO_FIQ_REVERSE_DEADLOCK 0x0010UL // fix FIQ will be deadlock when reverse block 1455 #define HW_ECO_FIX_SEC_NULLPKT_ERR 0x0020UL // fix section can't receive pid 1ffb pkt 1456 #define HW_ECO_INIT_TIMESTAMP 0x0400UL // set 1 to init timestamp when filein start 1457 1458 REG16 HWeco1; // 0x24 1459 REG16 ModeCfg; // 0x25 1460 #define TSP_3WIRE_SERIAL_MODE_MASK 0x001FUL //set 1 to enable 3 wire serial in mode: Combine valid and clk.Valid always 1 and gated clk when no data in 1461 #define TSP_3WIRE_SERIAL_TSIF0 0x0001UL 1462 #define TSP_3WIRE_SERIAL_TSIF1 0x0002UL 1463 #define TSP_3WIRE_SERIAL_TSIF2 0x0004UL 1464 #define TSP_3WIRE_SERIAL_TSIFFI 0x0010UL 1465 #define TSP_NEW_OVERFLOW_MODE 0x0100UL // 1: new dma_overflow 0:old dma_overflow 1466 #define TSP_NON_188_CNT_MODE 0x0200UL 1467 #define TSP_STREAMID_CHK_DISABLE 0x0400UL // 1 : for nagra dongle, sync byte = 0x00, 0x80 or 0x81 1468 #define TSP_FILTER_STREAMID_0_TO_1F 0x0800UL 1469 1470 REG16 NAGRA_DONGLE_SYNCBYTE; // 0x26 1471 #define SYNC_BYTE0_MASK 0x00FFUL 1472 #define SYNC_BYTE0_SHFT 0UL 1473 #define SYNC_BYTE1_MASK 0xFF00UL 1474 #define SYNC_BYTE1_SHFT 8UL 1475 1476 REG16 dummy; // 0x27 1477 1478 REG16 SyncByte_tsif0[4]; // 0x28~2b 1479 #define TSP_SYNC_BYTE0_MAASK0 0x00FFUL 1480 #define TSP_SYNC_BYTE0_MAASK1 0xFF00UL 1481 REG16 SourceId_tsif0[2]; // 0x2c~2d 1482 #define TSP_SRCID_MASK0 0x000FUL 1483 #define TSP_SRCID_MASK1 0x00F0UL 1484 #define TSP_SRCID_MASK2 0x0F00UL 1485 #define TSP_SRCID_MASK3 0xF000UL 1486 REG16 SyncByte_file[4]; // 0x2e~31 1487 REG16 SourceId_file[2]; // 0x32~33 1488 REG16 SyncByte_tsif1[4]; // 0x34~37 1489 REG16 SourceId_tsif1[2]; // 0x38~39 1490 REG16 SyncByte_tsif2[4]; // 0x3a~3d 1491 REG16 SourceId_tsif2[2]; // 0x3e~3f 1492 } REG_Ctrl3; 1493 1494 // TSP part 4 1495 typedef struct _REG_Ctrl4 1496 { 1497 REG16 Overflow0; // 0xbf803900 0x00 1498 #define PID_HIT_0_EVER_OVERFLOW 0x0001UL 1499 #define PID_HIT_1_EVER_OVERFLOW 0x0002UL 1500 #define PID_HIT_2_EVER_OVERFLOW 0x0004UL 1501 #define PID_HIT_FILE_EVER_OVERFLOW 0x0008UL 1502 #define PID_HIT_CB_EVER_OVERFLOW 0x0010UL 1503 #define AFIFO_EVER_OVERFLOW 0x0020UL 1504 #define AFIFOB_EVER_OVERFLOW 0x0040UL 1505 #define VFIFO_EVER_OVERFLOW 0x0080UL 1506 #define V3DFIFO_EVER_OVERFLOW 0x0100UL 1507 #define PVR_1_EVER_OVERFLOW 0x0200UL 1508 #define PVR_2_EVER_OVERFLOW 0x0400UL 1509 #define VQ_TX0_EVER_OVERFLOW 0x1000UL 1510 #define VQ_TX1_EVER_OVERFLOW 0x2000UL 1511 #define VQ_TX2_EVER_OVERFLOW 0x4000UL 1512 #define VQ_TX3_EVER_OVERFLOW 0x8000UL 1513 1514 REG16 Overflow1; // 0xbf803904 0x01 1515 #define AFIFOD_EVER_OVERFLOW 0x0010UL 1516 #define AFIFOC_EVER_OVERFLOW 0x0008UL 1517 #define SEC_DMAW_OVERFLOW 0x0004UL 1518 #define SEC_SINGLE_EVER_OVERFLOW 0x0002UL 1519 #define SEC_PINGPONG_EVER_OVERFLOW 0x0001UL 1520 1521 REG16 FifoStatus; // 0xbf803908 0x02 1522 #define AFIFO_STATUS_MASK 0x000FUL 1523 #define AFIFO_STATUS_SHFT 0UL 1524 #define AFIFOC_STATUS_MASK 0x000FUL 1525 #define AFIFOC_STATUS_SHFT 0UL 1526 #define AFIFOB_STATUS_MASK 0x00F0UL 1527 #define AFIFOB_STATUS_SHFT 4UL 1528 #define AFIFOD_STATUS_MASK 0x00F0UL 1529 #define AFIFOD_STATUS_SHFT 4UL 1530 #define VFIFO_STATUS_MASK 0x0F00UL 1531 #define VFIFO_STATUS_SHFT 8UL 1532 #define V3DFIFO_STATUS_MASK 0xF000UL 1533 #define V3DFIFO_STATUS_SHFT 12UL 1534 1535 REG16 PvrFifoStatus; // 0xbf80390C 0x03 1536 #define PVR_1_STATUS_MASK 0x000FUL 1537 #define PVR_1_STATUS_SHFT 0UL 1538 1539 REG16 VQTxFifoStatus; // 0xbf803910 0x04 1540 #define VQ_TX0_STATUS_MASK 0x000FUL 1541 #define VQ_TX0_STATUS_SHFT 0UL 1542 #define VQ_TX1_STATUS_MASK 0x0F00UL 1543 #define VQ_TX1_STATUS_SHFT 8UL 1544 1545 REG16 PktCnt_video; // 0xbf803914 0x05 1546 REG16 PktCnt_v3d; // 0xbf803918 0x06 1547 REG16 PktCnt_aud; // 0xbf80391C 0x07 1548 REG16 PktCnt_audB; // 0xbf803920 0x08 1549 REG16 PktCnt_audC; // 0xbf803924 0x09 1550 REG16 PktCnt_audD; // 0xbf803928 0x0a 1551 1552 REG32 _bf803924[1]; // 0xbf80392C~0xbf803930 0x0b~0x0c 1553 1554 REG16 LockedPktCnt; // 0x0d 1555 REG16 AVPktCnt; // 0x0e 1556 1557 REG16 PktErrStatus; // 0xbf80392C 0x0x0f 1558 REG16 PidMatched0; // 0xbf803930 0x10 1559 REG16 PidMatched1; // 0xbf803934 0x11 1560 REG16 PidMatched2; // 0xbf803938 0x12 1561 REG16 PidMatched3; // 0xbf80393C 0x13 1562 REG16 dummy[2]; // 0x14~0x15 1563 REG16 Sram2p_collision; // 0x16 1564 #define SRAM_COLLISION_BY_SW 0x1000UL 1565 #define SRAM_COLLISION_BY_HW 0x2000UL 1566 #define SECFLT_SRAM1_EVER_COLLISION 0x4000UL 1567 #define SECFLT_SRAM0_EVER_COLLISION 0x8000UL 1568 REG16 AVPktCnt1; //for vid_3d/audb 0x17 1569 REG16 ErrPktCnt; //use reg_err_pkt_src_sel 0x18 1570 REG16 AVPktCnt2; //for audc/audd 0x19 1571 1572 REG16 EverUnlockStatus; // 0x1a 1573 #define EVER_UNLOCK_TS0 0x0001UL // set 1 mean there are unlock pkts 1574 #define EVER_UNLOCK_TS1 0x0002UL 1575 #define EVER_UNLOCK_TS2 0x0004UL 1576 1577 REG16 Overflow2; // 0xbf803904 0x1b 1578 #define PC_EVER_OVERFLOW_0 0x0001UL 1579 #define PC_EVER_OVERFLOW_FILE 0x0002UL 1580 #define PC_EVER_OVERFLOW_1 0x0004UL 1581 #define PC_EVER_OVERFLOW_2 0x0008UL 1582 1583 REG16 dummy1[0x70-0x1c]; //0x1C~0x6f 1584 REG16 ErrPktSrcSel; //select source of ErrPktCnt 0x70 1585 #define ERR_PKT_SRC_TS0 0x0001UL 1586 #define ERR_PKT_SRC_FILE 0x0002UL 1587 #define ERR_PKT_SRC_TS1 0x0003UL 1588 #define ERR_PKT_SRC_TS2 0x0004UL 1589 #define ERR_PKT_SRC_MMFI0 0x0005UL 1590 #define ERR_PKT_SRC_MMFI1 0x0006UL 1591 1592 REG16 ErrPktCntLoad; // 0x71 1593 #define ERR_PKT_CNT_0_LOAD 0x0001UL 1594 #define ERR_PKT_CNT_FILE_LOAD 0x0002UL 1595 #define ERR_PKT_CNT_1_LOAD 0x0004UL 1596 #define ERR_PKT_CNT_2_LOAD 0x0008UL 1597 #define ERR_PKT_CNT_MMFI0_LOAD 0x0010UL 1598 #define ERR_PKT_CNT_MMFI1_LOAD 0x0020UL 1599 1600 REG16 ErrPktCntClr; // 0x72 1601 #define ERR_PKT_CNT_0_CLR 0x0001UL 1602 #define ERR_PKT_CNT_FILE_CLR 0x0002UL 1603 #define ERR_PKT_CNT_1_CLR 0x0004UL 1604 #define ERR_PKT_CNT_2_CLR 0x0008UL 1605 #define ERR_PKT_CNT_MMFI0_CLR 0x0010UL 1606 #define ERR_PKT_CNT_MMFI1_CLR 0x0020UL 1607 1608 REG16 dummy2[0x78-0x73]; // 0x73~0x78 1609 1610 REG16 PktCntSrc2; // 0x78 1611 #define AUDC_SRC_MASK 0x0007UL 1612 #define AUDC_SRC_SHIFT 0UL 1613 #define AUDD_SRC_MASK 0x0038UL 1614 #define AUDD_SRC_SHIFT 3UL 1615 1616 REG16 dummy3; // 0x79 1617 REG16 PktCntLoad; // 0x7a 1618 #define LOCK_PKT_CNT_0_LOAD 0x0001UL 1619 #define LOCK_PKT_CNT_1_LOAD 0x0002UL 1620 #define LOCK_PKT_CNT_2_LOAD 0x0004UL 1621 #define LOCK_PKT_CNT_FI_LOAD 0x0010UL 1622 #define V_PKT_CNT_LOAD 0x0100UL 1623 #define V3D_PKT_CNT_LOAD 0x0200UL 1624 #define AUD_PKT_CNT_LOAD 0x0400UL 1625 #define AUDB_PKT_CNT_LOAD 0x0800UL 1626 #define AUDC_PKT_CNT_LOAD 0x1000UL 1627 #define AUDD_PKT_CNT_LOAD 0x2000UL 1628 1629 REG16 PktCntLoad1; // 0x7b 1630 #define V_DROP_PKT_CNT_LOAD 0x0001UL 1631 #define V3D_DROP_PKT_CNT_LOAD 0x0002UL 1632 #define AUD_DROP_PKT_CNT_LOAD 0x0004UL 1633 #define AUDB_DROP_PKT_CNT_LOAD 0x0008UL 1634 #define AUDC_DROP_PKT_CNT_LOAD 0x0010UL 1635 #define AUDD_DROP_PKT_CNT_LOAD 0x0020UL 1636 #define V_DIS_CNTR_PKT_CNT_LOAD 0x0100UL 1637 #define V3D_DIS_CNTR_PKT_CNT_LOAD 0x0200UL 1638 #define AUD_DIS_CNTR_PKT_CNT_LOAD 0x0400UL 1639 #define AUDB_DIS_CNTR_PKT_CNT_LOAD 0x0800UL 1640 #define AUDC_DIS_CNTR_PKT_CNT_LOAD 0x1000UL 1641 #define AUDD_DIS_CNTR_PKT_CNT_LOAD 0x2000UL 1642 1643 REG16 PktCntClr; // 0x7c 1644 #define LOCK_PKT_CNT_0_CLR 0x0001UL 1645 #define LOCK_PKT_CNT_1_CLR 0x0002UL 1646 #define LOCK_PKT_CNT_2_CLR 0x0004UL 1647 #define LOCK_PKT_CNT_FI_CLR 0x0010UL 1648 #define V_PKT_CNT_CLR 0x0100UL 1649 #define V3D_PKT_CNT_CLR 0x0200UL 1650 #define AUD_PKT_CNT_CLR 0x0400UL 1651 #define AUDB_PKT_CNT_CLR 0x0800UL 1652 #define AUDC_PKT_CNT_CLR 0x1000UL 1653 #define AUDD_PKT_CNT_CLR 0x2000UL 1654 1655 REG16 PktCntClr1; // 0x7d 1656 #define V_DROP_PKT_CNT_CLR 0x0001UL 1657 #define V3D_DROP_PKT_CNT_CLR 0x0002UL 1658 #define AUD_DROP_PKT_CNT_CLR 0x0004UL 1659 #define AUDB_DROP_PKT_CNT_CLR 0x0008UL 1660 #define AUDC_DROP_PKT_CNT_CLR 0x0010UL 1661 #define AUDD_DROP_PKT_CNT_CLR 0x0020UL 1662 #define V_DIS_CNTR_PKT_CNT_CLR 0x0100UL 1663 #define V3D_DIS_CNTR_PKT_CNT_CLR 0x0200UL 1664 #define AUD_DIS_CNTR_PKT_CNT_CLR 0x0400UL 1665 #define AUDB_DIS_CNTR_PKT_CNT_CLR 0x0800UL 1666 #define AUDC_DIS_CNTR_PKT_CNT_CLR 0x1000UL 1667 #define AUDD_DIS_CNTR_PKT_CNT_CLR 0x2000UL 1668 1669 REG16 PktCntSrc; // 0x7e 1670 #define VID_SRC_MASK 0x0007UL 1671 #define VID_SRC_SHIFT 0UL 1672 #define V3D_SRC_MASK 0x0031UL 1673 #define V3D_SRC_SHIFT 3UL 1674 #define AUD_SRC_MASK 0x01C0UL 1675 #define AUD_SRC_SHIFT 6UL 1676 #define AUDB_SRC_MASK 0x0E00UL 1677 #define AUDB_SRC_SHIFT 9UL 1678 1679 REG16 DebugSrcSel; // 0x7f 1680 #define SRC_SEL_MASK 0x0001UL 1681 #define DROP_PKT_MODE_MASK 0x0002UL 1682 #define PIDFLT_SRC_SEL_MASK 0x001CUL 1683 #define TSIF_SRC_SEL_MASK 0x00E0UL 1684 #define TSIF_SRC_SEL_SHIFT 5UL 1685 #define TSIF_SRC_SEL_TSIF0 0x000UL 1686 #define TSIF_SRC_SEL_TSIF1 0x001UL 1687 #define TSIF_SRC_SEL_TSIF2 0x002UL 1688 #define TSIF_SRC_SEL_TSIF_FI 0x004UL 1689 #define AV_PKT_SRC_SEL 0x0100UL 1690 #define AV_PKT_SRC_SEL_MASK 0x0100UL 1691 #define AV_PKT_SRC_SEL_SHIFT 8UL 1692 #define AV_PKT_SRC_VID 0x0 1693 #define AV_PKT_SRC_AUD 0x1 1694 #define AV_PKT_SRC_V3D 0x0 1695 #define AV_PKT_SRC_AUDB 0x1 1696 #define AV_PKT_SRC_AUDC 0x0 1697 #define AV_PKT_SRC_AUDD 0x1 1698 #define CLR_SRC_MASK 0x0E00UL 1699 #define CLR_SRC_SHIFT 9UL 1700 #define CLR_SRC_TSIF0 0x0200UL 1701 #define CLR_SRC_TSIFFI 0x0400UL 1702 #define CLR_SRC_TSIF1 0x0600UL 1703 #define CLR_SRC_TSIF2 0x0800UL 1704 #define CLR_SRC_MMFI0 0x0C00UL 1705 #define CLR_SRC_MMFI1 0x0E00UL 1706 1707 }REG_Ctrl4; 1708 1709 // TSP part 4 1710 typedef struct _REG_Ctrl5 1711 { 1712 REG16 ATS_Adj_Period; // 0x00 1713 #define TSP_ATS_ADJ_PERIOD_MASK 0x000FUL 1714 1715 REG16 AtsCfg; // 0x01 1716 #define TSP_ATS_MODE_FI_ENABLE 0x0001UL 1717 #define TSP_ATS_OFFSET_FI_ENABLE 0x0002UL 1718 #define TSP_ATS_OFFSET_FI_SHIFT 8UL 1719 #define TSP_ATS_OFFSET_FI_MASK 0x0F00UL 1720 #define TSP_ATS_OFFSET_FI_POSITIVE 0x0000UL 1721 #define TSP_ATS_OFFSET_FI_NEGATIVE 0x1000UL 1722 1723 REG16 Ts_If_Fi_Cfg; // 0x02 1724 #define TSP_FIIF_EN 0x0001UL 1725 #define TSP_FIIF_DATA_SWAP 0x0002UL 1726 #define TSP_FIIF_P_SEL 0x0004UL 1727 #define TSP_FIIF_EXT_SYNC_SEL 0x0008UL 1728 #define TSP_FIIF_MUX_MASK 0x0010UL 1729 #define TSP_FIIF_MUX_FILE_PATH 0x0000UL 1730 #define TSP_FIIF_MUX_LIVE_PATH 0x0010UL 1731 #define TSP_PKT_CHK_SIZE_FI_MASK 0xFF00UL 1732 #define TSP_PKT_CHK_SIZE_FI_SHIFT 8UL 1733 1734 REG16 MatchPidSel; // 0x03 1735 #define TSP_MATCH_PID_SEL_MASK 0x000FUL 1736 #define TSP_MATCH_PID_SEL_SHIFT 0UL 1737 1738 REG16 TsifCfg; // 0x04 1739 #define TSP_TSIFCFG_TSIF0_TSOBLK_EN 0x0100UL 1740 #define TSP_TSIFCFG_TSIF1_TSOBLK_EN 0x0200UL 1741 #define TSP_TSIFCFG_TSIF2_TSOBLK_EN 0x0400UL 1742 #define TSP_TSIFCFG_TSIFFI_TSOBLK_EN 0x0800UL 1743 #define TSP_TSIFCFG_WB_FSM_RESET 0x1000UL 1744 #define TSP_TSIFCFG_WB_FSM_RESET_FINISH 0x2000UL 1745 1746 REG16 TraceMarkCfg; // 0x05 1747 #define TSP_TRACE_MARK_VID_EN 0x0001UL 1748 #define TSP_TRACE_MARK_V3D_EN 0x0002UL 1749 #define TSP_TRACE_MARK_AUD_EN 0x0004UL 1750 #define TSP_TRACE_MARK_AUDB_EN 0x0008UL 1751 #define TSP_TRACE_MARK_AUDC_EN 0x0010UL 1752 #define TSP_TRACE_MARK_AUDD_EN 0x0020UL 1753 1754 REG16 HwCfg0; // 0x06 1755 #define TSP_FIX_192_TIMER_0_EN 0x0001UL 1756 #define TSP_VQ_CLR 0x0002UL 1757 #define TSP_FILTER_NULL_PKT0 0x0004UL 1758 #define TSP_FILTER_NULL_PKT1 0x0008UL 1759 #define TSP_FILTER_NULL_PKT2 0x0010UL 1760 #define TSP_FILTER_NULL_PKT_FILE 0x0020UL 1761 #define TSP_FLUSH_PVR1_DATA 0x0100UL 1762 #define TSP_FLUSH_PVR2_DATA 0x0200UL 1763 1764 REG16 InitTimestamp; // 0x07 1765 #define TSP_INIT_TIMESTAMP_FILEIN 0x0001UL 1766 #define TSP_INIT_TIMESTAMP_MMFI0 0x0002UL 1767 #define TSP_INIT_TIMESTAMP_MMFI1 0x0004UL 1768 #define TSP_MATCH_CNT_FILEIN 0x0008UL // set 1 to enable match cnt function for filein 1769 #define TSP_MATCH_CNT_THRESHOLD_MASK 0x00F0UL // file in will lost lock when match cnt <= threshold 1770 #define TSP_MATCH_CNT_THRESHOLD_SHFT 4UL 1771 #define TSP_INIT_TRUST_SYNC_CNT_MASK 0xFF00UL // reg_init_trust_sync_cnt_value for Filein 1772 #define TSP_INIT_TRUST_SYNC_CNT_SHFT 8UL // 188 : normal 192 mode (+4 is sync byte) 1773 // 189 : nagra dongle 192 mode (+3 is sync byte) 1774 1775 REG16 MiuSelCtrl0; // 0x08 1776 #define TSP_MIU_SEL_FILEIN_MASK 0x0003UL 1777 #define TSP_MIU_SEL_FILEIN_SHIFT 0UL 1778 #define TSP_MIU_SEL_SECTION_MASK 0x000CUL 1779 #define TSP_MIU_SEL_SECTION_SHIFT 2UL 1780 #define TSP_MIU_SEL_MMFI0_MASK 0x0030UL 1781 #define TSP_MIU_SEL_MMFI0_SHIFT 4UL 1782 #define TSP_MIU_SEL_MMFI1_MASK 0x00C0UL 1783 #define TSP_MIU_SEL_MMFI1_SHIFT 6UL 1784 #define TSP_MIU_SEL_VQ_RW_MASK 0x0300UL 1785 #define TSP_MIU_SEL_VQ_RW_SHIFT 8UL 1786 #define TSP_MIU_SEL_OR_RW_MASK 0x0C00UL 1787 #define TSP_MIU_SEL_OR_RW_SHIFT 10UL 1788 #define TSP_MIU_SEL_PVRCB_RW_MASK 0x3000UL 1789 #define TSP_MIU_SEL_PVRCB_RW_SHIFT 12UL 1790 1791 REG16 MiuSelCtrl1; // 0x09 1792 #define TSP_MIU_SEL_PVR1_MASK 0x0003UL 1793 #define TSP_MIU_SEL_PVR1_SHIFT 0UL 1794 #define TSP_MIU_SEL_PVR2_MASK 0x000CUL 1795 #define TSP_MIU_SEL_PVR2_SHIFT 2UL 1796 #define TSP_MIU_SEL_FIQ0_RW_MASK 0x0300UL 1797 #define TSP_MIU_SEL_FIQ0_RW_SHIFT 8UL 1798 #define TSP_MIU_SEL_FIQ1_RW_MASK 0x0C00UL 1799 #define TSP_MIU_SEL_FIQ1_RW_SHIFT 10UL 1800 1801 REG16 MiuRrPri; // 0x0A 1802 #define TSP_MIU_RR_PRI_ABT0 0x0001UL 1803 #define TSP_MIU_RR_PRI_ABT1 0x0002UL 1804 #define TSP_MIU_RR_PRI_ABT2 0x0004UL 1805 #define TSP_MIU_RR_PRI_ABT3 0x0008UL 1806 #define TSP_MIU_RR_PRI_ABT4 0x0010UL 1807 1808 REG16 FIQ_MUX_CFG; // 0xB 1809 #define FIQ_MUX_CFG_MASK 0x0007UL 1810 #define FIQ_MUX_CFG_SHFT 0UL 1811 #define FIQ_MUX_CFG_TS0 0x0000UL 1812 #define FIQ_MUX_CFG_FILE 0x0001UL 1813 #define FIQ_MUX_CFG_TS1 0x0002UL 1814 #define FIQ_MUX_CFG_TS2 0x0003UL 1815 1816 REG16 HWeco2; // 0xC 1817 #define HW_ECO_TIMESTAMP_RING_BACK 0x0001UL // set 1 to fix time stamp ring back from 32'hffff_ffff 1818 #define HW_ECO_LPCR_RING_BACK 0x0002UL // set 1 to fix lpcr ring back from 32'hffff_ffff 1819 #define NMATCH_DISABLE 0x0008UL // set 1 to disable secflt_not_match 1820 #define SCRAMB_BIT_AFTER_CA 0x0010UL // set 1 to see match pid scramble status after ca on TSP1,0c~0d 1821 #define HW_ECO_TS_SYNC_OUT_DELAY 0x0020UL // set 1 to fix MxL FIQ no timestamp issue 1822 #define HW_ECO_TS_SYNC_OUT_REVERSE_BLK 0x0040UL // set 1 to fix MxL FIQ no timestamp issue & reverse block 1823 #define HW_ECO_FIQ_INPUT 0x0080UL // set 1 to fix MxL FIQ sync early issue 1824 #define SECFLT_CTRL_DMA_DISABLE 0x0100UL // set 1 to disable sec_dma update section sram table 1825 #define PKT_CONVERTER_FIRST_SYNC_VLD_MASK 0x0200UL // set 1 to enable first sync valid mask for pkt_converter 1826 1827 REG16 dummy0[0x10-0xD]; // 0xD~0xF 1828 1829 REG16 TS_MUX_CFG0; // 0x10 1830 #define TS_MUX_CFG_TS0_MUX_MASK 0x000FUL 1831 #define TS_MUX_CFG_TS0_MUX_SHIFT 0UL 1832 #define TS_MUX_CFG_TS1_MUX_MASK 0x00F0UL 1833 #define TS_MUX_CFG_TS1_MUX_SHIFT 4UL 1834 #define TS_MUX_CFG_TS2_MUX_MASK 0x0F00UL 1835 #define TS_MUX_CFG_TS2_MUX_SHIFT 8UL 1836 #define TS_MUX_CFG_TSFI_MUX_MASK 0xF000UL 1837 #define TS_MUX_CFG_TSFI_MUX_SHIFT 12UL 1838 #define TS_MUX_CFG_TS_MUX_TS0 0x0000UL 1839 #define TS_MUX_CFG_TS_MUX_TS1 0x0001UL 1840 #define TS_MUX_CFG_TS_MUX_TS2 0x0002UL 1841 #define TS_MUX_CFG_TS_MUX_TSO 0x0006UL 1842 #define TS_MUX_CFG_TS_MUX_DMD 0x0007UL 1843 REG16 TS_MUX_CFG1; // 0x11 1844 1845 REG16 TS_MUX_CFG_S2P; // 0x12 1846 #define TS_MUX_CFG_S2P0_MUX_MASK 0x000FUL 1847 #define TS_MUX_CFG_S2P1_MUX_MASK 0x00F0UL 1848 #define TS_MUX_CFG_S2P0_MUX_SHIFT 0 1849 #define TS_MUX_CFG_S2P1_MUX_SHIFT 4 1850 #define TS_MUX_CFG_S2P_MUX_TS0 0x0000UL 1851 #define TS_MUX_CFG_S2P_MUX_TS1 0x0001UL 1852 #define TS_MUX_CFG_S2P_MUX_TS2 0x0002UL 1853 1854 REG16 TS_MUX_CFG0_TSOIN; // 0x13 1855 #define TS_MUX_CFG_TSOIN0_MUX_MASK 0x000FUL 1856 #define TS_MUX_CFG_TSOIN0_MUX_SHIFT 0UL 1857 #define TS_MUX_CFG_TSOIN1_MUX_MASK 0x00F0UL 1858 #define TS_MUX_CFG_TSOIN1_MUX_SHIFT 4UL 1859 #define TS_MUX_CFG_TSOIN2_MUX_MASK 0x0F00UL 1860 #define TS_MUX_CFG_TSOIN2_MUX_SHIFT 8UL 1861 #define TS_MUX_CFG_TSO_MUX_TS0 0x0000UL 1862 #define TS_MUX_CFG_TSO_MUX_TS1 0x0001UL 1863 #define TS_MUX_CFG_TSO_MUX_TS2 0x0002UL 1864 #define TS_MUX_CFG_TSO_MUX_DMD 0x0007UL 1865 1866 REG16 TSP5_Reserve_14; // 0x14 1867 1868 REG16 TS_MUX_CFG_TSOOUT; // 0x15 1869 #define TS_MUX_CFG_TSOOUT_MASK 0x000FUL 1870 #define TS_MUX_CFG_TSOOUT_FROM_TSO 0x0000UL 1871 #define TS_MUX_CFG_TSOOUT_FROM_S2P 0x0001UL 1872 1873 REG16 TS_MMT_MUX_CFG; // 0x16 1874 #define TS_MMT_MUX_CFG_MASK 0x000FUL 1875 #define TS_MMT_MUX_CFG_TS_MUX_TS0 0x0000UL 1876 #define TS_MMT_MUX_CFG_TS_MUX_TS1 0x0001UL 1877 #define TS_MMT_MUX_CFG_TS_MUX_TS2 0x0002UL 1878 #define TS_MMT_MUX_CFG_TS_MUX_TSO 0x0006UL 1879 REG16 dummy1[0x20-0x17]; // 0x17~0x1F 1880 1881 REG32 FileIn_Dmar_LBnd; // 0x20 1882 #define TS_FILEIN_DMAR_LBND_MASK 0x0FFFFFFFUL 1883 1884 REG32 FileIn_Dmar_UBnd; // 0x22 1885 #define TS_FILEIN_DMAR_UBND_MASK 0x0FFFFFFFUL 1886 1887 REG32 MMFileIn0_Dmar_LBnd; // 0x24 1888 #define TS_MMFILEIN0_DMAR_LBND_MASK 0x0FFFFFFFUL 1889 1890 REG32 MMFileIn0_Dmar_UBnd; // 0x26 1891 #define TS_MMFILEIN0_DMAR_UBND_MASK 0x0FFFFFFFUL 1892 1893 REG32 MMFileIn1_Dmar_LBnd; // 0x28 1894 #define TS_MMFILEIN1_DMAR_LBND_MASK 0x0FFFFFFFUL 1895 1896 REG32 MMFileIn1_Dmar_UBnd; // 0x2A 1897 #define TS_MMFILEIN1_DMAR_UBND_MASK 0x0FFFFFFFUL 1898 1899 REG32 Orz_Dmar_LBnd; // 0x2C 1900 #define TS_ORZ_DMAR_LBND_MASK 0x0FFFFFFFUL 1901 1902 REG32 Orz_Dmar_UBnd; // 0x2E 1903 #define TS_ORZ_DMAR_UBND_MASK 0x0FFFFFFFUL 1904 1905 REG32 VQTX0_Dmar_LBnd; // 0x30 1906 #define TS_VQTX0_DMAR_LBND_MASK 0x0FFFFFFFUL 1907 1908 REG32 VQTX0_Dmar_UBnd; // 0x32 1909 #define TS_VQTX0_DMAR_UBND_MASK 0x0FFFFFFFUL 1910 1911 REG32 VQTX1_Dmar_LBnd; // 0x34 1912 #define TS_VQTX1_DMAR_LBND_MASK 0x0FFFFFFFUL 1913 1914 REG32 VQTX1_Dmar_UBnd; // 0x36 1915 #define TS_VQTX1_DMAR_UBND_MASK 0x0FFFFFFFUL 1916 1917 REG32 VQTX2_Dmar_LBnd; // 0x38 1918 #define TS_VQTX2_DMAR_LBND_MASK 0x0FFFFFFFUL 1919 1920 REG16 dummy_3A_3F[6]; // 0x3A~0x3F 1921 1922 REG32 VQTX2_Dmar_UBnd; // 0x40 1923 #define TS_VQTX2_DMAR_UBND_MASK 0x0FFFFFFFUL 1924 1925 REG32 VQTX3_Dmar_LBnd; // 0x42 1926 #define TS_VQTX3_DMAR_LBND_MASK 0x0FFFFFFFUL 1927 1928 REG32 VQTX3_Dmar_UBnd; // 0x44 1929 #define TS_VQTX3_DMAR_UBND_MASK 0x0FFFFFFFUL 1930 1931 REG32 VQRX_Dmar_LBnd; // 0x46 1932 #define TS_VQRX_DMAR_LBND_MASK 0x0FFFFFFFUL 1933 1934 REG32 VQRX_Dmar_UBnd; // 0x48 1935 #define TS_VQRX_DMAR_UBND_MASK 0x0FFFFFFFUL 1936 1937 REG32 Fiq0_Dmar_LBnd; // 0x4A 1938 #define TS_Fiq0_DMAR_LBND_MASK 0x0FFFFFFFUL 1939 1940 REG32 Fiq0_Dmar_UBnd; // 0x4C 1941 #define TS_Fiq0_DMAR_UBND_MASK 0x0FFFFFFFUL 1942 1943 REG32 Fiq1_Dmar_LBnd; // 0x4E 1944 #define TS_Fiq1_DMAR_LBND_MASK 0x0FFFFFFFUL 1945 1946 REG32 Fiq1_Dmar_UBnd; // 0x50 1947 #define TS_Fiq1_DMAR_UBND_MASK 0x0FFFFFFFUL 1948 1949 REG16 dummy2[0x60-0x52]; // 0x52~0x5F 1950 1951 REG16 Dma_Ns_Cfg; // 0x60 1952 #define TS_DMA_NS_CTRL_FILEIN 0x0001UL 1953 #define TS_DMA_NS_CTRL_MMFI0 0x0002UL 1954 #define TS_DMA_NS_CTRL_MMFI1 0x0004UL 1955 #define TS_DMA_NS_CTRL_PVR1 0x0008UL 1956 #define TS_DMA_NS_CTRL_PVR2 0x0010UL 1957 #define TS_DMA_NS_CTRL_VQ 0x0020UL 1958 #define TS_DMA_NS_CTRL_ORZ 0x0040UL 1959 #define TS_DMA_NS_CTRL_SEC 0x0080UL 1960 #define TS_DMA_NS_CTRL_FIQ0 0x0100UL 1961 #define TS_DMA_NS_CTRL_FIQ1 0x0200UL 1962 1963 REG16 Dma_Be_Cfg; // 0x61 1964 #define TS_DMA_BE_CTRL_FILEIN 0x0001UL 1965 #define TS_DMA_BE_CTRL_MMFI0 0x0002UL 1966 #define TS_DMA_BE_CTRL_MMFI1 0x0004UL 1967 #define TS_DMA_BE_CTRL_PVR1 0x0008UL 1968 #define TS_DMA_BE_CTRL_PVR2 0x0010UL 1969 #define TS_DMA_BE_CTRL_VQ 0x0020UL 1970 #define TS_DMA_BE_CTRL_ORZ 0x0040UL 1971 #define TS_DMA_BE_CTRL_SEC 0x0080UL 1972 #define TS_DMA_BE_CTRL_FIQ0 0x0100UL 1973 #define TS_DMA_BE_CTRL_FIQ1 0x0200UL 1974 1975 REG16 MIU_NsUseTee_Cfg; // 0x62 1976 #define TS_MIU_NS_USE_TEE_WP_RP_FILEIN 0x0001UL 1977 #define TS_MIU_NS_USE_TEE_WP_RP_MMFI0 0x0002UL 1978 #define TS_MIU_NS_USE_TEE_WP_RP_MMFI1 0x0004UL 1979 1980 REG32 INIT_TIMESTAMP_FILE; // 0x63 1981 REG32 INIT_TIMESTAMP_MMFI0; // 0x65 1982 REG32 INIT_TIMESTAMP_MMFI1; // 0x67 1983 1984 }REG_Ctrl5; 1985 1986 typedef struct _REG_Ctrl6 1987 { 1988 REG32 PCR64_3_L; // 0x00 1989 REG32 PCR64_3_H; // 0x02 1990 REG32 PCR64_4_L; // 0x04 1991 REG32 PCR64_4_H; // 0x06 1992 }REG_Ctrl6; 1993 1994 // TSP: ts sample part 1995 typedef struct _REG_TS_Sample 1996 { 1997 REG16 TS0_Clk_Sample; // 0x00 1998 #define TS0_PHASE_ADJUST_COUNT_MASK 0x001FUL 1999 #define TS0_PHASE_ADJUST_EN 0x0020UL 2000 #define TS0_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2001 2002 REG16 TS1_Clk_Sample; // 0x01 2003 #define TS1_PHASE_ADJUST_COUNT_MASK 0x001FUL 2004 #define TS1_PHASE_ADJUST_EN 0x0020UL 2005 #define TS1_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2006 2007 REG16 TS2_Clk_Sample; // 0x02 2008 #define TS2_PHASE_ADJUST_COUNT_MASK 0x001FUL 2009 #define TS2_PHASE_ADJUST_EN 0x0020UL 2010 #define TS2_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2011 2012 REG16 TS3_Clk_Sample; // 0x03 2013 #define TS3_PHASE_ADJUST_COUNT_MASK 0x001FUL 2014 #define TS3_PHASE_ADJUST_EN 0x0020UL 2015 #define TS3_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2016 2017 REG16 TS4_Clk_Sample; // 0x04 2018 #define TS4_PHASE_ADJUST_COUNT_MASK 0x001FUL 2019 #define TS4_PHASE_ADJUST_EN 0x0020UL 2020 #define TS4_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2021 2022 REG16 TS5_Clk_Sample; // 0x05 2023 #define TS5_PHASE_ADJUST_COUNT_MASK 0x001FUL 2024 #define TS5_PHASE_ADJUST_EN 0x0020UL 2025 #define TS5_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2026 2027 REG16 TsSample_Reserved0[0x10-0x6]; // 0x06 - 0x0F 2028 2029 REG16 TSO_Clk_Sample; // 0x10 2030 #define TSO_PHASE_ADJUST_COUNT_MASK 0x001FUL 2031 #define TSO_PHASE_ADJUST_EN 0x0020UL 2032 #define TSO_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2033 #define TSO_CLK_INVERT 0x0080UL 2034 2035 REG16 TsSample_Reserved1[0x20-0x11]; // 0x11 - 0x1F 2036 2037 REG16 TS_Out_Clk_Sample; // 0x20 (for old path: TSIF2 out) 2038 #define TS_OUT_PHASE_ADJUST_COUNT_MASK 0x001FUL 2039 #define TS_OUT_PHASE_ADJUST_EN 0x0020UL 2040 #define TS_OUT_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2041 #define TS_OUT_CLK_INVERT 0x0080UL 2042 2043 REG16 S2P_Out_Clk_Sample; // 0x21 2044 #define S2P_PHASE_ADJUST_COUNT_MASK 0x001FUL 2045 #define S2P_PHASE_ADJUST_EN 0x0020UL 2046 #define S2P_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2047 #define S2P_CLK_INVERT 0x0080UL 2048 2049 REG16 S2P1_Out_Clk_Sample; // 0x22 2050 #define S2P1_PHASE_ADJUST_COUNT_MASK 0x001FUL 2051 #define S2P1_PHASE_ADJUST_EN 0x0020UL 2052 #define S2P1_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2053 #define S2P1_CLK_INVERT 0x0080UL 2054 2055 }REG_TS_Sample; 2056 2057 // Firmware status 2058 #define TSP_FW_STATE_MASK 0xFFFF0000UL 2059 #define TSP_FW_STATE_LOAD 0x00010000UL 2060 #define TSP_FW_STATE_ENG_OVRUN 0x00020000UL 2061 #define TSP_FW_STATE_ENG1_OVRUN 0x00040000UL //[reserved] 2062 #define TSP_FW_STATE_IC_ENABLE 0x01000000UL 2063 #define TSP_FW_STATE_DC_ENABLE 0x02000000UL 2064 #define TSP_FW_STATE_IS_ENABLE 0x04000000UL 2065 #define TSP_FW_STATE_DS_ENABLE 0x08000000UL 2066 2067 // TSP AEON specific IP address 2068 #define OPENRISC_IP_1_ADDR 0x00200000UL 2069 #define OPENRISC_IP_1_SIZE 0x00020000UL 2070 #define OPENRISC_IP_2_ADDR 0x90000000UL 2071 #define OPENRISC_IP_2_SIZE 0x00010000UL 2072 #define OPENRISC_IP_3_ADDR 0x40080000UL 2073 #define OPENRISC_IP_3_SIZE 0x00020000UL 2074 #define OPENRISC_QMEM_ADDR 0x00000000UL 2075 #define OPENRISC_QMEM_SIZE 0x00003000UL 2076 #endif // _TSP_REG_H_ 2077