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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regAESDMA.h 98 // Description: AESDMA Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _AESDMA_REG_MCU_H_ 103 #define _AESDMA_REG_MCU_H_ 104 105 106 //-------------------------------------------------------------------------------------------------- 107 // Abbreviation 108 //-------------------------------------------------------------------------------------------------- 109 // Addr Address 110 // Buf Buffer 111 // Clr Clear 112 // CmdQ Command queue 113 // Cnt Count 114 // Ctrl Control 115 // Flt Filter 116 // Hw Hardware 117 // Int Interrupt 118 // Len Length 119 // Ovfw Overflow 120 // Pkt Packet 121 // Rec Record 122 // Recv Receive 123 // Rmn Remain 124 // Reg Register 125 // Req Request 126 // Rst Reset 127 // Scmb Scramble 128 // Sec Section 129 // Stat Status 130 // Sw Software 131 // Ts Transport Stream 132 133 134 //-------------------------------------------------------------------------------------------------- 135 // Global Definition 136 //-------------------------------------------------------------------------------------------------- 137 138 139 //-------------------------------------------------------------------------------------------------- 140 // Compliation Option 141 //-------------------------------------------------------------------------------------------------- 142 143 144 //------------------------------------------------------------------------------------------------- 145 // Harware Capability 146 //------------------------------------------------------------------------------------------------- 147 148 149 //------------------------------------------------------------------------------------------------- 150 // Type and Structure 151 //------------------------------------------------------------------------------------------------- 152 #if (defined(CONFIG_NUTTX) || defined(CONFIG_OPTEE)) 153 #define REG_AESDMACTRL_BASE 0x27B40UL //(0x13D00/2 + 0x50) * 4 154 #define REG_SHARNGCTRL_BASE 0x27A00UL //(0x13D00/2 + 0x0) * 4 155 #define AESDMS_SECURED_BANK_EN 1 156 #else 157 #define REG_AESDMACTRL_BASE 0x47940UL //(0x23C00/2 + 0x50) * 4 158 #define REG_SHARNGCTRL_BASE 0x47800UL //(0x23C00/2 + 0x0) * 4 159 #define AESDMS_SECURED_BANK_EN 0 160 #endif //#if (defined(CONFIG_NUTTX) || defined(CONFIG_OPTEE)) 161 162 #define REG_DMASECURE_CTRL_BASE 0x27A00UL //(0x13D00/2 + 0x00) * 4 163 #define REG_DMASECURE_BASE 0x27B40UL //(0x13D00/2 + 0x50) * 4 164 #define REG_AESDMACLK_BASE 0x1460UL //(0x0A00/2 + 0x18) * 4 165 //#define REG_AESDMAMBX_BASE 0x17F8 //(0x0B00/2 + 0x7F) * 4 166 #define REG_AESDMAMBX_BASE 0x7B84UL //(0x3D00/2 + 0x61) * 4 167 #define REG_PARSERCTRL_BASE 0x45800UL //(0x22C00/2 + 0x00) * 4 168 #define REG_CIPHERCTRL_BASE 0x45840UL //(0x22C00/2 + 0x10) * 4 169 #define REG_AESDMAEXT_BASE 0x45980UL //(0x22C00/2 + 0x60) * 4 170 #define REG_TZPC_NONPM_BASE 0x47200UL //(0x23900/2 + 0x00) * 4 171 #define REG_AES_DSCMB6_BASE 0xE7A00UL //(0x73D00/2 + 0x00) * 4 172 #define REG_AES_DSCMB7_BASE 0xE7B00UL //(0x73D00/2 + 0x40) * 4 173 174 175 //Used for Random Number Gen, Manhattan only 176 #define REG_ANA_MISC_BASE 0x21840UL //(0x10C00/2 + 0x10) * 4 177 178 #define RSA_E_BASE_ADDR (0x00UL) 179 #define RSA_N_BASE_ADDR (0x40UL) 180 #define RSA_A_BASE_ADDR (0x80UL) 181 #define RSA_Z_BASE_ADDR (0xC0UL) 182 #define REG_HDCP22_BASE 0xE74C0UL //(0x73A00/2 + 0x30) * 4 183 #define REG_HDCP22_SEK 0xE2538UL //(0x71200/2 + 0x4E) * 4 184 #define REG_HDCP14_BASE 0xE2438UL //(0x71200 + 0x1C) * 2 185 186 typedef struct _REG32 187 { 188 volatile MS_U16 L; 189 volatile MS_U16 empty_L; 190 volatile MS_U16 H; 191 volatile MS_U16 empty_H; 192 } REG32; 193 194 typedef struct _REG_CipherKey 195 { 196 REG32 Key_L; 197 REG32 Key_H; 198 } REG_CipherKey; 199 200 typedef struct _REG_InitVector 201 { 202 REG32 IV_L; 203 REG32 IV_H; 204 } REG_InitVector; 205 206 typedef struct _REG_AESDMACtrl 207 { 208 REG32 Dma_Ctrl; //0x50 209 #define AESDMA_CTRL_FILEIN_START 0x00000100UL 210 #define AESDMA_CTRL_FILEOUT_START 0x00000001UL 211 #define AESDMA_CTRL_SW_RST 0x00000080UL 212 #define AESDMA_CTRL_BURST_LENGTH 0x00001000UL 213 214 #define AESDMA_ENG_PS_RELEASE 0x00010000UL 215 #define AESDMA_ENG_PS_IN_EN 0x00100000UL 216 #define AESDMA_ENG_PS_OUT_EN 0x00200000UL 217 #define AESDMA_ENG_AES_EN 0x01000000UL 218 #define AESDMA_ENG_DES_EN 0x00040000UL 219 #define AESDMA_ENG_TDES_EN 0x00080000UL 220 #define AESDMA_ENG_DESCRYPT 0x02000000UL // 0:encrypt, 1:decrypt 221 #define AESDMA_ENG_CTR_MODE 0x10000000UL 222 #define AESDMA_ENG_CBC_MODE 0x20000000UL 223 #define AESDMA_ENG_CTS_CBC_MODE 0x40000000UL 224 #define AESDMA_ENG_CTS_ECB_MODE 0x00000002UL 225 #define AESDMA_ECO_FIX_LAST_BYTE 0x80000000UL // when (output address + length)/8=1 the last byte maybe no output 226 227 REG32 Dma_Filein_Addr; //0x52 228 REG32 Dma_Filein_Num; //0x54 229 REG32 Dma_Fileout_SAddr; //0x56 230 REG32 Dma_Fileout_EAddr; //0x58 231 REG32 Dma_PS_Pattern; //0x5a 232 REG32 Dma_PS_Pattern_Mask; //0x5c 233 #define AESDMA_CTR_IV_LSB64 0x01000000UL //0X5d[8]: reg_ctr_iv_lsb64 234 REG32 Dma_Ctrl2; //0x5e 235 #define AESDMA_DMA_USE_TDES_EN 0x00000100UL // DES/TDES path switch 236 #define AESDMA_CTRL_BANK_R_H 0x00002000UL 237 #define AESDMA_CTRL_BANK_W_H 0x00004000UL 238 #define AESDMA_CTRL_BANK_R 0x00000010UL 239 #define AESDMA_CTRL_BANK_W 0x00000020UL 240 #define AESDMA_INT_EN 0x00000080UL 241 #if AESDMS_SECURED_BANK_EN 242 #define AESDMA_USE_SECRET_KEY 0x00200000UL //0x79[6:5]=01, Enable Efuse Key1 243 #define AESDMA_USE_SECRET_KEY2 0x00400000UL //0x79[6:5]=10, Enable Efuse Key2 244 #else 245 #define AESDMA_USE_SECRET_KEY 0x00001000UL //0x5E[12], Enable Efuse Key1 246 #define AESDMA_USE_SECRET_KEY2 0x00001200UL //0x5E[9]+0x5E[12], Enable Efuse Key2 247 #endif 248 #define AESDMA_WADR_ERR_CLR 0x00000001UL 249 250 REG_CipherKey Dma_CipherKey_L; //0x60 251 REG_CipherKey Dma_CipherKey_H; //0x64 252 REG_InitVector Dma_InitVector_L; //0x68 253 REG_InitVector Dma_InitVector_H; //0x6C 254 REG32 Dma_Matched_Btyecnt; //0x70 255 REG32 Dma_Matched_Pat; //0x72 256 #define AESDMA_GEN_INTERNALKEY 0x00000001UL 257 #define AESDMA_GEN_INTERNALKEY2 0x00000002UL 258 #define AESDMA_HWKEY_EN 0x00000020UL 259 #define AESDMA_HWKEY2_EN 0x00000040UL 260 REG32 Dma_Err_Wadr; //0x74 261 REG32 Dma_Eng3_Ctrl; //0x76 262 #define AESDMA_ENG_SPEEDUP 0x03BF0000UL 263 REG32 Dma_Ctrl3_Secure; //0x78 264 REG32 _xbf808fd8[2]; //0x7a~0x7c 265 REG32 Dma_PVR_Status; //0x7e 266 #define AESDMA_IS_FINISHED 0x00010000UL 267 /* 268 #define AESDMA_PS_DONE 0x00000001 269 #define AESDMA_PS_STOP 0x00000002 270 #define AESDMA_DMA_DONE 0x00010000 271 #define AESDMA_DMA_PAUSE 0x00020000 272 #define AESDMA_STATES_GROUP (AESDMA_PS_DONE | \ 273 AESDMA_PS_STOP | \ 274 AESDMA_DMA_DONE | \ 275 AESDMA_DMA_PAUSE ) 276 */ 277 }REG_AESDMACtrl; 278 279 #define DmaCtrlSet (AESDMA_ENG_AES_EN | \ 280 AESDMA_ENG_DES_EN | \ 281 AESDMA_ENG_TDES_EN | \ 282 AESDMA_ENG_DESCRYPT | \ 283 AESDMA_ENG_CTR_MODE | \ 284 AESDMA_ENG_CBC_MODE | \ 285 AESDMA_ENG_CTS_CBC_MODE | \ 286 AESDMA_ENG_CTS_ECB_MODE) 287 288 typedef struct _REG_SHARNGCtrl 289 { 290 REG32 Rng_Ctrl; //0x00 291 #define SHARNG_CTRL_RNG_SW_RST 0x00000080UL 292 #define MOBF_IN_MIU_READ_EN 0x00010000UL 293 #define MOBF_IN_MIU_WRITE_EN 0x00020000UL 294 #define AES_FILE_IN_MIU_NS 0x00100000UL 295 #define AES_FILE_OUT_MIU_NS 0x00200000UL 296 #define MOBF_ONEWAY_EN 0x01000000UL 297 298 #define SECRET_KEY_IN_NORMAL_BANK 0x08000000UL 299 300 301 REG32 Rng_Out; //0x02 302 REG32 MOBF_KeyR; //0x04 303 REG32 MOBF_KeyW; //0x06 304 REG32 Sha_Ctrl; //0x08 305 #define SHARNG_CTRL_SHA_FIRE_ONCE 0x00000001UL 306 #define SHARNG_CTRL_SHA_CLR 0x00000040UL 307 #define SHARNG_CTRL_SHA_RST 0x00000080UL 308 #define SHARNG_CTRL_SHA_INT 0x00000100UL 309 #define SHARNG_CTRL_SHA_SEL_SHA256 0x00000200UL 310 #define SHARNG_CTRL_SHA_MSG_INVERSE 0x00040000UL 311 #define SHARNG_CTRL_SHA_MSG_BLOCK_NUM 0x00010000UL /* Always be 1 */ 312 #define SHARNG_CTRL_SPEED_MODE_N 0x00000010UL 313 #define SHARNG_CTRL_REMOVE_SCATTER_GATHER 0x00000800UL 314 315 REG32 Sha_Start; //0x0a 316 REG32 Sha_Length; //0x0c 317 REG32 Sha_Status; //0x0e 318 #define SHARNG_CTRL_SHA_BUSY 0x00020000UL 319 #define SHARNG_CTRL_SHA_READY 0x00010000UL 320 321 REG32 Sha_Out[8]; //0x10~0x1E 322 REG32 Rsa_Ind32_Start; //0x20 323 #define RSA_INDIRECT_START 0x00000001UL 324 #define RSA_IND32_CTRL_DIRECTION_WRITE 0x00020000UL 325 #define RSA_IND32_CTRL_ADDR_AUTO_INC 0x00040000UL 326 #define RSA_IND32_CTRL_ACCESS_AUTO_START 0x00080000UL 327 REG32 Rsa_Ind32_Addr; //0x22 328 #define RSA_ADDRESS_MASK 0x0000FFFFUL 329 #define RSA_WDATA_MASK_L 0xFFFF0000UL 330 REG32 Rsa_Ind32_WData; //0x24 331 #define RSA_WDATA_MASK_H 0x0000FFFFUL 332 #define RSA_RDATA_MASK_L 0xFFFF0000UL 333 REG32 Rsa_Ind32_RData; //0x26 334 #define RSA_RDATA_MASK_H 0x0000FFFFUL 335 #define RSA_EXP_START 0x00010000UL 336 #define RSA_INT_CLR 0x00020000UL 337 REG32 Rsa_Ctrl; //0x28 338 #define RSA_CTRL_RSA_RST 0x00000001UL 339 #define RSA_CTRL_SEL_HW_KEY 0x00000002UL 340 #define RSA_CTRL_SEL_PUBLIC_KEY 0x00000004UL 341 #define RSA_CTRL_KEY_LENGTH_MASK 0x00003F00UL 342 #define RSA_STATUS_RSA_BUSY 0x00010000UL 343 #define RSA_STATUS_MASK 0x00FF0000UL 344 }REG_SHARNGCtrl; 345 346 typedef struct _REG_DMASECURECtrl 347 { 348 REG32 Secure_file_st; //0x50 349 //#define AESDMA_SECURE_FILEIN_START 0x00000001 350 REG32 reserved52; //0x52 351 REG32 reserved54; //0x54 352 REG32 reserved56; //0x56 353 REG32 reserved58; //0x58 354 REG32 reserved5a; //0x5a 355 REG32 reserved5c; //0x5c 356 REG32 reserved5e; //0x5e 357 REG_CipherKey Secure_CipherKey_L; //0x60 358 REG_CipherKey Secure_CipherKey_H; //0x64 359 REG_InitVector Secure_InitVector_L; //0x68 360 REG_InitVector Secure_InitVector_H; //0x6C 361 REG32 reserved70; //0x70 362 REG32 reserved72; //0x72 363 REG32 reserved74; //0x74 364 REG32 reserved76; //0x76 365 REG32 Secure_dma3_ctrl; //0x78 366 #define AESDMA_SECURE_PROTECT_S 0x00010000UL 367 #define AESDMA_SECURE_PROTECT_SHA_S 0x00020000UL 368 #define AESDMA_SECURE_PROTECT_RSA_S 0x00040000UL 369 #define AESDMA_USE_SECRET_KEY0 0x00200000UL 370 #define AESDMA_USE_SECRET_KEY1 0x00400000UL 371 REG32 reserved7a; //0x7a 372 REG32 reserved7c; //0x7c 373 REG32 Secure_dma3_status; //0x7e 374 //#define AESDMA_DONE_S 0x00010000 375 }REG_DMASECURECtrl; 376 377 typedef struct _REG_CKG_AESDMA 378 { 379 REG32 Reg_Gate_Clk_AESDMA; //0x18 380 #define AESDMA_CLK_OFF_EN 0x00010000UL //0x19[0] 381 #define AESDMA_CLK_INV 0x00020000UL //0x19[1] 382 #define AESDMA_CLK_172M 0x00000000UL //0x19[3:2] 383 #define AESDMA_CLK_144M 0x00040000UL //0x19[3:2] 384 #define AESDMA_CLK_288M 0x00040000UL //0x19[3:2] 385 #define AESDMA_CLK_108M 0x00080000UL //0x19[3:2] 386 #define AESDMA_CLK_XTAL 0x000C0000UL //0x19[3:2] 387 388 }REG_AESDMAClk; 389 390 typedef struct _REG_MBX_AESDMA 391 { 392 REG32 Reg_Et_Rpd; //0x61 393 #define AESDMA_SEM_USED 0x00000100UL 394 #define AESDMA_CLK_USED 0x00000200UL 395 #define TSP_CLK_USED 0x00000400UL 396 }REG_AESDMAMbx; 397 398 399 typedef struct _REG_PARSERCtrl 400 { 401 REG32 Parser_Ctrl; //0x00 402 #define HDCP20_MODE 0x00000001UL 403 #define PKT192_MODE 0x00000002UL 404 #define AUTO_MODE 0x00000004UL 405 #define TRIGGER_MODE 0x00000008UL 406 #define INIT_TRUST 0x00000010UL 407 #define CLEAR_MODE 0x00000020UL 408 #define REMOVE_SCRMB 0x00000040UL 409 #define INSERT_SCRMB 0x00000080UL 410 #define SCRMB_PATTERN10 0x00000400UL 411 #define SCRMB_PATTERN11 0x00000600UL 412 #define SCRMB_INITVALUE 0x00000600UL 413 #define HW_PARSER_MODE 0x00000100UL 414 #define TS_SCRMB_MASK 0x00000800UL 415 #define TS_MODE 0x00008000UL 416 #define PARSER_PID0_MASK 0x1FFF0000UL 417 REG32 Parser_Pid1; //0x02 418 #define PARSER_PID1_MASK 0x00001FFFUL 419 #define BYPASS_PID 0x00080000UL 420 #define SCRMB_PATTERN10_ADD 0x00200000UL 421 #define SCRMB_PATTERN11_ADD 0x00300000UL 422 #define SCRMB_INITVALUE_ADD 0x00300000UL 423 #define SCRMB_ENABLE_TWO_KEY 0x00400000UL 424 #define ENABLE_LG_PATCH 0x01000000UL 425 REG32 Parser_Status; //0x04 426 427 }REG_PARSERCtrl; 428 429 typedef struct _REG_CIPHERCtrl 430 { 431 REG32 Cipher_Ctrl; //0x00 432 #define CC_CTRL_BY_ACPU 0x00000080UL 433 REG32 Cipher_len; //0x02 434 REG32 Parser_Status; //0x04 435 436 }REG_CIPHERCtrl; 437 438 #define ParserCtrlSet (HDCP20_MODE | \ 439 PKT192_MODE | \ 440 AUTO_MODE | \ 441 TRIGGER_MODE | \ 442 INIT_TRUST | \ 443 CLEAR_MODE | \ 444 HW_PARSER_MODE | \ 445 TS_MODE ) 446 447 typedef struct _REG_AESDMACtrlEx 448 { 449 REG_CipherKey Dma_CipherKey_L; //0x60 450 REG_CipherKey Dma_CipherKey_H; //0x64 451 REG_InitVector Dma_InitVector_L; //0x68 452 REG_InitVector Dma_InitVector_H; //0x6C 453 }REG_AESDMACtrlEx; 454 455 typedef struct _REG_HDCP22Data 456 { 457 REG32 Hdcp22_ContentKey[4]; 458 REG32 Hdcp22_Riv[2]; 459 }REG_HDCP22Data; 460 461 typedef struct _REG_HDCP22SEKCtrl 462 { 463 REG32 SEK; //0x9C 464 #define HDCP_SEK_BIT0 0x00000001 465 }REG_HDCP22SEKCtrl; 466 467 typedef struct _REG_GENERAL_STRUCT 468 { 469 REG32 Reg0001; //0x00 470 REG32 Reg0203; //0x02 471 REG32 Reg0405; //0x04 472 REG32 Reg0607; //0x06 473 REG32 Reg0809; //0x08 474 }REG_GENERAL_STRUCT; 475 476 typedef struct _REG_HDCP14SEKCtrl 477 { 478 REG32 REG_0001; //0x0E 479 #define HDCP14_SEK_BIT0 0x00000001 480 }REG_HDCP14SEKCtrl; 481 482 typedef REG_GENERAL_STRUCT REG_TZPCCtrl; //BANK: 0x1239 483 #define REG_TZPC2NONPM_RNG_SOURCE_EN 0x000F0000UL //0x03[3:0] 484 485 typedef REG_GENERAL_STRUCT REG_SECUREBASECtrl; //BANK: 0x113D 486 #define REG_RNG_EN 0x00000080UL //0x00[7] 487 488 typedef REG_GENERAL_STRUCT REG_ANAMISCBASECtrl; //BANK: 0x110C_10 489 #define REG_MIPSPLL_OCCCLK2_EN 0x02000000UL //0x11[9] 490 491 typedef REG_GENERAL_STRUCT REG_AES_DSCMB6Ctrl; //BANK: 0x173D_0 492 #define AESDMA_DSCRMB6_KSLOT_INDEX_DEFAULT 0x00000201UL 493 #define AESDMA_DSCRMB6_KSLOT_INDEX_USE_INTERNAL_KEY2 0x00000206UL 494 #define AESDMA_DSCRMB3_HW_PASER_EN 0x04000000UL //0x01[10] = 1:DESCRMB3/0:DESCRMB5, [11:10] reg_who_use_hwparser 495 typedef REG_GENERAL_STRUCT REG_AES_DSCMB7Ctrl; //BANK: 0x173D_40 496 #define AESDMA_ISR_CLR 0x00010000UL //0x01[0] 497 498 #endif // #ifndef _AESDMA_REG_MCU_H_ 499