1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regTSP.h 98 // Description: Transport Stream Processor (TSP) Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _TSP_REG_H_ 103 #define _TSP_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 #define TS_PACKET_SIZE 188UL 137 138 139 //-------------------------------------------------------------------------------------------------- 140 // Compliation Option 141 //-------------------------------------------------------------------------------------------------- 142 143 //[CMODEL][FWTSP] 144 // When enable, interrupt will not lost, CModel will block next packet 145 // and FwTSP will block until interrupt status is clear by MIPS. 146 // (For firmware and cmodel only) 147 #define TSP_DBG_SAFE_MODE_ENABLE 0UL 148 149 //------------------------------------------------------------------------------------------------- 150 // Harware Capability 151 //------------------------------------------------------------------------------------------------- 152 #define TSP_PIDFLT_NUM 128UL 153 #define TSP_PVR_IF_NUM 2UL 154 #define TSP_MMFI0_FILTER_NUM 4UL 155 #define TSP_MMFI1_FILTER_NUM 4UL 156 #define TSP_IF_NUM 4UL 157 #define TSP_DEMOD_NUM 2UL 158 #define TSP_VFIFO_NUM 2UL 159 #define TSP_AFIFO_NUM 2UL 160 #define TSP_TS_PAD_NUM 6UL // 4P+2S or 5P 161 #define TSP_VQ_NUM 4UL //VQ0, VQ_file, VQ1, VQ_2 162 #define TSP_VQ_PITCH 208UL 163 #define TSP_CA_ENGINE_NUM 2UL 164 #define TSP_CA_KEY_NUM 8UL 165 #define TSP_CA0_FLT_NUM 128UL 166 #define TSP_CA1_FLT_NUM 128UL 167 #define TSP_CA_FLT_NUM 128UL 168 #define TSP_MERGESTR_MUM 8UL 169 #define TSP_ENGINE_NUM 1UL 170 #define TSP_SECFLT_NUM 128UL 171 #define TSP_PCRFLT_NUM 2UL 172 #define TSP_STC_NUM 2UL 173 174 #ifdef HWPCR_ENABLE 175 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM+TSP_PCRFLT_NUM) 176 #else 177 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM) 178 #endif 179 180 #define TSP_SECBUF_NUM TSP_SECFLT_NUM 181 #define TSP_FILTER_DEPTH 16UL 182 183 #define TSP_WP_SET_NUM 4UL 184 185 #define DSCMB_FLT_START_ID 16UL 186 #define DSCMB_FLT_END_ID 31UL 187 #define DSCMB_FLT_NUM 16UL 188 189 #define DSCMB1_FLT_START_ID 32UL 190 #define DSCMB1_FLT_END_ID 47UL 191 #define DSCMB1_FLT_NUM 16UL 192 193 #define DSCMB_FLT_SHAREKEY_START_ID 48UL 194 #define DSCMB_FLT_SHAREKEY_END_ID 127UL 195 #define DSCMB_FLT_SHAREKEY_NUM 128UL 196 197 #define DSCMB_FLT_SHAREKEY1_START_ID 48UL 198 #define DSCMB_FLT_SHAREKEY1_END_ID 127UL 199 #define DSCMB_FLT_SHAREKEY1_NUM 128UL 200 201 #define TSP_NMATCH_FLTID 17UL 202 203 204 //PAD MUX definition 205 #define TSP_MUX_TS0 0UL 206 #define TSP_MUX_TS1 1UL 207 #define TSP_MUX_TS2 2UL 208 #define TSP_MUX_TS3 3UL 209 #define TSP_MUX_TS4 4UL 210 #define TSP_MUX_TS5 5UL 211 #define TSP_MUX_TSO 6UL 212 #define TSP_MUX_INDEMOD 7UL 213 #define TSP_MUX_TSCB 0xFFUL //not support 214 #define TSP_MUX_NONE 0xFF 215 216 //Clk source definition 217 #define TSP_CLK_DISABLE 0x01UL 218 #define TSP_CLK_INVERSE 0x02UL 219 #define TSP_CLK_TS0 0x00UL 220 #define TSP_CLK_TS1 0x04UL 221 #define TSP_CLK_TS2 0x08UL 222 #define TSP_CLK_TS3 0x0CUL 223 #define TSP_CLK_TS4 0x10UL 224 #define TSP_CLK_TS5 0x14UL 225 #define TSP_CLK_TSOOUT 0x18UL 226 #define TSP_CLK_INDEMOD 0x1CUL 227 #define CLKGEN0_TSP_CLK_MASK 0x1CUL 228 #define TSP_CLK_TSCB 0xFFUL //not support 229 230 //PIDFLT1,2 source definition 231 #define TSP_PIDFLT1_USE_TSIF1 0UL 232 #define TSP_PIDFLT2_USE_TSIF2 1UL 233 #define TSP_PIDFLT1_USE_TSIF_MMFI0 2UL 234 #define TSP_PIDFLT2_USE_TSIF_MMFI1 3UL 235 236 237 #define TSP_FW_DEVICE_ID 0x67UL 238 239 #define STC_SYNTH_DEFAULT 0x28000000UL 240 241 #define DRAM_SIZE (0x80000000UL) 242 #define TSP_FW_BUF_SIZE (0x4000UL) 243 #define TSP_FW_BUF_LOW_BUD 0UL 244 #define TSP_FW_BUF_UP_BUD DRAM_SIZE 245 246 #define TSP_VQ_BUF_LOW_BUD 0UL 247 #define TSP_VQ_BUF_UP_BUD (0xFFFFFFFFUL) 248 249 #define TSP_SEC_BUF_LOW_BUD 0UL 250 #define TSP_SEC_BUF_UP_BUD (0xFFFFFFFFUL) 251 #define TSP_SEC_FLT_DEPTH 32UL 252 #define TSP_FIQ_NUM 0UL 253 254 //QMEM Setting 255 #define _TSP_QMEM_I_MASK 0xffff8000UL //total: 0x4000 256 #define _TSP_QMEM_I_ADDR_HIT 0x00000000UL 257 #define _TSP_QMEM_I_ADDR_MISS 0xffffffffUL 258 #define _TSP_QMEM_D_MASK 0xffff8000UL 259 #define _TSP_QMEM_D_ADDR_HIT 0x00000000UL 260 #define _TSP_QMEM_D_ADDR_MISS 0xffffffffUL 261 #define _TSP_QMEM_SIZE 0x1000UL // 16K bytes, 32bit aligment //0x4000 262 263 //------------------------------------------------------------------------------------------------- 264 // Type and Structure 265 //------------------------------------------------------------------------------------------------- 266 267 // Software 268 #define REG_PIDFLT_L_BASE (0x00210000UL << 1UL) // Fit the size of REG32 269 #define REG_PIDFLT_H_BASE (0x00210800UL << 1UL) // Fit the size of REG32 270 271 #define REG_SECFLT_BASE1 (0x00211000UL << 1UL) // Fix the size of REG32 272 #define REG_SECFLT_BASE2 (0x00215000UL << 1UL) // Fix the size of REG32 273 274 #define REG_CTRL_BASE (0x2A00UL) // 0xBF800000+(1500/2)*4 275 #define REG_CTRL_MMFIBASE (0x39C0UL) // 0xBF800000+(3800/2)*4 (TSP2: debug table), from 0x70 276 #define REG_CTRL_TSP3 (0xC1440UL) // 0xBF800000+(60a20/2)*4 277 #define REG_CTRL_TSP4 (0xC2E00UL) // 0xBF800000+(61700/2)*4 278 #define REG_CTRL_TSP5 (0xC7600UL) // 0xBF800000+(63b00/2)*4 279 #define REG_CTRL_TS_SAMPLE (0x21400UL) // 0xBF800000+(10A00/2)*4 280 281 typedef struct _REG32 282 { 283 volatile MS_U16 L; 284 volatile MS_U16 empty_L; 285 volatile MS_U16 H; 286 volatile MS_U16 empty_H; 287 } REG32; 288 289 typedef struct _REG32_L 290 { 291 volatile MS_U32 data; 292 volatile MS_U32 _resv; 293 } REG32_L; 294 295 typedef struct _REG16 296 { 297 volatile MS_U16 u16data; 298 volatile MS_U16 _null; 299 } REG16; 300 301 typedef REG32 REG_PidFlt; 302 303 //******************** PIDFLT DEFINE START ********************// 304 // PID 305 #define TSP_PIDFLT_PID_MASK 0x00001FFFUL 306 #define TSP_PIDFLT_PID_SHFT 0UL 307 308 // PIDFLT SRC 309 #define TSP_PIDFLT_IN_MASK 0x0000E000UL 310 #define TSP_PIDFLT_IN_NONE 0x00000000UL 311 #define TSP_PIDFLT_IN_PIDFLT0 0x00002000UL 312 #define TSP_PIDFLT_IN_PIDFLT_FILE 0x00004000UL 313 #define TSP_PIDFLT_IN_PIDFLT1 0x00006000UL 314 #define TSP_PIDFLT_IN_PIDFLT2 0x00008000UL 315 #define TSP_PIDFLT_IN_PIDFLT_CB 0UL //not support 316 #define TSP_PIDFLT_IN_SHIFT 13UL 317 318 // Section filter Id (0~128) 319 #define TSP_PIDFLT_SECFLT_MASK 0x000007F0UL // [38:32] secflt id 320 #define TSP_PIDFLT_SECFLT_SHFT 4UL 321 322 // Stream source ID 323 #define TSP_PIDFLT_IN_SRC_MASK 0x0000000FUL // [42:39] stream source id 324 #define TSP_PIDFLT_IN_SRC_SHFT 0UL 325 326 // AF/Sec/Video/V3D/Audio/Audio-second/PVR1/PVR2 327 #define TSP_PIDFLT_OUT_MASK 0xFFE00000UL 328 #define TSP_PIDFLT_OUT_NONE 0x00000000UL 329 #define TSP_PIDFLT_OUT_AFIFO4 0x00200000UL 330 #define TSP_PIDFLT_OUT_AFIFO3 0x00400000UL 331 #define TSP_PIDFLT_OUT_SECFLT_AF 0x01000000UL 332 #define TSP_PIDFLT_OUT_SECFLT 0x02000000UL 333 #define TSP_PIDFLT_OUT_VFIFO 0x04000000UL 334 #define TSP_PIDFLT_OUT_VFIFO3D 0x08000000UL 335 #define TSP_PIDFLT_OUT_AFIFO 0x10000000UL 336 #define TSP_PIDFLT_OUT_AFIFO2 0x20000000UL 337 #define TSP_PIDFLT_OUT_PVR1 0x80000000UL 338 #define TSP_PIDFLT_OUT_PVR2 0x40000000UL 339 340 #define TSP_PIDFLT_SECFLT_NULL 0x7FUL // software usage clean selected section filter 341 //******************** PIDFLT DEFINE END ********************// 342 343 typedef struct _REG_SecFlt 344 { 345 REG32 Ctrl; 346 // SW flag 347 #define TSP_SECFLT_TYPE_MASK 0x01000007UL 348 #define TSP_SECFLT_TYPE_SHFT 0UL 349 #define TSP_SECFLT_TYPE_SEC 0x00000000UL 350 #define TSP_SECFLT_TYPE_PES 0x00000001UL 351 #define TSP_SECFLT_TYPE_PKT 0x00000002UL 352 #define TSP_SECFLT_TYPE_PCR 0x00000003UL 353 #define TSP_SECFLT_TYPE_TTX 0x00000004UL 354 #define TSP_SECFLT_TYPE_VER 0x00000005UL 355 #define TSP_SECFLT_TYPE_EMM 0x00000006UL 356 #define TSP_SECFLT_TYPE_ECM 0x00000007UL 357 #define TSP_SECFLT_TYPE_SEC_NO_PUSI 0x01000000UL 358 359 #define TSP_SECFLT_PCRRST 0x00000010UL // for TSP_SECFLT_TYPE_PCR 360 361 #define TSP_SECFLT_MODE_MASK 0x00000030UL // software implementation 362 #define TSP_SECFLT_MODE_SHFT 4UL 363 #define TSP_SECFLT_MODE_CONTI 0x0UL 364 #define TSP_SECFLT_MODE_ONESHOT 0x1UL 365 #define TSP_SECFLT_MODE_CRCCHK 0x2UL 366 #define TSP_SECFLT_MODE_PESSCMCHK 0x3UL //Only for PES type checking SCMB status 367 368 #define TSP_SECFLT_STATE_MASK 0x000000C0UL // software implementation 369 #define TSP_SECFLT_STATE_SHFT 6UL 370 #define TSP_SECFLT_STATE_OVERFLOW 0x1UL 371 #define TSP_SECFLT_STATE_DISABLE 0x2UL 372 373 REG32 Match[TSP_FILTER_DEPTH/sizeof(MS_U32)]; 374 375 REG32 Mask[TSP_FILTER_DEPTH/sizeof(MS_U32)]; 376 377 REG32 BufStart; 378 #define TSP_SECFLT_BUFSTART_MASK 0xFFFFFFFFUL 379 380 REG32 BufEnd; 381 382 REG32 BufRead; 383 384 REG32 BufWrite; 385 386 REG32 BufCur; 387 388 REG32 RmnReqCnt; 389 #define TSP_SECFLT_OWNER_MASK 0x80000000UL 390 #define TSP_SECFLT_OWNER_SHFT 31UL 391 #define TSP_SECFLT_REQCNT_MASK 0x7FFF0000UL 392 #define TSP_SECFLT_REQCNT_SHFT 16UL 393 #define TSP_SECFLT_RMNCNT_MASK 0x0000FFFFUL 394 #define TSP_SECFLT_RMNCNT_SHFT 0UL 395 396 REG32 CRC32; 397 398 REG32 _x50[16]; // (0x210080-0x210050)/4 399 } REG_SecFlt; 400 401 402 typedef struct _REG_Stc 403 { 404 REG32 ML; 405 REG32_L H32; 406 } REG_Stc; 407 408 typedef struct _REG_Pid 409 { // Index(word) CPU(byte) Default 410 REG_PidFlt Flt[TSP_PIDFLT_NUM]; 411 } REG_Pid; 412 413 typedef struct _REG_Sec 414 { // Index(word) CPU(byte) Default 415 REG_SecFlt Flt[TSP_SECFLT_NUM]; 416 } REG_Sec; 417 418 typedef struct _REG_Ctrl 419 { 420 //---------------------------------------------- 421 // 0xBF802A00 MIPS direct access 422 //---------------------------------------------- 423 // Type Name Index(word) CPU(byte) MIPS(0x1500/2+index)*4 424 REG32 TsRec_Head20; // 0xbf802a00 0x00 425 #define TSP_HW_PVR_BUF_HEAD20_MASK 0xFFFF0000UL 426 #define TSP_HW_PVR_BUF_HEAD20_SHFT 16UL 427 428 REG32 TsRec_Head21_Mid20_Wptr; // 0xbf802a08 0x02 ,wptr & mid share same register 429 #define TSP_HW_PVR_BUF_HEAD21_MASK 0x000007FFUL 430 #define TSP_HW_PVR_BUF_HEAD21_SHFT 0UL 431 #define TSP_HW_PVR_BUF_MID20_MASK 0xFFFF0000UL 432 #define TSP_HW_PVR_BUF_MID20_SHFT 16UL 433 434 REG32 TsRec_Mid21_Tail20; // 0xbf802a10 0x04 435 #define TSP_HW_PVR_BUF_MID21_MASK 0x000007FFUL 436 #define TSP_HW_PVR_BUF_MID21_SHFT 0UL 437 #define TSP_HW_PVR_BUF_TAIL20_MASK 0xFFFF0000UL 438 #define TSP_HW_PVR_BUF_TAIL20_SHFT 16UL 439 440 REG32 TsRec_Tail2_Pcr1; // 0xbf802a18 0x06 441 #define TSP_HW_PVR_BUF_TAIL21_MASK 0x000007FFUL 442 #define TSP_HW_PVR_BUF_TAIL21_SHFT 0UL // PCR64 L16 443 #define TSP_PCR64_L16_MASK 0xFFFF0000UL 444 #define TSP_PCR64_L16_SHFT 16UL 445 446 REG32 Pcr1; // 0xbf802a20 0x08 447 #define TSP_PCR64_MID32_MASK 0xFFFFFFFFUL // PCR64 Middle 64 448 #define TSP_PCR64_MID32_SHFT 0UL 449 450 REG32 Pcr64_H; // 0xbf802a28 0x0a 451 #define TSP_PCR64_H16_MASK 0x0000FFFFUL 452 #define TSP_PCR64_H16_SHFT 0UL 453 #define TSP_MOBF_FILE_INDEX_MASK 0x001F0000UL // MOBF file index 454 #define TSP_MOBF_FILE_INDEX_SHIFT 16UL 455 456 REG16 _xbf202a30; // 0xbf802a30 0x0c 457 458 REG16 SW_Mail_Box0; // 0xbf802a34 0x0d 459 460 REG32 PVR2_Config; // 0xbf802a38 0x0e 461 #define TSP_PVR2_LPCR1_WLD 0x00000001UL 462 #define TSP_PVR2_LPCR1_RLD 0x00000002UL 463 #define TSP_PVR2_STR2MIU_DSWAP 0x00000004UL 464 #define TSP_PVR2_STR2MIU_EN 0x00000008UL 465 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010UL 466 #define TSP_PVR2_STR2MIU_BT_ORDER 0x00000020UL 467 #define TSP_PVR2_STR2MIU_PAUSE 0x00000040UL 468 #define TSP_PVR2_REG_PINGPONG_EN 0x00000080UL 469 #define TSP_PVR2_PVR_ALIGN_EN 0x00000100UL 470 #define TSP_PVR2_DMA_FLUSH_EN 0x00000200UL 471 #define TSP_PVR2_PKT192_EN 0x00000400UL 472 #define TSP_PVR2_BURST_LEN_MASK 0x00001800UL 473 #define TSP_PVR2_BURST_LEN_4 0x00000800UL 474 #define TSP_REC_DATA2_INV 0x00002000UL 475 #define TSP_V_BLOCK_DIS 0x00004000UL 476 #define TSP_V3D_BLOCK_DIS 0x00008000UL 477 #define TSP_AUD_BLOCK_DIS 0x00010000UL 478 #define TSP_AUDB_BLOCK_DIS 0x00020000UL 479 #define TSP_PVR1_BLOCK_DIS 0x00040000UL 480 #define TSP_PVR2_BLOCK_DIS 0x00080000UL 481 #define TSP_TSIF2_ENABLE 0x00100000UL 482 #define TSP_TSIF2_DATASWAP 0x00200000UL 483 #define TSP_TSIF2_SERL 0x00000000UL 484 #define TSP_TSIF2_PARL 0x00400000UL 485 #define TSP_TSIF2_EXTSYNC 0x00800000UL 486 #define TSP_TSIF2_BYPASS 0x01000000UL 487 #define TSP_TEI_SKIP_PKT2 0x02000000UL 488 #define TSP_DIS_LOCKED_PKT_CNT 0x10000000UL 489 #define TSP_CLR_LOCKED_PKT_CNT 0x20000000UL 490 #define TSP_CLR_AV_PKT_CNT 0x40000000UL 491 #define TSP_CLR_PVR_OVERFLOW 0x80000000UL 492 493 REG32 PVR2_LPCR1; // 0xbf802a40 0x10 494 495 #define TSP_STR2MI2_ADDR_MASK 0x07FFFFFFUL 496 REG32 Str2mi_head1_pvr2; // 0xbf802a48 0x12 497 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14 498 REG32 Str2mi_tail1_pvr2; // 0xbf802a58 0x16 499 REG32 Str2mi_head2_pvr2; // 0xbf802a60 0x18 500 REG32 Str2mi_mid2_pvr2; // 0xbf802a68 0x1a, PVR2 mid address & write point 501 REG32 Str2mi_tail2_pvr2; // 0xbf802a70 0x1c 502 REG32 SyncByte2_ChkSize; // 0xbf802a78 0x1e 503 #define TSP_SYNC_BYTE2_MASK 0x000000FFUL 504 #define TSP_PKT_SIZE2_MASK 0x0000FF00UL 505 #define TSP_PKT_SIZE2_SHIFT 8UL 506 #define TSP_PKT_CHK_SIZE2_MASK 0x00FF0000UL 507 #define TSP_PKT_CHK_SIZE2_SHIFT 16UL 508 REG32 Pkt_CacheW0; // 0xbf802a80 0x20 509 510 REG32 Pkt_CacheW1; // 0xbf802a88 0x22 511 512 REG32 Pkt_CacheW2; // 0xbf802a90 0x24 513 514 REG32 Pkt_CacheW3; // 0xbf802a98 0x26 515 516 REG32_L Pkt_CacheIdx; // 0xbf802aa0 0x28 517 518 REG32 Pkt_DMA; // 0xbf802aa8 0x2a 519 #define TSP_SEC_DMAFIL_NUM_MASK 0x000000FFUL 520 #define TSP_SEC_DMAFIL_NUM_SHIFT 0UL 521 #define TSP_SEC_DMASRC_OFFSET_MASK 0x0000FF00UL 522 #define TSP_SEC_DMASRC_OFFSET_SHIFT 8UL 523 #define TSP_SEC_DMASRC_OFFSET_MASK 0x0000FF00UL 524 #define TSP_SEC_DMADES_LEN_MASK 0x00FF0000UL 525 #define TSP_SEC_DMADES_LEN_SHIFT 16UL 526 527 REG32 Hw_Config0; // 0xbf802ab0 0x2c 528 #define TSP_HW_CFG0_DATA_PORT_EN 0x00000001UL 529 #define TSP_HW_CFG0_TSIFO_SERL 0x00000000UL 530 #define TSP_HW_CFG0_TSIF0_PARL 0x00000002UL 531 #define TSP_HW_CFG0_TSIF0_EXTSYNC 0x00000004UL 532 #define TSP_HW_CFG0_TSIF0_TS_BYPASS 0x00000008UL 533 #define TSP_HW_CFG0_TSIF0_VPID_BYPASS 0x00000010UL 534 #define TSP_HW_CFG0_TSIF0_APID_BYPASS 0x00000020UL 535 #define TSP_HW_CFG0_WB_DMA_RESET 0x00000040UL 536 #define TSP_HW_CFG0_TSIF0_APID_B_BYPASS 0x00000080UL 537 #define TSP_HW_CFG0_PACKET_BUF_SIZE_MASK 0x0000FF00UL 538 #define TSP_HW_CFG0_PACKET_BUF_SIZE_SHIFT 8UL 539 #define TSP_HW_CFG0_PACKET_PIDFLT0_SIZE_MASK 0x00FF0000UL 540 #define TSP_HW_CFG0_PACKET_PIDFLT0_SIZE_SHIFT 16UL 541 #define TSP_HW_CFG0_PACKET_CHK_SIZE_MASK 0xFF000000UL 542 #define TSP_HW_CFG0_PACKET_CHK_SIZE_SHFT 24UL 543 544 REG32 TSP_DBG_PORT; // 0xbf802ab8 0x2e 545 #define TSP_DNG_DATA_PORT_MASK 0x00FF0000UL 546 #define TSP_DNG_DATA_PORT_SHIFT 16UL 547 548 REG_Stc Pcr; // 0xbf802ac0 0x30 & 0x32 549 550 REG32 Pkt_Info; // 0xbf802ad0 0x34 551 #define TSP_APID_L_MASK 0x000000FFUL 552 #define TSP_APID_L_SHIFT 0UL 553 #define TSP_APID_H_MASK 0x00001F00UL 554 #define TSP_APID_H_SHIFT 8UL 555 #define TSP_PKT_PID_8_12_CP_MASK 0x001F0000UL 556 #define TSP_PKT_PID_8_12_CP_SHIFT 16UL 557 #define TSP_PKT_PRI_MASK 0x00200000UL 558 #define TSP_PKT_PRI_SHIFT 21UL 559 #define TSP_PKT_PLST_MASK 0x00400000UL 560 #define TSP_PKT_PLST_SHIFT 22UL 561 #define TSP_PKT_ERR 0x00800000UL 562 #define TSP_PKT_ERR_SHIFT 23UL 563 #define TSP_DMAW_NO_HIT_INT 0x0F000000UL 564 #define TSP_DMAW_NO_HIT_INT_SHIFT 24UL 565 566 REG32 Pkt_Info2; // 0xbf802ad8 0x36 567 #define TSP_PKT_INFO_CC_MASK 0x0000000FUL 568 #define TSP_PKT_INFO_CC_SHFT 0UL 569 #define TSP_PKT_INFO_ADPCNTL_MASK 0x00000030UL 570 #define TSP_PKT_INFO_ADPCNTL_SHFT 4UL 571 #define TSP_PKT_INFO_SCMB 0x000000C0UL 572 #define TSP_PKT_INFO_SCMB_SHFT 6UL 573 #define TSP_PKT_PID_0_7_CP_MASK 0x0000FF00UL 574 #define TSP_PKT_PID_0_7_CP_SHIFT 8UL 575 #define TSP_VFIFO3D_STATUS 0x000F0000UL 576 #define TSP_VFIFO3D_STATUS_SHFT 16UL 577 #define TSP_VFIFO_STATUS 0x00F00000UL 578 #define TSP_VFIFO_STATUS_SHFT 20UL 579 #define TSP_AFIFO_STATUS 0x0F000000UL 580 #define TSP_AFIFO_STATUS_SHFT 24UL 581 #define TSP_AFIFOB_STATUS 0xF0000000UL 582 #define TSP_AFIFOB_STATUS_SHFT 28UL 583 584 REG32 SwInt_Stat; // 0xbf802ae0 0x38 585 #define TSP_SWINT_INFO_SEC_MASK 0x000000FFUL 586 #define TSP_SWINT_INFO_SEC_SHFT 0UL 587 #define TSP_SWINT_INFO_ENG_MASK 0x0000FF00UL 588 #define TSP_SWINT_INFO_ENG_SHFT 8UL 589 #define TSP_SWINT_STATUS_CMD_MASK 0x7FFF0000UL 590 #define TSP_SWINT_STATUS_CMD_SHFT 16UL 591 #define TSP_SWINT_STATUS_SEC_RDY 0x0001UL 592 #define TSP_SWINT_STATUS_REQ_RDY 0x0002UL 593 #define TSP_SWINT_STATUS_BUF_OVFLOW 0x0006UL 594 #define TSP_SWINT_STATUS_SEC_CRCERR 0x0007UL 595 #define TSP_SWINT_STATUS_SEC_ERROR 0x0008UL 596 #define TSP_SWINT_STATUS_SYNC_LOST 0x0010UL 597 #define TSP_SWINT_STATUS_PKT_OVRUN 0x0020UL 598 #define TSP_SWINT_STATUS_DEBUG 0x0030UL 599 #define TSP_SWINT_CMD_DMA_PAUSE 0x0100UL 600 #define TSP_SWINT_CMD_DMA_RESUME 0x0200UL 601 #define TSP_SWINT_STATUS_SEC_GROUP 0x000FUL 602 #define TSP_SWINT_STATUS_GROUP 0x00FFUL 603 #define TSP_SWINT_CMD_GROUP 0x7F00UL 604 #define TSP_SWINT_CMD_STC_UPD 0x0400UL 605 #define TSP_SWINT_CTRL_FIRE 0x80000000UL 606 607 REG32 TsDma_Addr; // 0xbf802ae8 0x3a 608 609 REG32 TsDma_Size; // 0xbf802af0 0x3c 610 611 REG32 TsDma_Ctrl_CmdQ; // 0xbf802af8 0x3e 612 613 #define TSP_TSDMA_CTRL_VPES0 0x00000004UL //not used 614 #define TSP_TSDMA_CTRL_APES0 0x00000008UL //not used 615 #define TSP_TSDMA_CTRL_A2PES0 0x00000010UL //not used 616 #define TSP_TSDMA_CTRL_V3DPES0 0x00000020UL //not used 617 618 #define TSP_TSDMA_CTRL_START 0x00000001UL 619 #define TSP_TSDMA_CTRL_DONE 0x00000002UL 620 #define TSP_TSDMA_STAT_ABORT 0x00000080UL 621 #define TSP_CMDQ_CNT_MASK 0x001F0000UL 622 #define TSP_CMDQ_CNT_SHFT 16UL 623 #define TSP_CMDQ_FULL 0x00400000UL 624 #define TSP_CMDQ_EMPTY 0x00800000UL 625 #define TSP_CMDQ_SIZE 16UL 626 #define TSP_CMDQ_WR_LEVEL_MASK 0x03000000UL 627 #define TSP_CMDQ_WR_LEVEL_SHFT 24UL 628 629 REG32 MCU_Cmd; // 0xbf802b00 0x40 630 #define TSP_MCU_CMD_MASK 0xFF000000UL 631 #define TSP_MCU_CMD_NULL 0x00000000UL 632 #define TSP_MCU_CMD_ALIVE 0x01000000UL 633 #define TSP_MCU_CMD_NMATCH 0x02000000UL 634 #define TSP_MCU_CMD_NMATCH_FLT_MASK 0x000000FFUL 635 #define TSP_MCU_CMD_NMATCH_FLT_SHFT 0x00000000UL 636 #define TSP_MCU_CMD_PCR_GET 0x03000000UL 637 #define TSP_MCU_CMD_VER_RESET 0x04000000UL 638 #define TSP_MCU_CMD_VER_RESET_FLT_MASK 0x000000FFUL 639 #define TSP_MCU_CMD_VER_RESET_FLT_SHFT 0x00000000UL 640 #define TSP_MCU_CMD_MEM_HIGH_ADDR 0x05000000UL 641 #define TSP_MCU_CMD_MEM_LOW_ADDR 0x06000000UL 642 #define TSP_MCU_CMD_MEM_ADDR_SHFT 0x00000000UL 643 #define TSP_MCU_CMD_MEM_ADDR_MASK 0x0000FFFFUL 644 #define TSP_MCU_CMD_VERSION_GET 0x07000000UL 645 #define TSP_MCU_CMD_DBG_MEM 0x08000000UL 646 #define TSP_MCU_CMD_DBG_WORD 0x09000000UL 647 #define TSP_MCU_CMD_HWPCR_REG_SET 0x0A000000UL 648 #define TSP_MCU_CMD_SCMSTS_GET 0x0B000000UL 649 #define TSP_MCU_CMD_CTRL_STC_UPDATE 0x0C000000UL 650 #define TSP_MCU_CMD_CTRL_STC1_UPDATE 0x0D000000UL 651 #define TSP_MCU_CMD_CTRL_STC_UPDATE_OPTION_MASK 0x00FF0000UL 652 #define TSP_MCU_CMD_CTRL_STC_UPDATE_ONCE 0x00010000UL 653 #define TSP_MCU_CMD_TEI_COUNT_GET 0x0E000000UL 654 #define TSP_MCU_CMD_TEI_COUNT_SRC_MASK 0x0000FFFFUL 655 #define TSP_MCU_CMD_TEI_COUNT_SRC_LIVE 0x00000000UL 656 #define TSP_MCU_CMD_TEI_COUNT_SRC_FILE 0x00000001UL 657 #define TSP_MCU_CMD_TEI_COUNT_OPTION_MASK 0x00FF0000UL 658 #define TSP_MCU_CMD_TEI_COUNT_OPTION_RESET 0x00800000UL 659 #define TSP_MCU_CMD_DISCONT_COUNT_GET 0x0F000000UL 660 #define TSP_MCU_CMD_DISCONT_COUNT_FLT_MASK 0x0000FFFFUL 661 #define TSP_MCU_CMD_DISCONT_COUNT_OPTION_MASK 0x00FF0000UL 662 #define TSP_MCU_CMD_DISCONT_COUNT_OPTION_RESET 0x00800000UL 663 #define TSP_MCU_CMD_SET_STC_OFFSET 0x10000000UL 664 #define TSP_MCU_CMD_SET_STC_OFFSET_OPTION_MASK 0x00FF0000UL 665 #define TSP_MCU_CMD_SET_STC_OFFSET_OPTION_SHIFT 16UL 666 #define TSP_MCU_CMD_SEL_STC_ENG 0x20000000UL 667 #define TSP_MCU_SEL_STC_ENG_ID_MASK 0x000000FFUL 668 #define TSP_MCU_SEL_STC_ENG_ID_SHIFT 0UL 669 #define TSP_MCU_CMD_SEL_STC_ENG_FLTSRC_MASK 0x0000FF00UL 670 #define TSP_MCU_CMD_SEL_STC_ENG_FLTSRC_SHIFT 8UL 671 672 REG32 Hw_Config2; // 0xbf802b08 0x42 673 #define TSP_HW_CFG2_PACKET_CHK_SIZE1_MASK 0x000000FFUL 674 #define TSP_HW_CFG2_PACKET_CHK_SIZE1_SHFT 0UL 675 #define TSP_HW_CFG2_PACKET_SYNCBYTE1_MASK 0x0000FF00UL 676 #define TSP_HW_CFG2_PACKET_SYNCBYTE1_SHFT 8UL 677 #define TSP_HW_CFG2_PACKET_SIZE1_MASK 0x00FF0000UL 678 #define TSP_HW_CFG2_PACKET_SIZE1_SHFT 16UL 679 #define TSP_HW_CFG2_TSIF1_SERL 0x00000000UL 680 #define TSP_HW_CFG2_TSIF1_PARL 0x01000000UL 681 #define TSP_HW_CFG2_TSIF1_EXTSYNC 0x02000000UL 682 #define TSP_HW_CFG2_PIDFLT1_SOURCE_TSIF_MMFI0 0x20000000UL // Switch source of PIDFLT1 to MMFI0 683 #define TSP_HW_CFG2_PIDFLT2_SOURCE_TSIF_MMFI1 0x40000000UL // Switch source of PIDFLT2 to MMFI1 684 685 REG32 Hw_Config4; // 0xbf802b10 0x44 686 #define TSP_HW_CFG4_PVR_ENABLE 0x00000002UL 687 #define TSP_HW_CFG4_PVR_ENDIAN_BIG 0x00000004UL // 1: record TS to MIU with big endian, 0: record TS to MIU with little endian 688 #define TSP_HW_CFG4_TSIF1_ENABLE 0x00000008UL // 1: enable ts interface 1 and vice versa 689 #define TSP_HW_CFG4_PVR_FLUSH 0x00000010UL // 1: str2mi_wadr <- str2mi_miu_head 690 #define TSP_HW_CFG4_PVRBUF_BYTEORDER_BIG 0x00000020UL // Byte order of 8-byte recoding buffer to MIU. 691 #define TSP_HW_CFG4_PVR_PAUSE 0x00000040UL 692 #define TSP_HW_CFG4_MEMTSDATA_ENDIAN_BIG 0x00000080UL // 32-bit data byte order read from 8x64 FIFO when playing file. 693 #define TSP_HW_CFG4_TSIF0_ENABLE 0x00000100UL // 1: enable ts interface 0 and vice versa 694 #define TSP_VALID_FALLING_DETECT 0x00000200UL // Reset bit count when data valid signal of TS interface is low. 695 #define TSP_SYNC_RISING_DETECT 0x00000400UL // Reset bit count on the rising sync signal of TS interface. 696 #define TSP_HW_CFG4_TS_DATA0_SWAP 0x00000800UL // Set 1 to swap the bit order of TS0 DATA bus 697 #define TSP_HW_CFG4_TS_DATA1_SWAP 0x00001000UL // Set 1 to swap the bit order of TS1 DATA bus 698 #define TSP_HW_TSP2OUTAEON_INT_EN 0x00004000UL // Set 1 to force interrupt to outside AEON 699 #define TSP_HW_HK_INT_FORCE 0x00008000UL // Set 1 to force interrupt to HK_MCU 700 #define TSP_HW_CFG4_BYTE_ADDR_DMA 0x000F0000UL // prevent from byte enable bug, bit1~3 must enable togather 701 #define TSP_HW_CFG4_ALT_TS_SIZE 0x00010000UL // enable TS packets in 204 mode 702 #define TSP_HW_DMA_MODE_MASK 0x00300000UL // Section filter DMA mode, 2'b00: Single.2'b01: Burst 2 bytes.2'b10: Burst 4 bytes.2'b11: Burst 8 bytes. 703 #define TSP_HW_DMA_MODE_SHIFT 20UL 704 #define TSP_HW_CFG4_WSTAT_CH_EN 0x00400000UL 705 #define TSP_HW_CFG4_PS_VID_EN 0x00800000UL // program stream video enable 706 #define TSP_HW_CFG4_PS_AUD_EN 0x01000000UL // program stream audio enable 707 #define TSP_HW_CFG4_PS_AUD2_EN 0x02000000UL // program stream audioB enable 708 #define TSP_HW_CFG4_APES_ERR_RM_EN 0x04000000UL // Set 1 to enable removing APES error packet 709 #define TSP_HW_CFG4_VPES_ERR_RM_EN 0x08000000UL // Set 1 to enable removing VPES error packet 710 #define TSP_HW_CFG4_SEC_ERR_RM_EN 0x10000000UL // Set 1 to enable removing section error packet 711 #define TSP_HW_CFG4_VID_ERR 0x20000000UL // Set 1 to mask the error packet interrupt 712 #define TSP_HW_CFG4_AUD_ERR 0x40000000UL // Set 1 to mask the error packet interrupt 713 #define TSP_HW_CFG4_ISYNC_PATCH_EN 0x80000000UL // Set 1 to enable the patch of internal sync in "tsif" 714 715 REG32 NOEA_PC; // 0xbf802b18 0x46 716 717 REG32 Idr_Ctrl_Addr0; // 0xbf802b20 0x48 718 #define TSP_IDR_START 0x00000001UL 719 #define TSP_IDR_READ 0x00000000UL 720 #define TSP_IDR_WRITE 0x00000002UL 721 #define TSP_IDR_WR_ENDIAN_BIG 0x00000004UL 722 #define TSP_IDR_WR_ADDR_AUTO_INC 0x00000008UL // Set 1 to enable address auto-increment after finishing read/write 723 #define TSP_IDR_WDAT0_TRIG_EN 0x00000010UL // WDAT0_TRIG_EN 724 #define TSP_IDR_MCUWAIT 0x00000020UL 725 #define TSP_IDR_SOFT_RST 0x00000080UL // Set 1 to soft-reset the IND32 module 726 #define TSP_IDR_AUTO_INC_VAL_MASK 0x00000F00UL 727 #define TSP_IDR_AUTO_INC_VAL_SHIFT 8UL 728 #define TSP_IDR_ADDR_MASK0 0xFFFF0000UL 729 #define TSP_IDR_ADDR_SHFT0 16UL 730 731 REG32 Idr_Addr1_Write0; // 0xbf802b28 0x4a 732 #define TSP_IDR_ADDR_MASK1 0x0000FFFFUL 733 #define TSP_IDR_ADDR_SHFT1 0UL 734 #define TSP_IDR_WRITE_MASK0 0xFFFF0000UL 735 #define TSP_IDR_WRITE_SHFT0 16UL 736 737 REG32 Idr_Write1_Read0; // 0xbf802b30 0x4c 738 #define TSP_IDR_WRITE_MASK1 0x0000FFFFUL 739 #define TSP_IDR_WRITE_SHFT1 0UL 740 #define TSP_IDR_READ_MASK0 0xFFFF0000UL 741 #define TSP_IDR_READ_SHFT0 16UL 742 743 REG32 Idr_Read1; // 0xbf802b38 0x4e 744 #define TSP_IDR_READ_MASK1 0x0000FFFFUL 745 #define TSP_IDR_READ_SHFT1 0UL 746 #define TSP_V3D_FIFO_DISCON 0x00100000UL 747 #define TSP_V3D_FIFO_OVERFLOW 0x00200000UL 748 #define TSP_VD_FIFO_DISCON 0x02000000UL 749 #define TSP_VD_FIFO_OVERFLOW 0x08000000UL 750 #define TSP_AUB_FIFO_OVERFLOW 0x10000000UL 751 #define TSP_AU_FIFO_OVERFLOW 0x20000000UL 752 753 // only 25 bits supported in PVR address. 8 bytes address 754 #define TSP_STR2MI2_ADDR_MASK 0x07FFFFFFUL 755 REG32 TsRec_Head; // 0xbf802b40 0x50 756 REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid address & write point 757 REG32 TsRec_Tail; // 0xbf802b50 0x54 758 759 REG16 SW_Mail_Box1; // 0xbf802b58 0x56 760 REG16 SW_Mail_Box2; // 0xbf802b5C 0x57 761 REG32 _xbf802b60; // 0xbf802b60 ~ 0xbf802b64 0x58~0x59 762 763 REG32 reg15b4; // 0xbf802b68 0x5a 764 #define TSP_SEC_DMAW_PROTECT_EN 0x00000001UL 765 #define TSP_PVR1_DAMW_PROTECT_EN 0x00000002UL 766 #define TSP_PVR2_DAMW_PROTECT_EN 0x00000004UL 767 #define TSP_PVR_PID_BYPASS 0x00000008UL // Set 1 to bypass PID in record 768 #define TSP_PVR_PID_BYPASS2 0x00000010UL // Set 1 to bypass PID in record2 769 #define TSP_BD_AUD_EN 0x00000020UL // Set 1 to enable the BD audio stream recognization ( core /extend audio stream) 770 #define TSP_AVFIFO_RD_EN 0x00000080UL // 0: AFIFO and VFIFO read are connected to MVD and MAD, 1: AFIFO and VFIFO read are controlled by registers (0x15B5[2:0]) 771 #define TSP_AVFIFO_RD 0x00000100UL // If AVFIFO_RD_EN is 1, set to 1, then set to 0 would issue a read strobe to AFIFO or VFIFO 772 #define TSP_AVFIFO_SEL_VIDEO 0x00000000UL 773 #define TSP_AVFIFO_SEL_AUDIO 0x00000200UL 774 #define TSP_AVFIFO_SEL_AUDIOB 0x00000400UL 775 #define TSP_AVFIFO_SEL_V3D 0x00000600UL 776 #define TSP_PVR_INVERT 0x00001000UL // Set 1 to enable data payload invert for PVR record 777 #define TSP_PLY_FILE_INV_EN 0x00002000UL // Set 1 to enable data payload invert in pidflt0 file path 778 #define TSP_PLY_TS_INV_EN 0x00004000UL // Set 1 to enable data payload invert in pidflt0 TS path 779 #define TSP_FILEIN_BYTETIMER_ENABLE 0x00008000UL // Set 1 to enable byte timer in ts_if0 TS path 780 #define TSP_PVR1_PINGPONG 0x00010000UL // Set 1 to enable MIU addresses with pinpon mode 781 #define TSP_TEI_SKIPE_PKT_PID0 0x00040000UL // Set 1 to skip error packets in pidflt0 TS path 782 #define TSP_TEI_SKIPE_PKT_FILE 0x00080000UL // Set 1 to skip error packets in pidflt0 file path 783 #define TSP_TEI_SKIPE_PKT_PID1 0x00100000UL // Set 1 to skip error packets in pidflt1 TS path 784 #define TSP_DUP_PKT_SKIP 0x00400000UL 785 #define TSP_64bit_PCR2_ld 0x00800000UL // Set 1 to load CNT_64B_2 (the second STC) 786 #define TSP_cnt_33b_ld 0x01000000UL // Set 1 to load cnt_33b 787 #define TSP_FORCE_SYNCBYTE 0x02000000UL // Set 1 to force sync byte (8'h47) in ts_if0 and ts_if1 path. 788 #define TSP_SERIAL_EXT_SYNC_LT 0x04000000UL // Set 1 to detect serial-in sync without 8-cycle mode 789 #define TSP_BURST_LEN_MASK 0x18000000UL // 00,01: burst length = 4; 10,11: burst length = 1 790 #define TSP_BURST_LEN_4 0x08000000UL 791 #define TSP_BURST_LEN_SHIFT 27UL 792 #define TSP_MATCH_PID_SRC_MASK 0x60000000UL // Select the source of pid filter number with hit pid and match pid number with scramble information, 00 : from pkt_demux0, 01 : from pkt_demux_file, 10 : from pkt_demux1, 11 : from pkt_demux2 793 #define TSP_MATCH_PID_SRC_SHIFT 29UL 794 #define TSP_MATCH_PID_SRC_PKTDMX0 0UL 795 #define TSP_MATCH_PID_SRC_PKTDMXFL 1UL 796 #define TSP_MATCH_PID_SRC_PKTDMX1 2UL 797 #define TSP_MATCH_PID_SRC_PKTDMX2 3UL 798 #define TSP_MATCH_PID_LD 0x80000000UL 799 800 REG32 TSP_MATCH_PID_NUM; // 0xbf802b70 0x5c 801 802 REG32 TSP_IWB_WAIT; // 0xbf802b78 0x5e // Wait count settings for IWB when TSP CPU i-cache is enabled. 803 804 REG32 Cpu_Base; // 0xbf802b80 0x60 805 #define TSP_CPU_BASE_ADDR_MASK 0x01FFFFFFUL 806 807 REG32 Qmem_Ibase; // 0xbf802b88 0x62 808 809 REG32 Qmem_Imask; // 0xbf802b90 0x64 810 811 REG32 Qmem_Dbase; // 0xbf802b98 0x66 812 813 REG32 Qmem_Dmask; // 0xbf802ba0 0x68 814 815 REG32 TSP_Debug; // 0xbf802ba8 0x6a 816 #define TSP_DEBUG_MASK 0x00FFFFFFUL 817 818 REG32 _xbf802bb0; // 0xbf802bb0 0x6c 819 820 REG32 TsFileIn_RPtr; // 0xbf802bb8 0x6e 821 822 REG32 TsFileIn_Timer; // 0xbf802bc0 0x70 823 #define TSP_FILE_TIMER_MASK 0x00FFFFFFUL 824 REG32 TsFileIn_Head; // 0xbf802bc8 0x72 825 #define TSP_FILE_ADDR_MASK 0x07FFFFFFUL 826 REG32 TsFileIn_Mid; // 0xbf802bd0 0x74 827 828 REG32 TsFileIn_Tail; // 0xbf802bd8 0x76 829 830 REG32 Dnld_Ctrl; // 0xbf802be0 0x78 831 #define TSP_DNLD_ADDR_MASK 0x0000FFFFUL 832 #define TSP_DNLD_ADDR_SHFT 0UL 833 #define TSP_DNLD_ADDR_ALI_SHIFT 4UL // Bit [11:4] of DMA_RADDR[19:0] 834 #define TSP_DNLD_NUM_MASK 0xFFFF0000UL 835 #define TSP_DNLD_NUM_SHFT 16UL 836 837 REG32 TSP_Ctrl; // 0xbf802be8 0x7a 838 #define TSP_CTRL_CPU_EN 0x00000001UL 839 #define TSP_CTRL_SW_RST 0x00000002UL 840 #define TSP_CTRL_DNLD_START 0x00000004UL 841 #define TSP_CTRL_DNLD_DONE 0x00000008UL // See 0x78 for related information 842 #define TSP_CTRL_TSFILE_EN 0x00000010UL 843 #define TSP_CTRL_R_PRIO 0x00000020UL 844 #define TSP_CTRL_W_PRIO 0x00000040UL 845 #define TSP_CTRL_ICACHE_EN 0x00000100UL 846 #define TSP_CTRL_CPU2MI_R_PRIO 0x00000400UL 847 #define TSP_CTRL_CPU2MI_W_PRIO 0x00000800UL 848 #define TSP_CTRL_I_EL 0x00000000UL 849 #define TSP_CTRL_I_BL 0x00001000UL 850 #define TSP_CTRL_D_EL 0x00000000UL 851 #define TSP_CTRL_D_BL 0x00002000UL 852 #define TSP_CTRL_NOEA_QMEM_ACK_DIS 0x00004000UL 853 #define TSP_CTRL_MEM_TS_WORDER 0x00008000UL 854 #define TSP_SYNC_BYTE_MASK 0x00FF0000UL 855 #define TSP_SYNC_BYTE_SHIFT 16UL 856 857 REG32 PKT_CNT; // 0xbf802bf0 0x7c 858 #define TSP_PKT_CNT_MASK 0x000000FFUL 859 #define TSP_DBG_SEL_MASK 0xFFFF0000UL 860 #define TSP_DBG_SEL_SHIFT 16UL 861 862 REG16 HwInt_Stat; // 0xbf802bf8 0x7e 863 #define TSP_HWINT_STATUS_MASK 0xFF00UL // Tsp2hk_int enable bits. 864 #define TSP_HWINT_TSP_PVR_TAIL0_STATUS 0x0100UL 865 #define TSP_HWINT_TSP_PVR_MID0_STATUS 0x0200UL 866 #define TSP_HWINT_TSP_HK_INT_FORCE_STATUS 0x0400UL 867 #define TSP_HWINT_TSP_FILEIN_MID_INT_STATUS 0x0800UL 868 #define TSP_HWINT_TSP_FILEIN_TAIL_INT_STATUS 0x1000UL 869 #define TSP_HWINT_TSP_SW_INT_STATUS 0x2000UL 870 #define TSP_HWINT_TSP_DMA_READ_DONE 0x4000UL 871 #define TSP_HWINT_TSP_AV_PKT_ERR 0x8000UL 872 873 #define TSP_HWINT_HW_PVR1_MASK (TSP_HWINT_TSP_PVR_TAIL0_STATUS | TSP_HWINT_TSP_PVR_MID0_STATUS) 874 #define TSP_HWINT_ALL (TSP_HWINT_HW_PVR1_MASK | TSP_HWINT_TSP_SW_INT_STATUS) 875 876 // 0x7f: TSP_CTRL1: hidden in HwInt_Stat 877 REG16 TSP_Ctrl1; // 0xbf802bfc 0x7f 878 #define TSP_CTRL1_FILEIN_TIMER_ENABLE 0x0001UL 879 #define TSP_CTRL1_TSP_FILE_NON_STOP 0x0002UL //Set 1 to enable TSP file data read without timer check 880 #define TSP_CTRL1_FILEIN_PAUSE 0x0004UL 881 #define TSP_CTRL1_STANDBY 0x0080UL 882 #define TSP_CTRL1_INT2NOEA 0x0100UL 883 #define TSP_CTRL1_INT2NOEA_FORCE 0x0200UL 884 #define TSP_CTRL1_FORCE_XIU_WRDY 0x0400UL 885 #define TSP_CTRL1_CMDQ_RESET 0x0800UL 886 #define TSP_CTRL1_DLEND_EN 0x1000UL // Set 1 to enable little-endian mode in TSP CPU 887 #define TSP_CTRL1_PVR_CMD_QUEUE_ENABLE 0x2000UL 888 #define TSP_CTRL1_DMA_RST 0x8000UL 889 890 //---------------------------------------------- 891 // 0xBF802C00 MIPS direct access 892 //---------------------------------------------- 893 REG32 MCU_Data0; // 0xbf802c00 0x00 894 #define TSP_MCU_DATA_ALIVE TSP_MCU_CMD_ALIVE 895 896 REG32 PVR1_LPcr1; // 0xbf802c08 0x02 897 898 REG32 LPcr2; // 0xbf802c10 0x04 899 900 REG32 reg160C; // 0xbf802c18 0x06 901 #define TSP_PVR1_LPCR1_WLD 0x00000001UL // Set 1 to load LPCR1 value 902 #define TSP_PVR1_LPCR1_RLD 0x00000002UL // Set 1 to read LPCR1 value (Default: 1) 903 #define TSP_LPCR2_WLD 0x00000004UL // Set 1 to load LPCR2 value 904 #define TSP_LPCR2_RLD 0x00000008UL // Set 1 to read LPCR2 value (Default: 1) 905 #define TSP_RECORD192_EN 0x00000010UL // 160C bit(5)enable TS packets with 192 bytes on record mode 906 #define TSP_FILEIN192_EN 0x00000020UL // 160C bit(5)enable TS packets with 192 bytes on file-in mode 907 #define TSP_RVU_TIMESTAMP_EN 0x00000040UL 908 #define TSP_ORZ_DMAW_PROT_EN 0x00000080UL // 160C bit(7) open RISC DMA write protection 909 #define TSP_CLR_PIDFLT_BYTE_CNT 0x00000100UL // Clear pidflt0_file byte counter 910 #define TSP_DOUBLE_BUF_DESC 0x00004000UL // 160d bit(6) remove buffer limitation, Force pinpong buffer to flush 911 #define TSP_TIMESTAMP_RESET 0x00008000UL // 160d bit(7) reset timestamp, reset all file in path 912 #define TSP_VQTX0_BLOCK_DIS 0x00010000UL 913 #define TSP_VQTX1_BLOCK_DIS 0x00020000UL 914 #define TSP_VQTX2_BLOCK_DIS 0x00040000UL 915 #define TSP_VQTX3_BLOCK_DIS 0x00080000UL 916 #define TSP_DIS_MIU_RQ 0x00100000UL // Disable miu R/W request for reset TSP usage 917 #define TSP_RM_DMA_GLITCH 0x00800000UL // Fix sec_dma overflow glitch 918 #define TSP_RESET_VFIFO 0x01000000UL // Reset VFIFO -- ECO Done 919 #define TSP_RESET_AFIFO 0x02000000UL // Reset AFIFO -- ECO Done 920 #define TSP_RESET_GDMA 0x04000000UL // Set 1 to reset GDMA bridge 921 #define TSP_CLR_ALL_FLT_MATCH 0x08000000UL // Set 1 to clean all flt_match in a packet 922 #define TSP_RESET_AFIFO2 0x10000000UL 923 #define TSP_RESET_VFIFO3D 0x20000000UL 924 #define TSP_PVR_WPRI_HIGH 0x20000000UL 925 #define TSP_OPT_ORACESS_TIMING 0x80000000UL 926 927 REG32 PktChkSizeFilein; // 0xbf802c20 0x08 928 #define TSP_PKT_SIZE_MASK 0x000000ffUL 929 #define TSP_PKT192_BLK_DIS_FIN 0x00000100UL // Set 1 to disable file-in timestamp block scheme 930 #define TSP_AV_CLR 0x00000200UL // Clear AV FIFO overflow flag and in/out counter 931 #define TSP_HW_STANDBY_MODE 0x00000400UL // Set 1 to disable all SRAM in TSP for low power mode automatically 932 #define TSP_CNT_34B_DEFF_EN 0x00020000UL // Switch STC DIFF Mode (Output STC+DIFF to MVD and MAD) 933 #define TSP_SYSTIME_MODE_STC64 0x00080000UL // Switch normal STC or STC diff 934 #define TSP_SEC_DMA_BURST_EN 0x00800000UL // ECO bit for section DMA burst mode 935 #define TSP_REMOVE_DUP_VIDEO_PKT 0x02000000UL // Set 1 to remove duplicate video packet 936 #define TSP_REMOVE_DUP_VIDEO3D_PKT 0x04000000UL // Set 1 to remove duplicate video 3D packet 937 #define TSP_REMOVE_DUP_AUDIO_PKT 0x08000000UL // Set 1 to remove duplicate audio packet 938 #define TSP_REMOVE_DUP_AUDIOB_PKT 0x10000000UL // Set 1 to remove duplicate audio description packet 939 940 #define TSP_REMOVE_DUP_AV_PKT (TSP_REMOVE_DUP_VIDEO_PKT | \ 941 TSP_REMOVE_DUP_VIDEO3D_PKT | \ 942 TSP_REMOVE_DUP_AUDIO_PKT | \ 943 TSP_REMOVE_DUP_AUDIOB_PKT ) 944 945 REG32 Dnld_Ctrl2; // 0xbf802c28 0x0a 946 #define TSP_DMA_RADDR_MSB_MASK 0x000000FFUL 947 #define TSP_DMA_RADDR_MSB_SHIFT 0UL 948 //#define TSP_CMQ_WORD_EN 0x00400000UL // Set 1 to access CMDQ related registers in word. 949 //#define TSP_RESET_PVR_MOBF 0x04000000UL 950 //#define TSP_RESET_FILEIN_MOBF 0x08000000UL 951 #define TSP_TSIF0_VPID_3D_BYPASS 0x08000000UL // bypass TS for matched video 3D pid 952 #define TSP_VPID_3D_ERR_RM_EN 0x10000000UL // enable removing v3d err pkt 953 #define TSP_PS_VID3D_EN 0x40000000UL 954 955 REG32 TsPidScmbStatTsin; // 0xbf802c30 0x0c 956 957 REG32 _xbf802c38; // 0xbf802c38 0x0e 958 959 REG32 PCR64_2_L; // 0xbf802c40 0x10 960 961 REG32 PCR64_2_H; // 0xbf802c48 0x12 962 963 #define TSP_DMAW_BND_MASK 0xFFFFFFFFFUL 964 REG32 DMAW_LBND0; // 0xbf802c50 0x14 965 966 REG32 DMAW_UBND0; // 0xbf802c58 0x16 967 968 REG32 DMAW_LBND1; // 0xbf802c60 0x18 969 970 REG32 DMAW_UBND1; // 0xbf802c68 0x1A 971 972 REG32 DMAW_ERR_WADDR_SRC_SEL; // 0xbf802c70 0x1C 973 #define TSP_CLR_NO_HIT_INT 0x00000001UL // set 1 clear all dma write function not hit interrupt 974 #define DMAW_ERR_WADDR_SRC_SEL_MASK 0x0000001EUL 975 #define DMAW_ERR_WADDR_SRC_SEL_SHIFT 1UL 976 #define TSP_PVR1_DWMA_WADDR_ERR 0x0UL 977 #define TSP_SEC_DWMA_WADDR_ERR 0x1UL 978 #define TSP_PVR_CB_DWMA_WADDR_ERR 0x2UL 979 #define TSP_VQTX0_DWMA_WADDR_ERR 0x3UL 980 #define TSP_VQTX1_DWMA_WADDR_ERR 0x4UL 981 #define TSP_ORZ_DWMA_WADDR_ERR 0x5UL 982 #define TSP_VQTX2_DWMA_WADDR_ERR 0x6UL 983 #define TSP_VQTX3_DWMA_WADDR_ERR 0x7UL 984 #define TSP_PVR2_DWMA_WADDR_ERR 0x8UL 985 #define TSP_CLR_SEC_DMAW_OVERFLOW 0x00000040UL 986 #define TSP_APES_B_ERR_RM_EN 0x00000080UL 987 #define TSP_BLK_AF_SCRMB_BIT 0x00000400UL 988 989 REG32 reg163C; // 0xbf802c78 0x1e 990 991 #define TSP_CLR_SRC_MASK 0x00070000UL 992 #define TSP_CLR_SRC_SHIFT 16UL 993 #define TSP_DISCONTI_VD_CLR 0x00080000UL //Set 1 to clear video discontinuity count 994 #define TSP_DISCONTI_V3D_CLR 0x00100000UL //Set 1 to clear v3D discontinuity count 995 #define TSP_DISCONTI_AUD_CLR 0x00200000UL //Set 1 to clear audio discontinuity count 996 #define TSP_DISCONTI_AUDB_CLR 0x00400000UL //Set 1 to clear videoB discontinuity count 997 #define TSL_CLR_SRAM_COLLISION 0x02000000UL 998 #define TSP_TS_OUT_EN 0x04000000UL //set 1 to enable ts_out 999 1000 #define TSP_ALL_VALID_EN 0x08000000UL 1001 #define TSP_PKT130_PUSI_EN 0x10000000UL 1002 #define TSP_PKT130_TEI_EN 0x20000000UL 1003 #define TSP_PKT130_ERR_CLR 0x40000000UL 1004 #define TSP_PKT130_EN 0x80000000UL // file in only 1005 1006 REG32 VQ0_BASE; // 0xbf802c80 0x20 1007 REG32 VQ0_CTRL; // 0xbf802c88 0x22 1008 #define TSP_VQ0_SIZE_208PK_MASK 0x0000FFFFUL 1009 #define TSP_VQ0_SIZE_208PK_SHIFT 0UL 1010 #define TSP_VQ0_WR_THRESHOLD_MASK 0x000F0000UL 1011 #define TSP_VQ0_WR_THRESHOLD_SHIFT 16UL 1012 #define TSP_VQ0_PRIORTY_THRESHOLD_MASK 0x00F00000UL 1013 #define TSP_VQ0_PRIORTY_THRESHOL_SHIFT 20UL 1014 #define TSP_VQ0_FORCE_FIRE_CNT_1K_MASK 0x0F000000UL 1015 #define TSP_VQ0_FORCE_FIRE_CNT_1K_SHIFT 24UL 1016 #define TSP_VQ0_RESET 0x10000000UL 1017 #define TSP_VQ0_OVERFLOW_INT_EN 0x40000000UL // Enable the interrupt for overflow happened on Virtual Queue path 1018 #define TSP_VQ0_CLR_OVERFLOW_INT 0x80000000UL // Clear the interrupt and the overflow flag 1019 1020 REG32 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 1021 #define TSP_REQ_VQ_RX_THRESHOLD_MASKE 0x000E0000UL 1022 #define TSP_REQ_VQ_RX_THRESHOLD_SHIFT 17UL 1023 #define TSP_REQ_VQ_RX_THRESHOLD_LEN1 0x00000000UL 1024 #define TSP_REQ_VQ_RX_THRESHOLD_LEN2 0x00020000UL 1025 #define TSP_REQ_VQ_RX_THRESHOLD_LEN4 0x00040000UL 1026 #define TSP_REQ_VQ_RX_THRESHOLD_LEN8 0x00060000UL 1027 #define TSP_PIDFLT0_OVF_INT_EN 0x00400000UL 1028 #define TSP_PIDFLT0_CLR_OVF_INT 0x00800000UL 1029 #define TSP_PIDFLT0_FILE_OVF_INT_EN 0x01000000UL 1030 #define TSP_PIDFLT0_FILE_CLR_OVF_INT 0x02000000UL 1031 #define TSP_PIDFLT1_OVF_INT_EN 0x04000000UL 1032 #define TSP_PIDFLT1_CLR_OVF_INT 0x08000000UL 1033 #define TSP_PIDFLT2_OVF_INT_EN 0x10000000UL 1034 #define TSP_PIDFLT2_CLR_OVF_INT 0x20000000UL 1035 1036 REG32 MOBF_PVR1_Index; // 0xbf3a2c98 0x26 1037 #define TSP_MOBF_PVR1_INDEX0_MASK 0x0000000FUL 1038 #define TSP_MOBF_PVR1_INDEX0_SHIFT 0UL 1039 #define TSP_MOBF_PVR1_INDEX1_MASK 0x000F0000UL 1040 #define TSP_MOBF_PVR1_INDEX1_SHIFT 16UL 1041 1042 REG32 MOBF_PVR2_Index; // 0xbf3a2cA0 0x28 1043 #define TSP_MOBF_PVR2_INDEX0_MASK 0x0000000FUL 1044 #define TSP_MOBF_PVR2_INDEX0_SHIFT 0UL 1045 #define TSP_MOBF_PVR2_INDEX1_MASK 0x000F0000UL 1046 #define TSP_MOBF_PVR2_INDEX1_SHIFT 16UL 1047 1048 REG32 DMAW_LBND2; // 0xbf802ca8 0x2a 1049 1050 REG32 DMAW_UBND2; // 0xbf802cb0 0x2c 1051 1052 REG32 DMAW_LBND3; // 0xbf802cb8 0x2e //reserved 1053 1054 REG32 DMAW_UBND3; // 0xbf802cc0 0x30 //reserved 1055 1056 REG32 DMAW_LBND4; // 0xbf802cc8 0x32 1057 1058 REG32 DMAW_UBND4; // 0xbf802cd0 0x34 1059 1060 REG32 ORZ_DMAW_LBND; // 0xbf802cd8 0x36 1061 #define TSP_ORZ_DMAW_LBND_MASK 0xffffffffUL 1062 REG32 ORZ_DMAW_UBND; // 0xbf802ce0 0x38 1063 #define TSP_ORZ_DMAW_UBND_MASK 0xffffffffUL 1064 REG32 _xbf802ce8_xbf802cec; // 0xbf802ce8_0xbf802cec 0x3a~0x3b 1065 1066 REG32 HWPCR0_L; // 0xbf802cf0 0x3c 1067 REG32 HWPCR0_H; // 0xbf802cf8 0x3e 1068 1069 REG32 CA_CTRL; // 0xbf802d00 0x40 1070 #define TSP_CA_CTRL_MASK 0xffffffffUL 1071 #define TSP_CA0_CTRL_MASK 0x00007077UL 1072 #define TSP_CA0_INPUT_TSIF0_LIVEIN 0x00000001UL 1073 #define TSP_CA0_INPUT_TSIF0_FILEIN 0x00000002UL 1074 #define TSP_CA0_INPUT_TSIF1 0x00000004UL 1075 #define TSP_CA0_OUTPUT_PKTDMX0_LIVE 0x00000010UL 1076 #define TSP_CA0_OUTPUT_PKTDMX0_FILE 0x00000020UL 1077 #define TSP_CA0_OUTPUT_PKTDMX1 0x00000040UL 1078 #define TSP_CA0_INPUT_TSIF2 0x00001000UL 1079 #define TSP_CA0_OUTPUT_PKTDMX2 0x00002000UL 1080 1081 #define TSP_CA1_CTRL_MASK 0x77300000UL 1082 #define TSP_CA1_INPUT_TSIF2 0x00100000UL 1083 #define TSP_CA1_OUTPUT_PKTDMX2 0x00200000UL 1084 #define TSP_CA1_INPUT_TSIF0_LIVEIN 0x01000000UL 1085 #define TSP_CA1_INPUT_TSIF0_FILEIN 0x02000000UL 1086 #define TSP_CA1_INPUT_TSIF1 0x04000000UL 1087 #define TSP_CA1_OUTPUT_PKTDMX0_LIVE 0x10000000UL 1088 #define TSP_CA1_OUTPUT_PKTDMX0_FILE 0x20000000UL 1089 #define TSP_CA1_OUTPUT_PKTDMX1 0x40000000UL 1090 1091 REG32 REG_ONEWAY; // 0xbf802d08 0x42 1092 #define TSP_ONEWAY_REC_DISABLE 0x00000001UL // Disable PVR 1093 #define TSP_ONEWAY_PVR_PORT 0x00000002UL // Oneway for PVR buffer 1094 #define TSP_ONEWAY_LOAD_FW_PORT 0x00000004UL // Oneway for f/w load address 1095 1096 REG32 HWPCR1_L; // 0xbf802d10 0x44 1097 REG32 HWPCR1_H; // 0xbf802d18 0x46 1098 1099 REG32 _xbf802d20[4]; // 0xbf802d20~0xbf802d3c 0x48~0x4f //LPCR_CB 1100 1101 REG32 FIFO_Src; // 0xbf802d40 0x50 1102 #define TSP_AUD_SRC_MASK 0x00000007UL 1103 #define TSP_AUD_SRC_SHIFT 0UL 1104 #define TSP_SRC_FROM_PKTDMX0 0x00000001UL 1105 #define TSP_SRC_FROM_PKTDMXFL 0x00000002UL 1106 #define TSP_SRC_FROM_PKTDMX1 0x00000003UL 1107 #define TSP_SRC_FROM_PKTDMX2 0x00000004UL 1108 #define TSP_SRC_FROM_MMFI0 0x00000006UL 1109 #define TSP_SRC_FROM_MMFI1 0x00000007UL 1110 #define TSP_AUDB_SRC_MASK 0x00000038UL 1111 #define TSP_AUDB_SRC_SHIFT 3UL 1112 #define TSP_VID_SRC_MASK 0x000001C0UL 1113 #define TSP_VID_SRC_SHIFT 6UL 1114 #define TSP_VID3D_SRC_MASK 0x00000E00UL 1115 #define TSP_VID3D_SRC_SHIFT 9UL 1116 #define TSP_PVR1_SRC_MASK 0x00007000UL 1117 #define TSP_PVR1_SRC_SHIFT 12UL 1118 #define TSP_PVR2_SRC_MASK 0x00038000UL 1119 #define TSP_PVR2_SRC_SHIFT 15UL 1120 #define TSP_PCR0_SRC_MASK 0x001C0000UL 1121 #define TSP_PCR0_SRC_SHIFT 18UL 1122 #define TSP_PCR1_SRC_MASK 0x00E00000UL 1123 #define TSP_PCR1_SRC_SHIFT 21UL 1124 #define TSP_TEI_SKIP_PKT_PCR0 0x01000000UL 1125 #define TSP_PCR0_RESET 0x02000000UL 1126 #define TSP_PCR0_INT_CLR 0x04000000UL 1127 #define TSP_PCR0_READ 0x08000000UL 1128 #define TSP_TEI_SKIP_PKT_PCR1 0x10000000UL 1129 #define TSP_PCR1_RESET 0x20000000UL 1130 #define TSP_PCR1_INT_CLR 0x40000000UL 1131 #define TSP_PCR1_READ 0x80000000UL 1132 1133 REG32 STC_DIFF_BUF; // 0xbf802d48 0x52 1134 1135 REG32 STC_DIFF_BUF_H; // 0xbf802d50 0x54 1136 #define TSP_STC_DIFF_BUF_H_MASK 0x0000007FUL 1137 #define TSP_STC_DIFF_BUF_H_AHIFT 0UL 1138 1139 REG32 VQ1_Base; // 0xbf802d58 0x56 1140 1141 REG32 _rbf802d60; // 0xbf802d60 0x58 1142 1143 REG32 CH_BW_CTRL; // 0xbf802d68 0x5a 1144 #define TSP_CH_BW_WP_LD 0x00000100UL 1145 1146 REG32 VQ1_Config; // 0xbf802d70 0x5C 1147 #define TSP_VQ1_SIZE_208BYTE_MASK 0x0000ffffUL 1148 #define TSP_VQ1_SIZE_208BYTE_SHIFT 0UL 1149 #define TSP_VQ1_WR_THRESHOLD_MASK 0x000F0000UL 1150 #define TSP_VQ1_WR_THRESHOLD_SHIFT 16UL 1151 #define TSP_VQ1_PRI_THRESHOLD_MASK 0x00F00000UL 1152 #define TSP_VQ1_PRI_THRESHOLD_SHIFT 20UL 1153 #define TSP_VQ1_FORCEFIRE_CNT_1K_MASK 0x0F000000UL 1154 #define TSP_VQ1_FORCEFIRE_CNT_1K_SHIFT 24UL 1155 #define TSP_VQ1_RESET 0x10000000UL 1156 #define TSP_VQ1_OVF_INT_EN 0x40000000UL 1157 #define TSP_VQ1_CLR_OVF_INT 0x80000000UL 1158 1159 REG32 VQ2_Base; // 0xbf802d78 0x5E 1160 1161 REG32 _rbf802d80; // 0xbf802d80 0x60 1162 1163 REG32 Bist_Fail; // 0xbf802d88 0x62 1164 #define TSP_BIST_FAIL_STATUS_MASK 0x00FF0000UL 1165 #define TSP_BIST_FAIL_STATUS_SRAM1P192x8_MASK 0x00070000UL 1166 #define TSP_BIST_FAIL_STATUS_SRAM2P512x32w8 0x00080000UL 1167 #define TSP_BIST_FAIL_STATUS_SRAM2P16x128_MASK 0x00600000UL 1168 #define TSP_BIST_FAIL_STATUS_SRAM1P2048x32w8 0x00800000UL 1169 #define TSP_BIST_FAIL_STATUS_SRAM1P1024x32w8 0x01000000UL 1170 #define TSP_BIST_FAIL_STATUS_SRAM1P512x20 0x00200000UL 1171 1172 REG32 VQ2_Config; // 0xbf802d90 0x64 1173 #define TSP_VQ2_SIZE_208BYTE_MASK 0x0000ffffUL 1174 #define TSP_VQ2_SIZE_208BYTE_SHIFT 0UL 1175 #define TSP_VQ2_WR_THRESHOLD_MASK 0x000F0000UL 1176 #define TSP_VQ2_WR_THRESHOLD_SHIFT 16UL 1177 #define TSP_VQ2_PRI_THRESHOLD_MASK 0x00F00000UL 1178 #define TSP_VQ2_PRI_THRESHOLD_SHIFT 20UL 1179 #define TSP_VQ2_FORCEFIRE_CNT_1K_MASK 0x0F000000UL 1180 #define TSP_VQ2_FORCEFIRE_CNT_1K_SHIFT 24UL 1181 #define TSP_VQ2_RESET 0x10000000UL 1182 #define TSP_VQ2_OVF_INT_EN 0x40000000UL 1183 #define TSP_VQ2_CLR_OVF_INT 0x80000000UL 1184 1185 REG32 VQ_STATUS; // 0xbf802d98 0x66 1186 #define TSP_VQ_STATUS_MASK 0xFFFFFFFFUL 1187 #define TSP_VQ_STATUS_SHIFT 0UL 1188 #define TSP_VQ0_STATUS_READ_EVER_FULL 0x00001000UL 1189 #define TSP_VQ0_STATUS_READ_EVER_OVERFLOW 0x00002000UL 1190 #define TSP_VQ0_STATUS_EMPTY 0x00004000UL 1191 #define TSP_VQ0_STATUS_READ_BUSY 0x00008000UL 1192 #define TSP_VQ1_STATUS_READ_EVER_FULL 0x00010000UL 1193 #define TSP_VQ1_STATUS_READ_EVER_OVERFLOW 0x00020000UL 1194 #define TSP_VQ1_STATUS_EMPTY 0x00040000UL 1195 #define TSP_VQ1_STATUS_READ_BUSY 0x00080000UL 1196 #define TSP_VQ2_STATUS_READ_EVER_FULL 0x00100000UL 1197 #define TSP_VQ2_STATUS_READ_EVER_OVERFLOW 0x00200000UL 1198 #define TSP_VQ2_STATUS_EMPTY 0x00400000UL 1199 #define TSP_VQ2_STATUS_READ_BUSY 0x00800000UL 1200 #define TSP_VQ3_STATUS_READ_EVER_FULL 0x01000000UL 1201 #define TSP_VQ3_STATUS_READ_EVER_OVERFLOW 0x02000000UL 1202 #define TSP_VQ3_STATUS_EMPTY 0x04000000UL 1203 #define TSP_VQ3_STATUS_READ_BUSY 0x08000000UL 1204 #define TSP_VQ0_STATUS_TX_OVERFLOW 0x10000000UL 1205 #define TSP_VQ1_STATUS_TX_OVERFLOW 0x20000000UL 1206 #define TSP_VQ2_STATUS_TX_OVERFLOW 0x40000000UL 1207 #define TSP_VQ3_STATUS_TX_OVERFLOW 0x80000000UL 1208 1209 REG32 DM2MI_WAddr_Err; // 0xbf802da0 0x68 , DM2MI_WADDR_ERR0 1210 1211 REG32 ORZ_DMAW_WAddr_Err; // 0xbf802da8 0x6a , ORZ_WADDR_ERR0 1212 1213 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c 1214 #define TSP_HWINT2_EN_MASK 0x00FFUL 1215 #define TSP_HWINT2_EN_SHIFT 0UL 1216 #define TSP_HWINT2_STATUS_MASK 0xFF00UL 1217 #define TSP_HWINT2_STATUS_SHIFT 8UL 1218 #define TSP_HWINT2_PCR1_UPDATE_END 0x0400UL 1219 #define TSP_HWINT2_PCR0_UPDATE_END 0x0800UL 1220 #define TSP_HWINT2_PVRCB_MEET_MID_TAIL 0x1000UL 1221 #define TSP_HWINT2_ALL_DMA_WADDR_NOT_IN_PROCT_Z 0x2000UL 1222 #define TSP_HWINT2_VQ0_VQ1_VQ2_VQ3_OVERFLOW 0x4000UL 1223 #define TSP_HWINT2_PVR2_MID_TAIL_STATUS 0x8000UL 1224 1225 #define TSP_HWINT_HW_PVRCB_MASK TSP_HWINT2_PVRCB_MEET_MID_TAIL 1226 #define TSP_HWINT_HW_PVR2_MASK TSP_HWINT2_PVR2_MID_TAIL_STATUS 1227 #define TSP_HWINT2_ALL (TSP_HWINT_HW_PVRCB_MASK|TSP_HWINT_HW_PVR2_MASK|TSP_HWINT2_PCR0_UPDATE_END|TSP_HWINT2_PCR1_UPDATE_END) 1228 1229 #define TSP_SWINT1_L_SHFT 16UL 1230 #define TSP_SWINT1_L_MASK 0xFFFF0000UL 1231 1232 REG16 SwInt_Stat1_M; 1233 REG32 SwInt_Stat1_H; // 0xbf802dB8 0x6e 1234 #define TSP_SWINT1_H_SHFT 0UL 1235 #define TSP_SWINT1_H_MASK 0x0000FFFFUL 1236 1237 REG32 TimeStamp_FileIn; // 0xbf802dC0 0x70 1238 1239 REG32 HW2_Config3; // 0xbf802dC0 0x72 1240 #define TSP_WADDR_ERR_SRC_SEL_MASK 0x00000006UL 1241 #define TSP_WADDR_ERR_SRC_SEL_SHIFT 1UL 1242 #define TSP_WADDR_ERR_SRC_PVR 0x00000000UL 1243 #define TSP_WADDR_ERR_SRC_VQ 0x00000002UL 1244 #define TSP_WADDR_ERR_SRC_SEC_CB 0x00000004UL 1245 #define TSP_RM_OVF_GLITCH 0x00000008UL 1246 #define TSP_FILEIN_RADDR_READ 0x00000010UL 1247 #define TSP_DUP_PKT_CNT_CLR 0x00000040UL 1248 #define TSP_REC_AT_SYNC_DIS 0x00000100UL 1249 #define TSP_PVR1_ALIGN_EN 0x00000200UL 1250 #define TSP_REC_FORCE_SYNC_EN 0x00000400UL 1251 #define TSP_RM_PKT_DEMUX_PIPE 0x00000800UL 1252 #define TSP_VQ_EN 0x00004000UL 1253 #define TSP_VQ2PINGPONG_EN 0x00008000UL 1254 #define TSP_PVR1_REC_ALL_EN 0x00010000UL 1255 #define TSP_PVR2_REC_ALL_EN 0x00020000UL 1256 #define TSP_DMA_FLUSH_EN 0x00040000UL //PVR1, PVR2 dma flush 1257 #define TSP_REC_ALL_OLD 0x00080000UL 1258 #define TSP_TSIF0_CLK_STAMP_27_EN 0x01000000UL 1259 #define TSP_PVR1_CLK_STAMP_27_EN 0x02000000UL 1260 #define TSP_PVR2_CLK_STAMP_27_EN 0x04000000UL 1261 #define TSP_REC_NULL 0x40000000UL // No used 1262 1263 1264 REG32 VQ3_BASE; // 0xbf802dC0 0x74 1265 1266 REG32 VQ3_Config; // 0xbf802dC0 0x76 1267 #define TSP_VQ3_SIZE_208BYTE_MASK 0x0000ffffUL 1268 #define TSP_VQ3_SIZE_208BYTE_SHIFT 0UL 1269 #define TSP_VQ3_WR_THRESHOLD_MASK 0x000F0000UL 1270 #define TSP_VQ3_WR_THRESHOLD_SHIFT 16UL 1271 #define TSP_VQ3_PRI_THRESHOLD_MASK 0x00F00000UL 1272 #define TSP_VQ3_PRI_THRESHOLD_SHIFT 20UL 1273 #define TSP_VQ3_FORCEFIRE_CNT_1K_MASK 0x0F000000UL 1274 #define TSP_VQ3_FORCEFIRE_CNT_1K_SHIFT 24UL 1275 #define TSP_VQ3_RESET 0x10000000UL 1276 #define TSP_VQ3_OVF_INT_EN 0x40000000UL 1277 #define TSP_VQ3_CLR_OVF_INT 0x80000000UL 1278 1279 REG32 VQ_RX_Status; // 0xbf802dC0 0x78 1280 #define VQ_RX_ARBITER_MODE_MASK 0x0000000FUL 1281 #define VQ_RX_ARBITER_MODE_SHIFT 0UL 1282 #define VQ_RX0_PRI_MASK 0x000000F0UL 1283 #define VQ_RX0_PRI_SHIFT 4UL 1284 #define VQ_RX1_PRI_MASK 0x00000F00UL 1285 #define VQ_RX1_PRI_SHIFT 8UL 1286 #define VQ_RX2_PRI_MASK 0x0000F000UL 1287 #define VQ_RX2_PRI_SHIFT 12UL 1288 #define VQ_RX3_PRI_MASK 0x000F0000UL 1289 #define VQ_RX3_PRI_SHIFT 16UL 1290 1291 REG32 _xbf802dC0; // 0xbf802dC0 0x7a 1292 1293 REG32 MCU_Data1; // 0xbf802dC0 0x7c 1294 } REG_Ctrl; 1295 1296 // TSP part 2 1297 typedef struct _REG_Ctrl2 1298 { 1299 REG16 Qmem_Dbg; // 0xbf803ac0 0x70 1300 #define QMEM_DBG_MODE 0x0001 1301 #define QMEM_DBG_TSP_SEL_SRAM 0x0002 1302 REG16 Qmem_Dbg_RAddr; // 0xbf803ac4 0x71 1303 #define QMEM_DBG_RADDR_MASK 0xFFFF 1304 REG32 Qmem_Dbg_RD ; // 0xbf803ac8~0xbf803acc 0x72~0x73 1305 1306 } REG_Ctrl2; 1307 1308 typedef struct _REG_Ctrl3 1309 { 1310 REG16 PktConverterCfg[4]; // 0x10~13 1311 #define INPUT_MODE_MASK 0x0007UL 1312 #define INPUT_MODE_SHIF 0UL 1313 #define FORCE_SYNC_0X47 0x0008UL 1314 #define BYPASS_PKT_CONVERTER 0x0010UL 1315 #define BYPASS_SRC_ID_PARSER 0x0020UL 1316 1317 REG16 HW3_Cfg0; //0x14 1318 #define PREVENT_SRAM_COLLISION 0x0001UL 1319 #define PUSI_THREE_BYTE_MODE 0x0002UL 1320 #define PCR0_SRC_MASK 0x0F00UL 1321 #define PCR0_SRC_SHIFT 8UL 1322 #define PCR1_SRC_MASK 0xF000UL 1323 #define PCR1_SRC_SHIFT 12UL 1324 1325 REG16 HW3_Cfg1; //0x15 1326 #define MASK_SCR_VID_EN 0x0001UL 1327 #define MASK_SCR_VID_3D_EN 0x0002UL 1328 #define MASK_SCR_AUD_EN 0x0004UL 1329 #define MASK_SCR_AUD_B_EN 0x0008UL 1330 #define MASK_SCR_PVR1_EN 0x0040UL 1331 #define MASK_SCR_PVR2_EN 0x0080UL 1332 #define RST_CC_MODE 0x0100UL 1333 #define DIS_CNTR_INC_BY_PL 0x0200UL 1334 #define BYPASS_TIMESTAMP_SEL0 0x0400UL 1335 #define BYPASS_TIMESTAMP_SEL1 0x0800UL 1336 1337 REG32 PauseTime[2]; // 0x16~17, 0x18~19 1338 REG32 PIDFLR_PCR[2]; 1339 #define TSP_PIDFLT_PCR_PID_MASK 0x00001fffUL 1340 #define TSP_PIDFLT_PCR_EN 0x00008000UL 1341 #define TSP_PIDFLT_PCR_SOURCE_MASK 0x000F0000UL 1342 #define TSP_PIDFLT_PCR_SOURCE_SHIFT 16UL 1343 REG32 Reserve; // 0x1e 1344 REG16 HW_Semaphore0; // 0x20 1345 REG16 HW_Semaphore1; // 0x21 1346 REG16 HW_Semaphore2; // 0x22 1347 1348 REG16 HWeco0; // 0x23 1349 #define HW_ECO_RVU 0x0001UL //RVU, reg_start_read_bypass_en, set 1 to fix start_read hang when unexpected writes 1350 #define HW_ECO_NEW_SYNCP_IN_ECO 0x0002UL // fixed_rm_pinpong_limation_en 1351 #define HW_ECO_SEC_DMA_BURST_NEWMODE 0x000CUL // fixed bust length 2 /4 issue 1352 #define HW_ECO_FIX_SEC_NULLPKT_ERR 0x0020UL 1353 1354 REG16 HWeco1; // 0x24 1355 REG16 ModeCfg; // 0x25 1356 #define TSP_3WIRE_SERIAL_MODE_MASK 0x001FUL //set 1 to enable 3 wire serial in mode: Combine valid and clk.Valid always 1 and gated clk when no data in 1357 #define TSP_3WIRE_SERIAL_TSIF0 0x0001UL 1358 #define TSP_3WIRE_SERIAL_TSIF1 0x0002UL 1359 #define TSP_3WIRE_SERIAL_TSIF2 0x0004UL 1360 #define TSP_3WIRE_SERIAL_TSIFFI 0x0010UL 1361 #define TSP_NEW_OVERFLOW_MODE 0x0100UL // 1: new dma_overflow 0:old dma_overflow 1362 #define TSP_NON_188_CNT_MODE 0x0200UL 1363 REG16 dummy[2]; // 0x26~27 1364 1365 REG16 SyncByte_tsif0[4]; // 0x28~2b 1366 #define TSP_SYNC_BYTE0_MAASK0 0x00FFUL 1367 #define TSP_SYNC_BYTE0_MAASK1 0xFF00UL 1368 REG16 SourceId_tsif0[2]; // 0x2c~2d 1369 #define TSP_SRCID_MASK0 0x000FUL 1370 #define TSP_SRCID_MASK1 0x00F0UL 1371 #define TSP_SRCID_MASK2 0x0F00UL 1372 #define TSP_SRCID_MASK3 0xF000UL 1373 REG16 SyncByte_file[4]; // 0x2e~31 1374 REG16 SourceId_file[2]; // 0x32~33 1375 REG16 SyncByte_tsif1[4]; // 0x34~37 1376 REG16 SourceId_tsif1[2]; // 0x38~39 1377 REG16 SyncByte_tsif2[4]; // 0x3a~3d 1378 REG16 SourceId_tsif2[2]; // 0x3e~3f 1379 } REG_Ctrl3; 1380 1381 // TSP part 4 1382 typedef struct _REG_Ctrl4 1383 { 1384 REG16 Overflow0; // 0xbf803900 0x00 1385 #define PID_HIT_0_EVER_OVERFLOW 0x0001UL 1386 #define PID_HIT_1_EVER_OVERFLOW 0x0002UL 1387 #define PID_HIT_2_EVER_OVERFLOW 0x0004UL 1388 #define PID_HIT_FILE_EVER_OVERFLOW 0x0008UL 1389 #define AFIFO_EVER_OVERFLOW 0x0020UL 1390 #define AFIFOB_EVER_OVERFLOW 0x0040UL 1391 #define VFIFO_EVER_OVERFLOW 0x0080UL 1392 #define V3DFIFO_EVER_OVERFLOW 0x0100UL 1393 #define PVR_1_EVER_OVERFLOW 0x0200UL 1394 #define PVR_2_EVER_OVERFLOW 0x0400UL 1395 #define VQ_TX0_EVER_OVERFLOW 0x1000UL 1396 #define VQ_TX1_EVER_OVERFLOW 0x2000UL 1397 #define VQ_TX2_EVER_OVERFLOW 0x4000UL 1398 #define VQ_TX3_EVER_OVERFLOW 0x8000UL 1399 1400 REG16 Overflow1; // 0xbf803904 0x01 1401 #define AFIFOD_EVER_OVERFLOW 0x0010UL 1402 #define AFIFOC_EVER_OVERFLOW 0x0008UL 1403 #define SEC_DMAW_OVERFLOW 0x0004UL 1404 #define SEC_SINGLE_EVER_OVERFLOW 0x0002UL 1405 #define SEC_PINGPONG_EVER_OVERFLOW 0x0001UL 1406 1407 REG16 FifoStatus; // 0xbf803908 0x02 1408 #define AFIFO_STATUS_MASK 0x000FUL 1409 #define AFIFO_STATUS_SHFT 0UL 1410 #define AFIFOC_STATUS_MASK 0x000FUL 1411 #define AFIFOC_STATUS_SHFT 0UL 1412 #define AFIFOB_STATUS_MASK 0x00F0UL 1413 #define AFIFOB_STATUS_SHFT 4UL 1414 #define AFIFOD_STATUS_MASK 0x00F0UL 1415 #define AFIFOD_STATUS_SHFT 4UL 1416 #define VFIFO_STATUS_MASK 0x0F00UL 1417 #define VFIFO_STATUS_SHFT 8UL 1418 #define V3DFIFO_STATUS_MASK 0xF000UL 1419 #define V3DFIFO_STATUS_SHFT 12UL 1420 1421 REG16 PvrFifoStatus; // 0xbf80390C 0x03 1422 #define PVR_1_STATUS_MASK 0x000FUL 1423 #define PVR_1_STATUS_SHFT 0UL 1424 1425 REG16 VQTxFifoStatus; // 0xbf803910 0x04 1426 #define VQ_TX0_STATUS_MASK 0x000FUL 1427 #define VQ_TX0_STATUS_SHFT 0UL 1428 #define VQ_TX1_STATUS_MASK 0x0F00UL 1429 #define VQ_TX1_STATUS_SHFT 8UL 1430 1431 REG16 PktCnt_video; // 0xbf803914 0x05 1432 REG16 PktCnt_v3d; // 0xbf803918 0x06 1433 REG16 PktCnt_aud; // 0xbf80391C 0x07 1434 REG16 PktCnt_audB; // 0xbf803920 0x08 1435 1436 REG32 _bf803924[2]; //0xbf803924~0xbf803930 0x09~0x0c 1437 1438 REG16 LockedPktCnt; // 0x0d 1439 REG16 AVPktCnt; // 0x0e 1440 1441 REG16 PktErrStatus; // 0xbf80392C 0x0x0f 1442 REG16 PidMatched0; // 0xbf803930 0x10 1443 REG16 PidMatched1; // 0xbf803934 0x11 1444 REG16 PidMatched2; // 0xbf803938 0x12 1445 REG16 PidMatched3; // 0xbf80393C 0x13 1446 REG16 dummy[2]; // 0x14~0x15 1447 REG16 Sram2p_collision; // 0x16 1448 #define SRAM_COLLISION_BY_SW 0x1000UL 1449 #define SRAM_COLLISION_BY_HW 0x2000UL 1450 #define SECFLT_SRAM1_EVER_COLLISION 0x4000UL 1451 #define SECFLT_SRAM0_EVER_COLLISION 0x8000UL 1452 REG16 AVPktCnt1; //for vid_3d/audb 0x17 1453 REG16 ErrPktCnt; //use reg_err_pkt_src_sel 0x18 1454 REG16 AVPktCnt2; //for audc/audd 0x19 1455 1456 REG16 EverUnlockStatus; // 0x1a 1457 #define EVER_UNLOCK_TS0 0x0001UL // set 1 mean there are unlock pkts 1458 #define EVER_UNLOCK_TS1 0x0002UL 1459 #define EVER_UNLOCK_TS2 0x0004UL 1460 1461 REG16 Overflow2; // 0xbf803904 0x1b 1462 #define PC_EVER_OVERFLOW_0 0x0001UL 1463 #define PC_EVER_OVERFLOW_FILE 0x0002UL 1464 #define PC_EVER_OVERFLOW_1 0x0004UL 1465 #define PC_EVER_OVERFLOW_2 0x0008UL 1466 1467 REG16 dummy1[0x70-0x1c]; //0x1C~0x6f 1468 REG16 ErrPktSrcSel; //select source of ErrPktCnt 0x70 1469 #define ERR_PKT_SRC_TS0 0x0001UL 1470 #define ERR_PKT_SRC_FILE 0x0002UL 1471 #define ERR_PKT_SRC_TS1 0x0003UL 1472 #define ERR_PKT_SRC_TS2 0x0004UL 1473 #define ERR_PKT_SRC_MMFI0 0x0005UL 1474 #define ERR_PKT_SRC_MMFI1 0x0006UL 1475 1476 REG16 ErrPktCntLoad; // 0x71 1477 #define ERR_PKT_CNT_0_LOAD 0x0001UL 1478 #define ERR_PKT_CNT_FILE_LOAD 0x0002UL 1479 #define ERR_PKT_CNT_1_LOAD 0x0004UL 1480 #define ERR_PKT_CNT_2_LOAD 0x0008UL 1481 #define ERR_PKT_CNT_MMFI0_LOAD 0x0010UL 1482 #define ERR_PKT_CNT_MMFI1_LOAD 0x0020UL 1483 1484 REG16 ErrPktCntClr; // 0x72 1485 #define ERR_PKT_CNT_0_CLR 0x0001UL 1486 #define ERR_PKT_CNT_FILE_CLR 0x0002UL 1487 #define ERR_PKT_CNT_1_CLR 0x0004UL 1488 #define ERR_PKT_CNT_2_CLR 0x0008UL 1489 #define ERR_PKT_CNT_MMFI0_CLR 0x0010UL 1490 #define ERR_PKT_CNT_MMFI1_CLR 0x0020UL 1491 1492 REG16 dummy2[0x7A-0x73]; // 0x73~0x79 1493 REG16 PktCntLoad; // 0x7a 1494 #define LOCK_PKT_CNT_0_LOAD 0x0001UL 1495 #define LOCK_PKT_CNT_1_LOAD 0x0002UL 1496 #define LOCK_PKT_CNT_2_LOAD 0x0004UL 1497 #define LOCK_PKT_CNT_FI_LOAD 0x0010UL 1498 #define V_PKT_CNT_LOAD 0x0100UL 1499 #define V3D_PKT_CNT_LOAD 0x0200UL 1500 #define AUD_PKT_CNT_LOAD 0x0400UL 1501 #define AUDB_PKT_CNT_LOAD 0x0800UL 1502 1503 REG16 PktCntLoad1; // 0x7b 1504 #define V_DROP_PKT_CNT_LOAD 0x0001UL 1505 #define V3D_DROP_PKT_CNT_LOAD 0x0002UL 1506 #define AUD_DROP_PKT_CNT_LOAD 0x0004UL 1507 #define AUDB_DROP_PKT_CNT_LOAD 0x0008UL 1508 #define V_DIS_CNTR_PKT_CNT_LOAD 0x0100UL 1509 #define V3D_DIS_CNTR_PKT_CNT_LOAD 0x0200UL 1510 #define AUD_DIS_CNTR_PKT_CNT_LOAD 0x0400UL 1511 #define AUDB_DIS_CNTR_PKT_CNT_LOAD 0x0800UL 1512 1513 REG16 PktCntClr; // 0x7c 1514 #define LOCK_PKT_CNT_0_CLR 0x0001UL 1515 #define LOCK_PKT_CNT_1_CLR 0x0002UL 1516 #define LOCK_PKT_CNT_2_CLR 0x0004UL 1517 #define LOCK_PKT_CNT_FI_CLR 0x0010UL 1518 #define V_PKT_CNT_CLR 0x0100UL 1519 #define V3D_PKT_CNT_CLR 0x0200UL 1520 #define AUD_PKT_CNT_CLR 0x0400UL 1521 #define AUDB_PKT_CNT_CLR 0x0800UL 1522 1523 REG16 PktCntClr1; // 0x7d 1524 #define V_DROP_PKT_CNT_CLR 0x0001UL 1525 #define V3D_DROP_PKT_CNT_CLR 0x0002UL 1526 #define AUD_DROP_PKT_CNT_CLR 0x0004UL 1527 #define AUDB_DROP_PKT_CNT_CLR 0x0008UL 1528 #define V_DIS_CNTR_PKT_CNT_CLR 0x0100UL 1529 #define V3D_DIS_CNTR_PKT_CNT_CLR 0x0200UL 1530 #define AUD_DIS_CNTR_PKT_CNT_CLR 0x0400UL 1531 #define AUDB_DIS_CNTR_PKT_CNT_CLR 0x0800UL 1532 1533 REG16 PktCntSrc; // 0x7e 1534 #define VID_SRC_MASK 0x0007UL 1535 #define VID_SRC_SHIFT 0UL 1536 #define V3D_SRC_MASK 0x0031UL 1537 #define V3D_SRC_SHIFT 3UL 1538 #define AUD_SRC_MASK 0x01C0UL 1539 #define AUD_SRC_SHIFT 6UL 1540 #define AUDB_SRC_MASK 0x0E00UL 1541 #define AUDB_SRC_SHIFT 9UL 1542 1543 REG16 DebugSrcSel; // 0x7f 1544 #define SRC_SEL_MASK 0x0001UL 1545 #define DROP_PKT_MODE_MASK 0x0002UL 1546 #define PIDFLT_SRC_SEL_MASK 0x001CUL 1547 #define TSIF_SRC_SEL_MASK 0x00E0UL 1548 #define TSIF_SRC_SEL_SHIFT 5UL 1549 #define TSIF_SRC_SEL_TSIF0 0x000UL 1550 #define TSIF_SRC_SEL_TSIF1 0x001UL 1551 #define TSIF_SRC_SEL_TSIF2 0x002UL 1552 #define TSIF_SRC_SEL_TSIF_FI 0x004UL 1553 #define AV_PKT_SRC_SEL 0x0100UL 1554 #define AV_PKT_SRC_SEL_MASK 0x0100UL 1555 #define AV_PKT_SRC_SEL_SHIFT 8UL 1556 #define AV_PKT_SRC_VID 0x0 1557 #define AV_PKT_SRC_AUD 0x1 1558 #define AV_PKT_SRC_V3D 0x0 1559 #define AV_PKT_SRC_AUDB 0x1 1560 #define CLR_SRC_MASK 0x0E00UL 1561 #define CLR_SRC_SHIFT 9UL 1562 #define CLR_SRC_TSIF0 0x0200UL 1563 #define CLR_SRC_TSIFFI 0x0400UL 1564 #define CLR_SRC_TSIF1 0x0600UL 1565 #define CLR_SRC_TSIF2 0x0800UL 1566 #define CLR_SRC_MMFI0 0x0C00UL 1567 #define CLR_SRC_MMFI1 0x0E00UL 1568 1569 }REG_Ctrl4; 1570 1571 // TSP part 4 1572 typedef struct _REG_Ctrl5 1573 { 1574 REG16 ATS_Adj_Period; // 0x00 1575 #define TSP_ATS_ADJ_PERIOD_MASK 0x000FUL 1576 1577 REG16 AtsCfg; // 0x01 1578 #define TSP_ATS_MODE_FI_ENABLE 0x0001UL 1579 #define TSP_ATS_OFFSET_FI_ENABLE 0x0002UL 1580 #define TSP_ATS_OFFSET_FI_SHIFT 8UL 1581 #define TSP_ATS_OFFSET_FI_MASK 0x0F00UL 1582 #define TSP_ATS_OFFSET_FI_POSITIVE 0x0000UL 1583 #define TSP_ATS_OFFSET_FI_NEGATIVE 0x1000UL 1584 1585 REG16 Ts_If_Fi_Cfg; // 0x02 1586 #define TSP_FIIF_EN 0x0001UL 1587 #define TSP_FIIF_DATA_SWAP 0x0002UL 1588 #define TSP_FIIF_P_SEL 0x0004UL 1589 #define TSP_FIIF_EXT_SYNC_SEL 0x0008UL 1590 #define TSP_FIIF_MUX_MASK 0x0010UL 1591 #define TSP_FIIF_MUX_FILE_PATH 0x0000UL 1592 #define TSP_FIIF_MUX_LIVE_PATH 0x0010UL 1593 #define TSP_PKT_CHK_SIZE_FI_MASK 0xFF00UL 1594 #define TSP_PKT_CHK_SIZE_FI_SHIFT 8UL 1595 1596 REG16 MatchPidSel; // 0x03 1597 #define TSP_MATCH_PID_SEL_MASK 0x000FUL 1598 #define TSP_MATCH_PID_SEL_SHIFT 0UL 1599 1600 REG16 TsifCfg; // 0x04 1601 #define TSP_TSIFCFG_TSIF0_TSOBLK_EN 0x0100UL 1602 #define TSP_TSIFCFG_TSIF1_TSOBLK_EN 0x0200UL 1603 #define TSP_TSIFCFG_TSIF2_TSOBLK_EN 0x0400UL 1604 #define TSP_TSIFCFG_TSIFFI_TSOBLK_EN 0x0800UL 1605 #define TSP_TSIFCFG_WB_FSM_RESET 0x1000UL 1606 #define TSP_TSIFCFG_WB_FSM_RESET_FINISH 0x2000UL 1607 1608 REG16 TraceMarkCfg; // 0x05 1609 #define TSP_TRACE_MARK_VID_EN 0x0001UL 1610 #define TSP_TRACE_MARK_V3D_EN 0x0002UL 1611 #define TSP_TRACE_MARK_AUD_EN 0x0004UL 1612 #define TSP_TRACE_MARK_AUDB_EN 0x0008UL 1613 #define TSP_TRACE_MARK_AUDC_EN 0x0010UL 1614 #define TSP_TRACE_MARK_AUDD_EN 0x0020UL 1615 1616 REG16 HwCfg0; // 0x06 1617 #define TSP_FIX_192_TIMER_0_EN 0x0001UL 1618 #define TSP_VQ_CLR 0x0002UL 1619 #define TSP_FILTER_NULL_PKT0 0x0004UL 1620 #define TSP_FILTER_NULL_PKT1 0x0008UL 1621 #define TSP_FILTER_NULL_PKT2 0x0010UL 1622 #define TSP_FILTER_NULL_PKT_FILE 0x0020UL 1623 #define TSP_FLUSH_PVR1_DATA 0x0100UL 1624 #define TSP_FLUSH_PVR2_DATA 0x0200UL 1625 1626 REG16 InitTimestamp; // 0x07 1627 #define TSP_INIT_TIMESTAMP_FILEIN 0x0001UL 1628 #define TSP_INIT_TIMESTAMP_MMFI0 0x0002UL 1629 #define TSP_INIT_TIMESTAMP_MMFI1 0x0004UL 1630 1631 REG16 MiuSelCtrl0; // 0x08 1632 #define TSP_MIU_SEL_FILEIN_MASK 0x0003UL 1633 #define TSP_MIU_SEL_FILEIN_SHIFT 0UL 1634 #define TSP_MIU_SEL_SECTION_MASK 0x000CUL 1635 #define TSP_MIU_SEL_SECTION_SHIFT 2UL 1636 #define TSP_MIU_SEL_MMFI0_MASK 0x0030UL 1637 #define TSP_MIU_SEL_MMFI0_SHIFT 4UL 1638 #define TSP_MIU_SEL_MMFI1_MASK 0x00C0UL 1639 #define TSP_MIU_SEL_MMFI1_SHIFT 6UL 1640 #define TSP_MIU_SEL_VQ_RW_MASK 0x0300UL 1641 #define TSP_MIU_SEL_VQ_RW_SHIFT 8UL 1642 #define TSP_MIU_SEL_OR_RW_MASK 0x0C00UL 1643 #define TSP_MIU_SEL_OR_RW_SHIFT 10UL 1644 1645 REG16 MiuSelCtrl1; // 0x09 1646 #define TSP_MIU_SEL_PVR1_MASK 0x0003UL 1647 #define TSP_MIU_SEL_PVR1_SHIFT 0UL 1648 #define TSP_MIU_SEL_PVR2_MASK 0x000CUL 1649 #define TSP_MIU_SEL_PVR2_SHIFT 2UL 1650 #define TSP_MIU_SEL_FIQ0_RW_MASK 0x0300UL 1651 #define TSP_MIU_SEL_FIQ0_RW_SHIFT 8UL 1652 #define TSP_MIU_SEL_FIQ1_RW_MASK 0x0C00UL 1653 #define TSP_MIU_SEL_FIQ1_RW_SHIFT 10UL 1654 1655 REG16 MiuRrPri; // 0x0A 1656 #define TSP_MIU_RR_PRI_ABT0 0x0001UL 1657 #define TSP_MIU_RR_PRI_ABT1 0x0002UL 1658 #define TSP_MIU_RR_PRI_ABT2 0x0004UL 1659 #define TSP_MIU_RR_PRI_ABT3 0x0008UL 1660 #define TSP_MIU_RR_PRI_ABT4 0x0010UL 1661 1662 REG16 dummy0[0x10-0xB]; // 0xB~0xF 1663 1664 REG16 TS_MUX_CFG0; // 0x10 1665 #define TS_MUX_CFG_TS0_MUX_MASK 0x000FUL 1666 #define TS_MUX_CFG_TS0_MUX_SHIFT 0UL 1667 #define TS_MUX_CFG_TS1_MUX_MASK 0x00F0UL 1668 #define TS_MUX_CFG_TS1_MUX_SHIFT 4UL 1669 #define TS_MUX_CFG_TS2_MUX_MASK 0x0F00UL 1670 #define TS_MUX_CFG_TS2_MUX_SHIFT 8UL 1671 #define TS_MUX_CFG_TSFI_MUX_MASK 0xF000UL 1672 #define TS_MUX_CFG_TSFI_MUX_SHIFT 12UL 1673 #define TS_MUX_CFG_TS_MUX_TS0 0x0000UL 1674 #define TS_MUX_CFG_TS_MUX_TS1 0x0001UL 1675 #define TS_MUX_CFG_TS_MUX_TS2 0x0002UL 1676 #define TS_MUX_CFG_TS_MUX_TSO 0x0006UL 1677 #define TS_MUX_CFG_TS_MUX_DMD 0x0007UL 1678 REG16 TS_MUX_CFG1; // 0x11 1679 1680 REG16 TS_MUX_CFG_S2P; // 0x12 1681 #define TS_MUX_CFG_S2P0_MUX_MASK 0x000FUL 1682 #define TS_MUX_CFG_S2P_MUX_TS0 0x0000UL 1683 #define TS_MUX_CFG_S2P_MUX_TS1 0x0001UL 1684 #define TS_MUX_CFG_S2P_MUX_TS2 0x0002UL 1685 1686 REG16 TS_MUX_CFG0_TSOIN; // 0x13 1687 #define TS_MUX_CFG_TSOIN0_MUX_MASK 0x000FUL 1688 #define TS_MUX_CFG_TSOIN0_MUX_SHIFT 0UL 1689 #define TS_MUX_CFG_TSOIN1_MUX_MASK 0x00F0UL 1690 #define TS_MUX_CFG_TSOIN1_MUX_SHIFT 4UL 1691 #define TS_MUX_CFG_TSOIN2_MUX_MASK 0x0F00UL 1692 #define TS_MUX_CFG_TSOIN2_MUX_SHIFT 8UL 1693 #define TS_MUX_CFG_TSO_MUX_TS0 0x0000UL 1694 #define TS_MUX_CFG_TSO_MUX_TS1 0x0001UL 1695 #define TS_MUX_CFG_TSO_MUX_TS2 0x0002UL 1696 #define TS_MUX_CFG_TSO_MUX_DMD 0x0007UL 1697 1698 REG16 TSP5_Reserve_14; // 0x14 1699 1700 REG16 TS_MUX_CFG_TSOOUT; // 0x15 1701 #define TS_MUX_CFG_TSOOUT_MASK 0x000FUL 1702 #define TS_MUX_CFG_TSOOUT_FROM_TSO 0x0000UL 1703 #define TS_MUX_CFG_TSOOUT_FROM_S2P 0x0001UL 1704 1705 REG16 dummy1[0x20-0x16]; // 0x16~0x1F 1706 1707 REG32 FileIn_Dmar_LBnd; // 0x20 1708 #define TS_FILEIN_DMAR_LBND_MASK 0x0FFFFFFFUL 1709 1710 REG32 FileIn_Dmar_UBnd; // 0x22 1711 #define TS_FILEIN_DMAR_UBND_MASK 0x0FFFFFFFUL 1712 1713 REG32 MMFileIn0_Dmar_LBnd; // 0x24 1714 #define TS_MMFILEIN0_DMAR_LBND_MASK 0x0FFFFFFFUL 1715 1716 REG32 MMFileIn0_Dmar_UBnd; // 0x26 1717 #define TS_MMFILEIN0_DMAR_UBND_MASK 0x0FFFFFFFUL 1718 1719 REG32 MMFileIn1_Dmar_LBnd; // 0x28 1720 #define TS_MMFILEIN1_DMAR_LBND_MASK 0x0FFFFFFFUL 1721 1722 REG32 MMFileIn1_Dmar_UBnd; // 0x2A 1723 #define TS_MMFILEIN1_DMAR_UBND_MASK 0x0FFFFFFFUL 1724 1725 REG32 Orz_Dmar_LBnd; // 0x2C 1726 #define TS_ORZ_DMAR_LBND_MASK 0x0FFFFFFFUL 1727 1728 REG32 Orz_Dmar_UBnd; // 0x2E 1729 #define TS_ORZ_DMAR_UBND_MASK 0x0FFFFFFFUL 1730 1731 REG32 VQTX0_Dmar_LBnd; // 0x30 1732 #define TS_VQTX0_DMAR_LBND_MASK 0x0FFFFFFFUL 1733 1734 REG32 VQTX0_Dmar_UBnd; // 0x32 1735 #define TS_VQTX0_DMAR_UBND_MASK 0x0FFFFFFFUL 1736 1737 REG32 VQTX1_Dmar_LBnd; // 0x34 1738 #define TS_VQTX1_DMAR_LBND_MASK 0x0FFFFFFFUL 1739 1740 REG32 VQTX1_Dmar_UBnd; // 0x36 1741 #define TS_VQTX1_DMAR_UBND_MASK 0x0FFFFFFFUL 1742 1743 REG32 VQTX2_Dmar_LBnd; // 0x38 1744 #define TS_VQTX2_DMAR_LBND_MASK 0x0FFFFFFFUL 1745 1746 REG32 VQTX2_Dmar_UBnd; // 0x40 1747 #define TS_VQTX2_DMAR_UBND_MASK 0x0FFFFFFFUL 1748 1749 REG32 VQTX3_Dmar_LBnd; // 0x42 1750 #define TS_VQTX3_DMAR_LBND_MASK 0x0FFFFFFFUL 1751 1752 REG32 VQTX3_Dmar_UBnd; // 0x44 1753 #define TS_VQTX3_DMAR_UBND_MASK 0x0FFFFFFFUL 1754 1755 REG32 VQRX_Dmar_LBnd; // 0x46 1756 #define TS_VQRX_DMAR_LBND_MASK 0x0FFFFFFFUL 1757 1758 REG32 VQRX_Dmar_UBnd; // 0x48 1759 #define TS_VQRX_DMAR_UBND_MASK 0x0FFFFFFFUL 1760 1761 REG32 Fiq0_Dmar_LBnd; // 0x4A 1762 #define TS_Fiq0_DMAR_LBND_MASK 0x0FFFFFFFUL 1763 1764 REG32 Fiq0_Dmar_UBnd; // 0x4C 1765 #define TS_Fiq0_DMAR_UBND_MASK 0x0FFFFFFFUL 1766 1767 REG32 Fiq1_Dmar_LBnd; // 0x4E 1768 #define TS_Fiq1_DMAR_LBND_MASK 0x0FFFFFFFUL 1769 1770 REG32 Fiq1_Dmar_UBnd; // 0x50 1771 #define TS_Fiq1_DMAR_UBND_MASK 0x0FFFFFFFUL 1772 1773 REG16 dummy2[0x60-0x52]; // 0x52~0x5F 1774 1775 REG16 Dma_Ns_Cfg; // 0x60 1776 #define TS_DMA_NS_CTRL_FILEIN 0x0001UL 1777 #define TS_DMA_NS_CTRL_MMFI0 0x0002UL 1778 #define TS_DMA_NS_CTRL_MMFI1 0x0004UL 1779 #define TS_DMA_NS_CTRL_PVR1 0x0008UL 1780 #define TS_DMA_NS_CTRL_PVR2 0x0010UL 1781 #define TS_DMA_NS_CTRL_VQ 0x0020UL 1782 #define TS_DMA_NS_CTRL_ORZ 0x0040UL 1783 #define TS_DMA_NS_CTRL_SEC 0x0080UL 1784 #define TS_DMA_NS_CTRL_FIQ0 0x0100UL 1785 #define TS_DMA_NS_CTRL_FIQ1 0x0200UL 1786 1787 REG16 Dma_Be_Cfg; // 0x61 1788 #define TS_DMA_BE_CTRL_FILEIN 0x0001UL 1789 #define TS_DMA_BE_CTRL_MMFI0 0x0002UL 1790 #define TS_DMA_BE_CTRL_MMFI1 0x0004UL 1791 #define TS_DMA_BE_CTRL_PVR1 0x0008UL 1792 #define TS_DMA_BE_CTRL_PVR2 0x0010UL 1793 #define TS_DMA_BE_CTRL_VQ 0x0020UL 1794 #define TS_DMA_BE_CTRL_ORZ 0x0040UL 1795 #define TS_DMA_BE_CTRL_SEC 0x0080UL 1796 #define TS_DMA_BE_CTRL_FIQ0 0x0100UL 1797 #define TS_DMA_BE_CTRL_FIQ1 0x0200UL 1798 1799 REG16 MIU_NsUseTee_Cfg; // 0x62 1800 #define TS_MIU_NS_USE_TEE_WP_RP_FILEIN 0x0001UL 1801 #define TS_MIU_NS_USE_TEE_WP_RP_MMFI0 0x0002UL 1802 #define TS_MIU_NS_USE_TEE_WP_RP_MMFI1 0x0004UL 1803 1804 }REG_Ctrl5; 1805 1806 // TSP: ts sample part 1807 typedef struct _REG_TS_Sample 1808 { 1809 REG16 TS0_Clk_Sample; // 0x00 1810 #define TS0_PHASE_ADJUST_COUNT_MASK 0x001FUL 1811 #define TS0_PHASE_ADJUST_EN 0x0020UL 1812 #define TS0_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 1813 1814 REG16 TS1_Clk_Sample; // 0x01 1815 #define TS1_PHASE_ADJUST_COUNT_MASK 0x001FUL 1816 #define TS1_PHASE_ADJUST_EN 0x0020UL 1817 #define TS1_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 1818 1819 REG16 TS2_Clk_Sample; // 0x02 1820 #define TS2_PHASE_ADJUST_COUNT_MASK 0x001FUL 1821 #define TS2_PHASE_ADJUST_EN 0x0020UL 1822 #define TS2_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 1823 1824 REG16 TS3_Clk_Sample; // 0x03 1825 #define TS3_PHASE_ADJUST_COUNT_MASK 0x001FUL 1826 #define TS3_PHASE_ADJUST_EN 0x0020UL 1827 #define TS3_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 1828 1829 REG16 TS4_Clk_Sample; // 0x04 1830 #define TS4_PHASE_ADJUST_COUNT_MASK 0x001FUL 1831 #define TS4_PHASE_ADJUST_EN 0x0020UL 1832 #define TS4_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 1833 1834 REG16 TS5_Clk_Sample; // 0x05 1835 #define TS5_PHASE_ADJUST_COUNT_MASK 0x001FUL 1836 #define TS5_PHASE_ADJUST_EN 0x0020UL 1837 #define TS5_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 1838 1839 REG16 TsSample_Reserved0[0x10-0x6]; // 0x06 - 0x0F 1840 1841 REG16 TSO_Clk_Sample; // 0x10 1842 #define TSO_PHASE_ADJUST_COUNT_MASK 0x001FUL 1843 #define TSO_PHASE_ADJUST_EN 0x0020UL 1844 #define TSO_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 1845 #define TSO_CLK_INVERT 0x0080UL 1846 1847 REG16 TsSample_Reserved1[0x20-0x11]; // 0x11 - 0x1F 1848 1849 REG16 TS_Out_Clk_Sample; // 0x20 (for old path: TSIF2 out) 1850 #define TS_OUT_PHASE_ADJUST_COUNT_MASK 0x001FUL 1851 #define TS_OUT_PHASE_ADJUST_EN 0x0020UL 1852 #define TS_OUT_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 1853 #define TS_OUT_CLK_INVERT 0x0080UL 1854 1855 REG16 S2P_Out_Clk_Sample; // 0x21 1856 #define S2P_PHASE_ADJUST_COUNT_MASK 0x001FUL 1857 #define S2P_PHASE_ADJUST_EN 0x0020UL 1858 #define S2P_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 1859 #define S2P_CLK_INVERT 0x0080UL 1860 1861 REG16 S2P1_Out_Clk_Sample; // 0x22 1862 #define S2P1_PHASE_ADJUST_COUNT_MASK 0x001FUL 1863 #define S2P1_PHASE_ADJUST_EN 0x0020UL 1864 #define S2P1_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 1865 #define S2P1_CLK_INVERT 0x0080UL 1866 1867 }REG_TS_Sample; 1868 1869 // Firmware status 1870 #define TSP_FW_STATE_MASK 0xFFFF0000UL 1871 #define TSP_FW_STATE_LOAD 0x00010000UL 1872 #define TSP_FW_STATE_ENG_OVRUN 0x00020000UL 1873 #define TSP_FW_STATE_ENG1_OVRUN 0x00040000UL //[reserved] 1874 #define TSP_FW_STATE_IC_ENABLE 0x01000000UL 1875 #define TSP_FW_STATE_DC_ENABLE 0x02000000UL 1876 #define TSP_FW_STATE_IS_ENABLE 0x04000000UL 1877 #define TSP_FW_STATE_DS_ENABLE 0x08000000UL 1878 1879 1880 // TSP AEON specific IP address 1881 #define OPENRISC_IP_1_ADDR 0x00200000UL 1882 #define OPENRISC_IP_1_SIZE 0x00020000UL 1883 #define OPENRISC_IP_2_ADDR 0x90000000UL 1884 #define OPENRISC_IP_2_SIZE 0x00010000UL 1885 #define OPENRISC_IP_3_ADDR 0x40080000UL 1886 #define OPENRISC_IP_3_SIZE 0x00020000UL 1887 #define OPENRISC_QMEM_ADDR 0x00000000UL 1888 #define OPENRISC_QMEM_SIZE 0x00003000UL 1889 #endif // _TSP_REG_H_ 1890 1891