1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regRASP.h 98 // Description: RASP Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _RASP_REG_H_ 103 #define _RASP_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 137 //-------------------------------------------------------------------------------------------------- 138 // Compliation Option 139 //-------------------------------------------------------------------------------------------------- 140 141 //------------------------------------------------------------------------------------------------- 142 // Harware Capability 143 //------------------------------------------------------------------------------------------------- 144 #define RASP_PIDFLT_NUM 24 145 #define RASP_PIDFLT_DEF 0x1fff 146 #define RASP_EVENT_NUM 16 147 #define RASP_EVENT_FIFO_DEPTH 32*4 148 149 //------------------------------------------------------------------------------------------------- 150 // Type and Structure 151 //------------------------------------------------------------------------------------------------- 152 153 #define REG_RASP0_BASE (0x111B00<<1) 154 #define REG_RASP0_FILE_BASE (0x112500<<1) 155 156 #define REG_RASP1_BASE (0x111D00<<1) 157 #define REG_RASP1_FILE_BASE (0x112600<<1) 158 159 #define REG_CHIPTOP_RP_BASE (0x101E00<<1) 160 #define REG_CLKGEN_RP_BASE (0x100B00<<1) 161 #define REG_CLKGEN2_BASE (0x100A00<<1) 162 163 #define RASP_PID_PKT_CORPT_EN 0x2000 164 165 166 #define REG_RASP_PKT_TIMER_L 0x0000 167 #define REG_RASP_PKT_TIMER_H 0x0001 168 #define REG_RASP_PKT_NUM_L 0x0002 169 #define REG_RASP_PKT_NUM_H 0x0003 170 #define REG_RASP_CORRUPTION 0x0004 171 #define RASP_FROMTO_MASK 0x00FF 172 #define RASP_TO_SHIFT 8 173 174 #define REG_RASP_CORPT_PKTSIZE 0x0005 175 #define RASP_CORPT_DATA 0x00FF 176 #define RASP_PKT_SIZE 0xFF00 177 #define RASP_PKT_SIZE_188 0xBB 178 #define RASP_PKT_SHIFT 8 179 180 #define REG_RASP_EVENTLOG_STATUS 0x0006 181 #define RASP_EVENT_FIFO_NUM_MASK 0x0000001F 182 #define RASP_EVENT_FIFO_FULL 0X00000020 183 #define RASP_EVENT_FIFO_EMPTY 0x00000040 184 #define RASP_EVENT_FIFO_RDLV_MASK 0x00000300 185 #define RASP_EVENT_FIFO_RDLV_SHIFT 8 186 #define RASP_EVENT_FIFO_WTLV_MASK 0x00000C00 187 #define RASP_EVENT_FIFO_WTLV_SHIFT 10 188 #define RASP_EVENT_FIFO_RD_OVF 0x00001000 189 #define RASP_EVENT_FIFO_WT_OVF 0x00002000 190 191 #define REG_RASP_CONFIG_TSIF2 0x0007 192 193 #define REG_RASP_HW_CTRL0 0x0008 194 #define RASP_SW_RESET 0x00000001 195 #define RASP_TSIF2_ENABLE 0x00000002 196 #define RASP_TSIF2_DATA_SWP 0x00000004 197 #define RASP_TSIF2_PARA_SEL 0x00000008 198 #define RASP_TSIF2_EXT_SYNC 0x00000010 199 #define RASP_FILEIN_EN 0x00000020 200 #define RASP_RISING_SYNC_DETECT 0x00000080 201 #define RASP_FALLING_VALID_DETECT 0x00000100 202 #define RASP_CLR_EVENT_OVERFLOW 0x00000200 203 #define RASP_REC_EVENT_FIFO_EN 0x00001000 204 #define RASP_CLEAR_ECM_PKT_NUM 0x00002000 205 206 #define REG_RASP_HW_CTRL1 0x0009 207 #define RASP_REC_PID 0x00000001 208 #define RASP_STR2MIU_EN 0x00000002 209 #define RASP_PINGPONG_EN 0x00000004 210 #define RASP_ALT_TS_SIZE_EN 0x00000080 211 #define RASP_STR2MIU_RST_WADDR 0x00000010 212 #define RASP_SERIAL_EXT_SYNC_1T 0x00000400 213 //192 aligement 214 #define RASP_BURST_LEN_MASK 0x00001800 215 #define RASP_BURST_LEN_SHIFT 0x0000000B 216 217 #define RASP_EVENT_FIFO_READ 0x00008000 218 219 #define REG_RASP_HW_CTRL2 0x000A 220 #define RASP_INT_TIMER_EN 0x00000001 221 #define RASP_INT_EVENT_EN 0x00000002 222 223 #define RASP_INT_TIMER_MASK 0x0000000C 224 #define RASP_INT_TIMER_SHIFT 2 225 226 #define RASP_INT_EVENT_MASK 0x000001F0 227 #define RASP_INT_EVENT_SHIFT 4 228 229 #define RASP_PAYLOAD_BURST_LEN 0x00000400 230 #define RASP_ECM_BURST_LEN 0x00001000 231 232 #define REG_RASP_HW_CTRL3 0x000B 233 #define RASP_PAYLD2MIU_EN 0x00000001 234 #define RASP_PAYLD2MIU_PINGPONE 0x00000002 235 #define RASP_PAYLD2MIU_SWAP 0x00000004 236 #define RASP_PAYLD2MIU_RST_WADDR 0x00000008 237 #define RASP_PAYLD2_PKT_192_DIS 0x00000040 238 #define RASP_PAYLD2MIU_LPCR_WT 0x00000080 239 #define RASP_ECM2MIU_EN 0x00000100 240 #define RASP_ECM2MIU_RST_WADDR 0x00000800 241 #define RASP_ECMPKT_192_DIS 0x00004000 242 #define RASP_ECM2MIU_LPCR_WT 0x00008000 243 244 #define REG_RASP_CLK90K_DIV 0x000C 245 #define REG_RASP_INT_CLR 0x000D 246 #define REG_RASP_INT_ENABLE 0x000E 247 #define REG_RASP_INT_STATUS 0x000F 248 #define RASP_INT_EFRAME_RD_OVF 0x00000001 249 #define RASP_INT_EFRAME_WT_OVF 0x00000002 250 #define RASP_INT_STR2MIU 0x0000000C // 2 BIT FOR WHAT ? 251 #define RASP_INT_PAYLD2MIU 0x00000030 252 #define RASP_INT_ECM2MIU 0x000000C0 253 #define RASP_INT_TIME_WATER_MARK 0x00000100 254 #define RASP_INT_EVENT_WATER_MARK 0x00000200 255 #define RASP_INT_ECM_PKT_RDY 0x00000400 256 #define RASP_INT_PVR2MIU 0x00001800 257 258 #define REG_RASP_STR2MIU_HEAD1_L 0x0010 259 #define REG_RASP_STR2MIU_HEAD1_H 0x0011 260 #define REG_RASP_STR2MIU_TAIL1_L 0x0012 261 #define REG_RASP_STR2MIU_TAIL1_H 0x0013 262 #define REG_RASP_STR2MIU_MID1_L 0x0014 263 #define REG_RASP_STR2MIU_MID1_H 0x0015 264 265 #define REG_RASP_STR2MIU_HEAD2_L 0x0016 266 #define REG_RASP_STR2MIU_HEAD2_H 0x0017 267 #define REG_RASP_STR2MIU_TAIL2_L 0x0018 268 #define REG_RASP_STR2MIU_TAIL2_H 0x0019 269 #define REG_RASP_STR2MIU_MID2_L 0x001A 270 #define REG_RASP_STR2MIU_MID2_H 0x001B 271 272 273 #define REG_RASP_HW_CTRL4 0x001C 274 #define RASP_STREAM_192_EN 0x0001 275 #define RASP_STREAM_LPCR_WLD 0x0002 276 #define RASP_TS_FF_BYPASS 0x0004 277 #define RASP_TS_FF_CLR_OVERFLOW 0x0008 278 #define RASP_TS_FF_FULL_SEL_MASK 0x0070 279 #define RASP_TS_FF_FULL_SEL_SHFT 4 280 #define RASP_TS_STR2MI_WP_LD_DIS 0x0080 281 #define RASP_TS_PAY2MI_WP_LD_DIS 0x0100 282 #define RASP_REC_AT_SYNC_DIS 0x0400 283 #define RASP_AUTO_STREAM_47_48 0x2000 284 285 #define REG_RASP_HW_CTRL5 0x001D 286 287 #define REG_RASP_PIDFLT_N(n) (0x0020 + n) 288 289 #define REG_RASP_EVENT_DESCR_L 0x0050 290 #define REG_RASP_EVENT_DESCR_H 0x0051 291 292 #define REG_RASP_EVENT_PKT_NUM_L 0x0052 293 #define REG_RASP_EVENT_PKT_NUM_H 0x0053 294 #define REG_RASP_EVENT_PKT_TIMER_L 0x0054 295 #define REG_RASP_EVENT_PKT_TIMER_H 0x0055 296 #define REG_RASP_EVENT_PKT_PCR_L 0x0056 297 #define REG_RASP_EVENT_PKT_PCR_H 0x0057 298 #define REG_RASP_EVENT_PKT_PID 0x0058 299 300 #define REG_RASP_PAYLOAD2MIU_HEAD1_L 0x0060 301 #define REG_RASP_PAYLOAD2MIU_HEAD1_H 0x0061 302 #define REG_RASP_PAYLOAD2MIU_TAIL1_L 0x0062 303 #define REG_RASP_PAYLOAD2MIU_TAIL1_H 0x0063 304 #define REG_RASP_PAYLOAD2MIU_MID1_L 0x0064 305 #define REG_RASP_PAYLOAD2MIU_MID1_H 0x0065 306 307 #define REG_RASP_PAYLOAD2MIU_HEAD2_L 0x0066 308 #define REG_RASP_PAYLOAD2MIU_HEAD2_H 0x0067 309 #define REG_RASP_PAYLOAD2MIU_TAIL2_L 0x0068 310 #define REG_RASP_PAYLOAD2MIU_TAIL2_H 0x0069 311 #define REG_RASP_PAYLOAD2MIU_MID2_L 0x006A 312 #define REG_RASP_PAYLOAD2MIU_MID2_H 0x006B 313 314 #define REG_RASP_PAY_LPCR1_BUF_L 0x006C 315 #define REG_RASP_PAY_LPCR1_BUF_H 0x006D 316 #define REG_RASP_PAY_LPCR1_L 0x006E 317 #define REG_RASP_PAY_LPCR1_H 0x006F 318 319 #define REG_RASP_ECM2MIU_HEAD1_L 0x0070 320 #define REG_RASP_ECM2MIU_HEAD1_H 0x0071 321 #define REG_RASP_ECM2MIU_TAIL1_L 0x0072 322 #define REG_RASP_ECM2MIU_TAIL1_H 0x0073 323 #define REG_RASP_ECM2MIU_MID1_L 0x0074 324 #define REG_RASP_ECM2MIU_MID1_H 0x0075 325 326 #define REG_RASP_ECM_LPCR1_BUF_L 0x0076 327 #define REG_RASP_ECM_LPCR1_BUF_H 0x0077 328 #define REG_RASP_ECM_LPCR1_L 0x0078 329 #define REG_RASP_ECM_LPCR1_H 0x0079 330 331 #define REG_RASP_STR_LPCR1_BUF_L 0x007A 332 #define REG_RASP_STR_LPCR1_BUF_H 0x007B 333 #define REG_RASP_STR_LPCR1_L 0x007C 334 #define REG_RASP_STR_LPCR1_H 0x007D 335 336 #define REG_RASP_STATUS 0x007F 337 338 #define REG_RASP_ECM_PID_N(n) (0x0080 + 0x0012 + n) 339 340 #define REG_RASP_ECM_TID (0x0080 + 0x0016) 341 #define REG_RASP_ECM_LOCK_CTRL (0x0080 + 0x0017) 342 #define REG_RASP_CA_INT (0x0080 + 0x0018) 343 #define REG_RASP_ECM_INT_STATE (0x0080 + 0x0019) 344 345 #define REG_RASP_ECM_PID_4 (0x0080 + 0x0030) 346 #define REG_RASP_ECM_PID_5 (0x0080 + 0x0031) 347 348 #define REG_RASP_ECM45_LOCK_CTRL (0x0080 + 0x0032) 349 350 #define REG_RASP_ECM_PACKET_NUM_L (0x0080 + 0x0034) 351 #define REG_RASP_ECM_PACKET_NUM_H (0x0080 + 0x0035) 352 353 #define REG_RASP_PKT_MEET_SIZE_L (0x0080 + 0x003A) 354 #define REG_RASP_PKT_MEET_SIZE_H (0x0080 + 0x003B) 355 #define REG_RASP_PKT_SET (0x0080 + 0x003C) 356 #define RASP_PKT_RESET_NUMBER 0x0100 357 #define RASP_PKT_RESET_TIMER 0x0200 358 359 #define REG_RASP_PAYLOAD_MASK_N(n) (0x0080 + 0x0040 + 2*n) 360 361 #define REG_RASP_EVENT_MASK_N(n) (0x0080 + 0x0060 + 2*n) 362 363 #define REG_RFILEIN_RESET 0x0000 364 #define REG_RFILEIN_RESET_ALL 0x001F 365 366 #define REG_RFILEIN_CTRL_0 0x0001 367 #define REG_RFILEIN_PKT_CHK_SIZE 0x00FF 368 #define REG_RFILEIN_PKT_CHK_SIZE_188 0x00BB 369 #define REG_RFILEIN_PKT_CHK_SIZE_192 0x00BF 370 #define RASP_RFILEIN_PORT_SEL_FILE 0x0100 371 #define RASP_RFILEIN_ALIGN_EN 0x0200 372 #define RASP_RFILEIN_TIMER_EN 0x0400 373 #define RASP_RFILEIN_INPUT_EN 0x0800 374 375 #define RASP_RFILEIN_PKT192_EN 0x1000 376 #define RASP_RFILEIN_PKT192_BLK_DIS 0x2000 377 378 #define REG_RFILEIN_TIMER 0x0002 379 #define REG_RFILEIN_CTRL_1 0x0003 380 #define REG_RFILEIN_LPCR2_WLD 0x0002 381 #define REG_RFILEIN_LPCR2_LOAD 0x0020 382 #define REG_RFILEIN_FLUSH_AUTO 0x0100 383 #define REG_RFILEIN_FLUSH 0x0200 384 #define REG_RFILEIN_TIMER_192FIX 0x0800 //fix 192 mode issue 385 #define REG_RFILEIN_RST_PKT_TSTAMP 0x1000 //reset file in stream timestamp 386 387 388 #define REG_RFILEIN_DTS_CONFIG_0 0x0004 389 #define REG_RFILEIN_DBG_SEL 0x000A 390 391 #define REG_RFILEIN_ADDR_L 0x0020 392 #define REG_RFILEIN_ADDR_H 0x0021 393 #define REG_RFILEIN_SIZE_L 0x0022 394 #define REG_RFILEIN_SIZE_H 0x0023 395 #define REG_RFILEIN_START 0x0024 396 #define RASP_FILEIN_START 0x0001 397 #define REG_RFILEIN_LPCR2_BUF_L 0x0025 398 #define REG_RFILEIN_LPCR2_RD_L 0x0027 399 #define REG_RFILEIN_STREAM_TIMESTAMP_L 0x002f 400 #define REG_RFILEIN_STREAM_TIMESTAMP_H 0x0030 401 402 403 //there are still some registers not defined....maybe type later..... 404 405 #define REG_RFILEIN_CMDQ_STATUS 0x002B 406 #define RFILEIN_CMD_WR_CNT_MASK 0xF 407 #define RFILEIN_CMD_FIFO_FULL (0x1<<6) 408 #define RFILEIN_CMD_FIFO_EMPTY (0x1<<7) 409 #define RFILEIN_CMD_WR_LEVEL_MASK (0x3<<8) 410 #define RFILEIN_CMD_WR_COUNT_MASK (0x1F) 411 412 #define REG_RFILEIN_DBG_L 0x002C 413 #define REG_RFILEIN_DBG_H 0x002D 414 415 // Software 416 #define RASP0_BANK0_REG_CTRL_BASE (0x23600) //0x11B<<9 //bank 0x111B 417 #define RASP0_BANK1_REG_CTRL_BASE (0x23800) //0x11C<<9 //bank 0x111C 418 419 #define RASP0_BANK0_PIDFLT_BASE (RASP0_BANK0_REG_CTRL_BASE+0x80) 420 #define RASP0_BANK1_EVENT_MASK_BASE (RASP0_BANK1_REG_CTRL_BASE+0x180) 421 #define RASP0_BANK1_PAYLOAD_MASK_BASE (RASP0_BANK1_REG_CTRL_BASE+0x100) 422 #define RASP0_BANK1_ECM_PIDFLT_BASE (RASP0_BANK1_REG_CTRL_BASE+0x48) 423 424 425 #define RASP1_BANK0_REG_CTRL_BASE (0x23A00) //0x11D<<9 //bank 0x111D 426 #define RASP1_BANK1_REG_CTRL_BASE (0x23C00) //0x11E<<9 //bank 0x111E 427 428 #define RASP1_BANK0_PIDFLT_BASE (RASP1_BANK0_REG_CTRL_BASE+0x80) 429 #define RASP1_BANK1_EVENT_MASK_BASE (RASP1_BANK1_REG_CTRL_BASE+0x180) 430 #define RASP1_BANK1_PAYLOAD_MASK_BASE (RASP1_BANK1_REG_CTRL_BASE+0x100) 431 #define RASP1_BANK1_ECM_PIDFLT_BASE (RASP1_BANK1_REG_CTRL_BASE+0x48) 432 433 434 // Payload/Event Mask flag 435 #define RASP_BYPASS_MASK 0xffffffff 436 #define RASP_BYPASS_AFE 0x00000001 // adaptation field extension 437 #define RASP_BYPASS_TPD 0x00000002 // transport private data 438 #define RASP_BYPASS_SP 0x00000004 // splicing point 439 #define RASP_BYPASS_OPCR 0x00000008 // OPCR 440 #define RASP_BYPASS_PCR 0x00000010 // PCR 441 #define RASP_BYPASS_ESPI 0x00000020 // elementary stream priority indicator 442 #define RASP_BYPASS_RAI 0x00000040 //random access indicator 443 #define RASP_BYPASS_DI 0x00000080 // discontinue indicator 444 #define RASP_BYPASS_ESOS 0x00000100 // elementary stream not scrambled 445 #define RASP_BYPASS_ESES 0x00000200 // elementary stream even scrambled 446 #define RASP_BYPASS_ESNS 0x00000400 // elementary stream odd scrambled 447 #define RASP_BYPASS_PUSI 0x00000800 // payload unit start indicator 448 #define RASP_BYPASS_FPR 0x00001000 // first packet recorded 449 #define RASP_BYPASS_RASP_Tick 0x80000000 // rasp tick 450 451 //Ctrl MASK 452 #define RASP_CTRL_MASK 0x0000ffff 453 454 typedef struct _REG32 455 { 456 volatile MS_U16 L; 457 volatile MS_U16 empty_L; 458 volatile MS_U16 H; 459 volatile MS_U16 empty_H; 460 } REG32; 461 462 typedef struct _REG16 463 { 464 volatile MS_U16 data; 465 volatile MS_U16 _resv; 466 } REG16; 467 468 typedef enum 469 { 470 E_NDSRASP_FILEIN = 0, 471 E_NDSRASP_LIVEIN, 472 } FILEIN_TSIF_Mode; 473 474 typedef REG16 REG_PidFlt; 475 476 typedef struct _REG_RASP 477 { 478 //---------------------------------------------- 479 // 0xBF223600 MIPS direct access 480 //---------------------------------------------- 481 REG32 RASP_PktTimer; // 0xbf201c00 0x00 482 REG32 RASP_PktNum; // 0xbf201c08 0x02 483 REG16 RASP_CorptFromTo; // 0xbf201c10 0x04 484 #define RASP_FROMTO_MASK 0x00FF 485 #define RASP_TO_SHIFT 8 486 REG16 RASP_CorptData_PktSize2; // 0xbf201c14 0x05 487 #define RASP_CORPT_DATA 0x00FF 488 #define RASP_PKT_SIZE 0xFF00 489 #define RASP_PKT_SIZE_188 0xBB 490 #define RASP_PKT_SHIFT 8 491 REG16 RASP_EventlogCtrlStatus; // 0xbf201c18 0x06 492 #define RASP_EVENT_FIFO_NUM_MASK 0x0000001F 493 #define RASP_EVENT_FIFO_FULL 0X00000020 494 #define RASP_EVENT_FIFO_EMPTY 0x00000040 495 #define RASP_EVENT_FIFO_RDLV_MASK 0x00000300 496 #define RASP_EVENT_FIFO_RDLV_SHIFT 8 497 #define RASP_EVENT_FIFO_WTLV_MASK 0x00000C00 498 #define RASP_EVENT_FIFO_WTLV_SHIFT 10 499 #define RASP_EVENT_FIFO_RD_OVF 0x00001000 500 #define RASP_EVENT_FIFO_WT_OVF 0x00002000 501 502 REG16 RASP_PktChkSize2_SyncByte2; // 0xbf201c1c 0x07 503 REG16 RASP_HW_CTRL0; // 0xbf201c20 0x08 504 #define RASP_SW_RESET 0x00000001 505 #define RASP_TSIF2_ENABLE 0x00000002 506 #define RASP_TSIF2_DATA_SWP 0x00000004 507 #define RASP_TSIF2_PARA_SEL 0x00000008 508 #define RASP_TSIF2_EXT_SYNC 0x00000010 509 #define RASP_FILEIN_EN 0x00000020 510 #define RASP_RISING_SYNC_DETECT 0x00000080 511 #define RASP_FALLING_VALID_DETECT 0x00000100 512 #define RASP_CLR_EVENT_OVERFLOW 0x00000200 513 #define RASP_REC_EVENT_FIFO_EN 0x00001000 514 #define RASP_CLEAR_ECM_PKT_NUM 0x00002000 515 516 REG16 RASP_HW_CTRL1; // 0xbf201c24 0x09 517 #define RASP_REC_PID 0x00000001 518 #define RASP_STR2MIU_EN 0x00000002 519 #define RASP_PINGPONG_EN 0x00000004 520 #define RASP_ALT_TS_SIZE_EN 0x00000080 521 #define RASP_STR2MIU_RST_WADDR 0x00000010 522 #define RASP_SERIAL_EXT_SYNC_1T 0x00000400 523 //192 aligement 524 #define RASP_BURST_LEN_MASK 0x00001800 525 #define RASP_BURST_LEN_SHIFT 0x0000000B 526 #define RASP_BURST_LEN 0x00000002 527 528 #define RASP_EVENT_FIFO_READ 0x00008000 529 530 531 532 REG16 RASP_HW_CTRL2; // 0xbf201c28 0x0a 533 #define RASP_INT_TIMER_EN 0x00000001 534 #define RASP_INT_EVENT_EN 0x00000002 535 #define RASP_INT_TIMER_MASK 0x0000000C 536 #define RASP_INT_TIMER_SHIFT 2 537 #define RASP_INT_EVENT_MASK 0x000001F0 538 #define RASP_INT_EVENT_SHIFT 4 539 #define RASP_PAYLOAD_BURST_LEN 0x00000400 540 #define RASP_ECM_BURST_LEN 0x00001000 541 542 REG16 RASP_HW_CTRL3; // 0xbf201c2c 0x0b 543 #define RASP_PAYLD2MIU_EN 0x00000001 544 #define RASP_PAYLD2MIU_PINGPONE 0x00000002 545 #define RASP_PAYLD2MIU_SWAP 0x00000004 546 #define RASP_PAYLD2MIU_RST_WADDR 0x00000008 547 #define RASP_PAYLD2MIU_LPCR_WT 0x00000080 548 //#define RASP_ECM2MIU_EN 0X00000100 549 //#define RASP_ECM2MIU_RST_WADDR 0X00000800 550 //#define RASP_ECM2MIU_LPCR_WT 0X00008000 551 552 553 REG16 RASP_C90K_Divisor; // 0xbf201c30 0x0c 554 REG16 RASP_Int_CLR; // 0xbf201c34 0x0d 555 REG16 RASP_Int_EN; // 0xbf201c38 0x0e 556 REG16 RASP_Int_Status; // 0xbf201c3c 0x0f 557 558 559 REG32 RASP_Str2miu_Head; // 0xbf201c40 0x10 560 REG32 RASP_Str2miu_Tail; // 0xbf201c48 0x12 561 REG32 RASP_Str2miu_Mid; // 0xbf201c50 0x14 562 REG32 RASP_Str2miu_Head2; // 0xbf201c58 0x16 563 REG32 RASP_Str2miu_Tail2; // 0xbf201c60 0x18 564 REG32 RASP_Str2miu_Mid2; // 0xbf201c68 0x1a 565 REG16 RASP_HW_CTRL4; // 0xbf201c70 0x1c 566 #define RASP_STREAM_192_EN 0x0001 567 #define RASP_STREAM_LPCR_WLD 0x0002 568 #define RASP_TS_FF_BYPASS 0x0004 569 #define RASP_TS_FF_CLR_OVERFLOW 0x0008 570 #define RASP_TS_FF_FULL_SEL_MASK 0x0070 571 #define RASP_TS_FF_FULL_SEL_SHFT 4 572 #define RASP_TS_STR2MI_WP_LD_DIS 0x0080 573 #define RASP_TS_PAY2MI_WP_LD_DIS 0x0100 574 #define RASP_REC_AT_SYNC_DIS 0x0400 575 #define RASP_AUTO_STREAM_47_48 0x2000 576 577 REG16 RASP_HW_CTRL5; // 0xbf201c74 0x1d 578 579 REG16 _bf201c78; // 0xbf201c78 0x1e 580 581 REG16 RASP_HW_Status1; // 0xbf201c7C 0x1f 582 REG16 RASP_Pidflt_0; // 0xbf201c80 0x20 583 REG16 RASP_Pidflt_1; // 0xbf201c84 0x21 584 REG16 RASP_Pidflt_2; // 0xbf201c88 0x22 585 REG16 RASP_Pidflt_3; // 0xbf201c8c 0x23 586 REG16 RASP_Pidflt_4; // 0xbf201c90 0x24 587 REG16 RASP_Pidflt_5; // 0xbf201c94 0x25 588 REG16 RASP_Pidflt_6; // 0xbf201c98 0x26 589 REG16 RASP_Pidflt_7; // 0xbf201c9c 0x27 590 REG16 RASP_Pidflt_8; // 0xbf201ca0 0x28 591 REG16 RASP_Pidflt_9; // 0xbf201ca4 0x29 592 REG16 RASP_Pidflt_a; // 0xbf201ca8 0x2a 593 REG16 RASP_Pidflt_b; // 0xbf201cac 0x2b 594 REG16 RASP_Pidflt_c; // 0xbf201cb0 0x2c 595 REG16 RASP_Pidflt_d; // 0xbf201cb4 0x2d 596 REG16 RASP_Pidflt_e; // 0xbf201cb8 0x2e 597 REG16 RASP_Pidflt_f; // 0xbf201cbc 0x2f 598 REG16 RASP_Pidflt_10; // 0xbf201cc0 0x30 599 REG16 RASP_Pidflt_11; // 0xbf201cc4 0x31 600 REG16 RASP_Pidflt_12; // 0xbf201cc8 0x32 601 REG16 RASP_Pidflt_13; // 0xbf201ccc 0x33 602 REG16 RASP_Pidflt_14; // 0xbf201cd0 0x34 603 REG16 RASP_Pidflt_15; // 0xbf201cd4 0x35 604 REG16 RASP_Pidflt_16; // 0xbf201cd8 0x36 605 REG16 RASP_Pidflt_17; // 0xbf201cdc 0x37 606 #define RASP_PID_PKT_CORPT_EN 0x2000 607 608 REG16 _bf201d00[0x50-0x38]; // 0xbf201ce0-bf201d38 0x38-0x4f 609 610 REG32 RASP_EventDescriptor; // 0xbf201d40 0x50 611 REG32 RASP_EventPktNum; // 0xbf201d48 0x52 612 REG32 RASP_EventPktTimer; // 0xbf201d50 0x54 613 REG32 RASP_EventPktPCR; // 0xbf201d58 0x56 614 REG16 RASP_EventPktPID; // 0xbf201d60 0x58 615 616 REG16 _bf201d68_bf201d68[0x60-0x59]; // 0xbf201d64-bf201d7c 0x59-0x5f 617 618 REG32 RASP_Payload2miu_Head; // 0xbf201d80 0x60 619 REG32 RASP_Payload2miu_Tail; // 0xbf201d88 0x62 620 REG32 RASP_Payload2miu_Mid; // 0xbf201d90 0x64 621 REG32 RASP_Payload2miu_Head2; // 0xbf201d98 0x66 622 REG32 RASP_Payload2miu_Tail2; // 0xbf201da0 0x68 623 REG32 RASP_Payload2miu_Mid2; // 0xbf201da8 0x6a 624 625 REG32 RASP_PayLPCR1Buf; // 0xbf201db0 0x6c 626 REG32 RASP_PayLPCR1; // 0xbf201db8 0x6e 627 REG32 RASP_Ecm2miu_Head; // 0xbf201dc0 0x70 628 REG32 RASP_Ecm2miu_Tail; // 0xbf201dc8 0x72 629 REG32 RASP_Ecm2miu_Mid; // 0xbf201dd0 0x74 630 REG32 RASP_EcmLPCR1Buf; // 0xbf201dd8 0x76 631 REG32 RASP_EcmLPCR1; // 0xbf201de0 0x78 632 REG32 RASP_StrLPCR1Buf; // 0xbf201de8 0x7a 633 REG32 RASP_StrLPCR1; // 0xbf201df0 0x7c 634 635 REG32 _bf201db8; // 0xbf201df8 0x7e-0x7f 636 637 //---------------------------------------------- 638 // 0xBF223800 MIPS direct access 639 //---------------------------------------------- 640 REG16 _bf201e00_bf201e44[0x12-0x0]; // 0xbf201e00-bf201e44 0x00-0x11 641 642 REG16 RASP_EcmPidflt_0; // 0xbf201e48 0x12 643 REG16 RASP_EcmPidflt_1; // 0xbf201e4c 0x13 644 REG16 RASP_EcmPidflt_2; // 0xbf201e50 0x14 645 REG16 RASP_EcmPidflt_3; // 0xbf201e54 0x15 646 REG16 RASP_Ecm_reg_16; // 0xbf201e58 0x16 647 REG16 RASP_Ecm_reg_17; // 0xbf201e5c 0x17 648 649 REG16 RASP_Ecm_reg_18; // 0xbf201e60 0x18 650 REG16 RASP_Ecm_reg_19; // 0xbf201e64 0x19 651 652 REG32 RASP_EcmDummy1a; // 0xbf201e68 0x1a 653 REG32 RASP_EcmDummy1c; // 0xbf201e70 0x1c 654 REG32 RASP_EcmDummy1e; // 0xbf201e78 0x1e 655 REG32 RASP_EcmDummy20; // 0xbf201e80 0x20 656 REG32 RASP_EcmDummy22; // 0xbf201e88 0x22 657 REG32 RASP_EcmDummy24; // 0xbf201e90 0x24 658 REG32 RASP_EcmDummy26; // 0xbf201e98 0x26 659 REG32 RASP_EcmDummy28; // 0xbf201ea0 0x28 660 REG32 RASP_EcmDummy2a; // 0xbf201ea8 0x2a 661 REG32 RASP_EcmDummy2c; // 0xbf201eb0 0x2c 662 REG32 RASP_EcmDummy2e; // 0xbf201eb8 0x2e 663 664 REG16 RASP_EcmPidflt_4; // 0xbf201ec0 0x30 665 REG16 RASP_EcmPidflt_5; // 0xbf201ec4 0x31 666 REG16 RASP_Ecm_reg_32; // 0xbf201ec8 0x32 667 REG16 RASP_EcmDummy33; // 0xbf201ecc 0x33 668 669 REG32 RASP_EcmPktNum; // 0xbf201ed0 0x34 670 671 REG32 RASP_EcmDummy36; // 0xbf201ed8 0x36 672 REG32 RASP_EcmDummy38; // 0xbf201ee0 0x38 673 REG32 RASP_EcmDummy3a; // 0xbf201ee8 0x3a 674 REG32 RASP_EcmDummy3c; // 0xbf201ef0 0x3c 675 REG32 RASP_EcmDummy3e; // 0xbf201ef8 0x3e 676 677 REG32 RASP_PayLoadMask_0; // 0xbf201f00 0x40 678 REG32 RASP_PayLoadMask_1; // 0xbf201f08 0x42 679 REG32 RASP_PayLoadMask_2; // 0xbf201f10 0x44 680 REG32 RASP_PayLoadMask_3; // 0xbf201f18 0x46 681 REG32 RASP_PayLoadMask_4; // 0xbf201f20 0x48 682 REG32 RASP_PayLoadMask_5; // 0xbf201f28 0x4a 683 REG32 RASP_PayLoadMask_6; // 0xbf201f30 0x4c 684 REG32 RASP_PayLoadMask_7; // 0xbf201f38 0x4e 685 REG32 RASP_PayLoadMask_8; // 0xbf201f40 0x50 686 REG32 RASP_PayLoadMask_9; // 0xbf201f48 0x52 687 REG32 RASP_PayLoadMask_a; // 0xbf201f50 0x54 688 REG32 RASP_PayLoadMask_b; // 0xbf201f58 0x56 689 REG32 RASP_PayLoadMask_c; // 0xbf201f60 0x58 690 REG32 RASP_PayLoadMask_d; // 0xbf201f68 0x5a 691 REG32 RASP_PayLoadMask_e; // 0xbf201f70 0x5c 692 REG32 RASP_PayLoadMask_f; // 0xbf201f78 0x5e 693 694 REG32 RASP_EventMask_0; // 0xbf201f80 0x60 695 REG32 RASP_EventMask_1; // 0xbf201f88 0x62 696 REG32 RASP_EventMask_2; // 0xbf201f90 0x64 697 REG32 RASP_EventMask_3; // 0xbf201f98 0x66 698 REG32 RASP_EventMask_4; // 0xbf201f70 0x68 699 REG32 RASP_EventMask_5; // 0xbf201f78 0x6a 700 REG32 RASP_EventMask_6; // 0xbf201f80 0x6c 701 REG32 RASP_EventMask_7; // 0xbf201f88 0x6e 702 REG32 RASP_EventMask_8; // 0xbf201f90 0x70 703 REG32 RASP_EventMask_9; // 0xbf201f98 0x72 704 REG32 RASP_EventMask_a; // 0xbf201fa0 0x74 705 REG32 RASP_EventMask_b; // 0xbf201fa8 0x76 706 REG32 RASP_EventMask_c; // 0xbf201fb0 0x78 707 REG32 RASP_EventMask_d; // 0xbf201fb8 0x7a 708 REG32 RASP_EventMask_e; // 0xbf201fc0 0x7c 709 REG32 RASP_EventMask_f; // 0xbf201fc8 0x7e 710 } REG_RASP; 711 712 #endif // _RASP_REG_H_ 713