1 #ifndef _TSP2_REG_H_ 2 #define _TSP2_REG_H_ 3 typedef struct _REG32 4 { 5 volatile MS_U16 low; 6 volatile MS_U16 _null_l; 7 volatile MS_U16 high; 8 volatile MS_U16 _null_h; 9 } REG32; 10 11 typedef struct _REG16 12 { 13 volatile MS_U16 data; //[jerry] not to name "low" 14 volatile MS_U16 _null; 15 } REG16; 16 17 typedef struct _TSP32 18 { 19 volatile MS_U32 reg32; 20 } TSP32; 21 22 23 //######################################################################### 24 //#### Hardware Capability Macro Start 25 //######################################################################### 26 27 #define TSP_TSIF_NUM 4 28 #define TSP_PVRENG_NUM 4 29 #define TSP_PVR_IF_NUM 4 30 #define TSP_OTVENG_NUM 4 31 #define STC_ENG_NUM 2 32 #define TSP_PCRFLT_NUM STC_ENG_NUM 33 34 #define TSP_PIDFLT_NUM 192 35 #define TSP_SECFLT_NUM 192 36 #define TSP_SECBUF_NUM 192 37 38 #define TSP_MERGESTREAM_NUM 8 39 40 //@NOTE: accroding to width of FW/VQ/SEC buffer base addr , lower / upper bound may be different 41 #define TSP_FW_BUF_LOW_BUD 0 42 #define TSP_FW_BUF_UP_BUD ((1ULL << 32) - 1) // base addr: bits[31:4] , unit: 16-bytes (bits[3:0]) 43 // base addr = {reg_dma_raddr_msb(8-bits),reg_dma_raddr(16-bits),4'b0(4-bits)} 44 #define TSP_VQ_BUF_LOW_BUD 0 45 #define TSP_VQ_BUF_UP_BUD ((1ULL << 32) - 1) // base addr: bits[31:0] , unit: 1-byte 46 #define TSP_SEC_BUF_LOW_BUD 0 47 #define TSP_SEC_BUF_UP_BUD ((1ULL << 32) - 1) // base addr: bits[31:0] , unit: 1-byte 48 49 50 //@Note : Compatible for K6 drvtsp2.c HWCL of PCR2,PCR3 51 #define TSP_HWINT3_PCR2_UPDATE_END_EN 0x0000 52 #define TSP_HWINT3_PCR3_UPDATE_END_EN 0x0000 53 #define TSP_HWINT3_PCR2_UPDATE_END 0x0000 54 #define TSP_HWINT3_PCR3_UPDATE_END 0x0000 55 #define TSP_HWINT3_ALL 0x0000 56 57 58 59 //######################################################################### 60 //#### Hardware Capability Macro End 61 //######################################################################### 62 63 64 // PID Filter 65 typedef TSP32 REG_PidFlt; // 0x210000 66 67 // TSIF 68 #define TSP_PIDFLT_TSIF_MASK 0x0000E000 69 #define TSP_PIDFLT_TSIF_SHFT 13 70 71 #define TSP_FILTER_DEPTH 16 72 73 // CLKGEN0 Bank:0x100B 74 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x1600 + ((addr)<<2)))) 75 #define REG_CLKGEN0_DC0_SYTNTH 0x05 76 #define REG_CLKGEN0_STC_CW_SEL 0x0002 77 #define REG_CLKGEN0_STC_CW_EN 0x0004 78 #define REG_CLKGEN0_STC1_CW_SEL 0x0200 79 #define REG_CLKGEN0_STC1_CW_EN 0x0400 80 #define REG_CLKGEN0_DC0_STC_CW_L 0x06 81 #define REG_CLKGEN0_DC0_STC_CW_H 0x07 82 #define REG_CLKGEN0_DC0_STC1_CW_L 0x08 83 #define REG_CLKGEN0_DC0_STC1_CW_H 0x09 84 85 #define REG_CLKGEN0_S2P_IN_CLK_SRC 0x0C 86 #define REG_CLKGEN0_S2P_IN_CLK_SHIFT 0 87 #define REG_CLKGEN0_S2P1_IN_CLK_SHIFT 8 88 89 #define REG_CLKGEN0_S2P_IN_CLK_MASK 0x1F 90 #define REG_CLKGEN0_S2P_IN_CLK_DISABLE 0x0001 91 #define REG_CLKGEN0_S2P_IN_CLK_INVERT 0x0002 92 #define REG_CLKGEN0_S2P_IN_CLK_SRC_SHIFT 2 93 #define REG_CLKGEN0_S2P_IN_CLK_SRC_MASK 0x7 94 95 #define REG_CLKGEN0_TSO0_CLK 0x27 96 #define REG_CLKGEN0_TSO0_SHIFT 0 97 #define REG_CLKGEN0_TS0_CLK 0x28 98 #define REG_CLKGEN0_TS0_SHIFT 0 99 #define REG_CLKGEN0_TS1_CLK 0x28 100 #define REG_CLKGEN0_TS1_SHIFT 8 101 #define REG_CLKGEN0_TS2_CLK 0x29 102 #define REG_CLKGEN0_TS2_SHIFT 0 103 #define REG_CLKGEN0_TS3_CLK 0x29 104 #define REG_CLKGEN0_TS3_SHIFT 8 105 #define REG_CLKGEN0_TS_MASK 0x003F // 4 bit each 106 #define REG_CLKGEN0_TS_DISABLE 0x0001 107 #define REG_CLKGEN0_TS_INVERT 0x0002 108 #define REG_CLKGEN0_TS_SRC_SHIFT 2 109 #define REG_CLKGEN0_TS_SRC_MASK 0x000F 110 #define REG_CLKGEN0_TS_SRC_EXT0 0x0000 111 #define REG_CLKGEN0_TS_SRC_EXT1 0x0001 112 #define REG_CLKGEN0_TS_SRC_EXT2 0x0002 113 #define REG_CLKGEN0_TS_SRC_EXT3 0x0003 114 #define REG_CLKGEN0_TS_SRC_EXT4 0x0004 115 #define REG_CLKGEN0_TS_SRC_EXT5 0x0005 116 #define REG_CLKGEN0_TS_SRC_EXT6 0x0006 117 #define REG_CLKGEN0_TS_SRC_TSO0 0x0007 118 //@NOTE Not support internal demod in KANO 119 #define REG_CLKGEN0_TS_SRC_DMD0 0x000F 120 121 //get TSP Clk Gen bank 122 #define REG_CLKGEN0_TSP_CLK 0x2A 123 #define REG_CLKGEN0_TSP_CLK_MASK 0x001F 124 #define REG_CLKGEN0_TSP_SHIFT 0 125 #define REG_CLKGEN0_TSP_DISABLE 0x0001 126 #define REG_CLKGEN0_TSP_INVERT 0x0002 127 //SRC 128 #define REG_CLKGEN0_TSP_SRC_SHIFT 2 129 #define REG_CLKGEN0_TSP_SRC_MASK 0x0007 130 #define REG_CLKGEN0_TSP_SRC_192MHZ 0x0000 131 #define REG_CLKGEN0_TSP_SRC_172MHZ 0x0001 132 #define REG_CLKGEN0_TSP_SRC_144MHZ 0x0002 133 #define REG_CLKGEN0_TSP_SRC_108MHZ 0x0003 134 #define REG_CLKGEN0_TSP_SRC_XTAL 0x0007 135 136 //get STC0/1 Clk Gen bank 137 #define REG_CLKGEN0_STC0_CLK 0x2A 138 #define REG_CLKGEN0_STC0_MASK 0x0F00 139 #define REG_CLKGEN0_STC0_SHIFT 8 140 #define REG_CLKGEN0_STC1_CLK 0x2A 141 #define REG_CLKGEN0_STC1_MASK 0xF000 142 #define REG_CLKGEN0_STC1_SHIFT 12 143 144 #define REG_CLKGEN0_STC_DISABLE 0x0001 145 #define REG_CLKGEN0_STC_INVERT 0x0002 146 //SRC 147 #define REG_CLKGEN0_STC_SRC_SHIFT 2 148 #define REG_CLKGEN0_STC_SRC_MASK 0x0003 149 #define REG_CLKGEN0_STC_SRC_SYNTH 0x0000 150 #define REG_CLKGEN0_STC_SRC_ONE 0x0001 151 #define REG_CLKGEN0_STC_SRC_27M 0x0002 152 #define REG_CLKGEN0_STC_SRC_XTAL 0x0003 153 154 #define REG_CLKGEN0_STAMP_CLK 0x2F 155 #define REG_CLKGEN0_STAMP_MASK 0x0F00 156 #define REG_CLKGEN0_STAMP_SHIFT 8 157 #define REG_CLKGEN0_STAMP_DISABLE 0x0001 158 #define REG_CLKGEN0_STAMP_INVERT 0x0002 159 160 #define REG_CLKGEN0_PARSER_CLK 0x39 161 #define REG_CLKGEN0_PARSER_MASK 0x0F00 162 #define REG_CLKGEN0_PARSER_SHIFT 8 163 #define REG_CLKGEN0_PARSER_DISABLE 0x0001 164 #define REG_CLKGEN0_PARSER_INVERT 0x0002 165 166 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x3c00UL + ((addr)<<2)))) 167 #define REG_TOP_TS0_MUX 0x38 168 #define REG_TOP_TS0_SHIFT 0x0 169 #define REG_TOP_TS1_MUX 0x38 170 #define REG_TOP_TS1_SHIFT 0x4 171 #define REG_TOP_TS2_MUX 0x38 172 #define REG_TOP_TS2_SHIFT 0x8 173 #define REG_TOP_TS3_MUX 0x38 174 #define REG_TOP_TS3_SHIFT 0xC 175 176 177 #define REG_TOP_TSO0_MUX 0x3A 178 #define REG_TOP_TSO0_SHIFT 0 179 180 #define REG_TOP_TS_SRC_MASK 0x000F 181 #define REG_TOP_TS_SRC_EXT0 0x0000 182 #define REG_TOP_TS_SRC_EXT1 0x0001 183 #define REG_TOP_TS_SRC_EXT2 0x0002 184 #define REG_TOP_TS_SRC_EXT3 0x0003 185 #define REG_TOP_TS_SRC_EXT4 0x0004 186 #define REG_TOP_TS_SRC_EXT5 0x0005 187 #define REG_TOP_TS_SRC_EXT6 0x0006 188 #define REG_TOP_TS_SRC_TSO0 0x0007 189 //@NOTE Not support internal demod in KANO 190 #define REG_TOP_TS_SRC_DMD0 0x0008 191 192 #define REG_TOP_TSO4_5_MUX 0x3B 193 #define REG_TOP_TSO4_SHIFT 0 194 #define REG_TOP_TSO4_MASK 0x0003 195 #define REG_TOP_TSO5_SHIFT 4 196 #define REG_TOP_TSO5_MASK 0x0003 197 198 #define REG_TOP_TS_PADMUX_MODE 0x02 199 #define REG_TOP_TS0MODE_MASK 0x1 200 #define REG_TOP_TS0MODE_SHIFT 0 201 #define REG_TOP_TS0MODE_PARALLEL 1 202 #define REG_TOP_TS1MODE_MASK 0x3 203 #define REG_TOP_TS1MODE_SHIFT 1 204 #define REG_TOP_TS1MODE_INPUT 1 205 #define REG_TOP_TS2MODE_MASK 0x3 206 #define REG_TOP_TS2MODE_SHIFT 3 207 #define REG_TOP_TS2MODE_PARALLEL 1 208 #define REG_TOP_TS2MODE_4WIRED 2 209 #define REG_TOP_TS2MODE_3WIRED 3 210 211 #define REG_TOP_TS_OUTPUT_MODE 0x07 212 #define REG_TOP_TS_OUT_MODE_MASK 0x3 213 #define REG_TOP_TS_OUT_MODE_SHIFT 14 214 #define REG_TOP_TS_OUT_MODE_TSO 1 215 #define REG_TOP_TS_OUT_MODE_S2P 2 216 #define REG_TOP_TS_OUT_MODE_S2P1 3 217 218 #define REG_TOP_TSP_BOOT_CLK_SEL 0x54 219 #define REG_TOP_TSP_BOOT_CLK_SEL_MASK 0x0100 220 #define REG_TOP_TSP_BOOT_CLK_SEL_TSP 0x0000 221 222 #define REG_TOP_TSP_3WIRE_MODE 0x11 223 #define REG_TOP_TSP_TS0_3WIRE_EN 0x0001 224 #define REG_TOP_TSP_TS1_3WIRE_EN 0x0002 225 #define REG_TOP_TSP_TS2_3WIRE_EN 0x0400 226 #define REG_TOP_TSP_TS3_3WIRE_EN 0x0800 227 228 229 230 #define TSP_MMFI_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x27E00 + ((addr)<<2)))) 231 #define REG_MMFI_TSP_SEL_SRAM 0x70 232 #define REG_MMFI_TSP_SEL_SRAM_EN 0x0002 233 234 #define TSP_TSO_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0xE0C00 + ((addr)<<2)))) 235 #define REG_TSO_TSP_CONFIG0 0x1C 236 #define REG_TSO_TSP_S2P_MASK 0x001F 237 #define REG_TSO_TSP_S2P_EN 0x0001 238 #define REG_TSO_TSP_S2P_TS_SIN_C0 0x0002 239 #define REG_TSO_TSP_S2P_TS_SIN_C1 0x0004 240 #define REG_TSO_TSP_S2P_3WIRE 0x0008 241 #define REG_TSO_TSP_BYPASS_S2P 0x0010 242 243 #define REG_TSO_TSP_S2P1_MASK 0x1F00 244 #define REG_TSO_TSP_S2P1_EN 0x0100 245 #define REG_TSO_TSP_S2P1_TS_SIN_C0 0x0200 246 #define REG_TSO_TSP_S2P1_TS_SIN_C1 0x0400 247 #define REG_TSO_TSP_S2P1_3WIRE 0x0800 248 #define REG_TSO_TSP_BYPASS_S2P1 0x1000 249 250 251 typedef struct _REG_SecFlt 252 { 253 TSP32 Ctrl; 254 // Software Usage Flags 255 #define TSP_SECFLT_USER_MASK 0x00000007 256 #define TSP_SECFLT_USER_SHFT 0 257 #define TSP_SECFLT_USER_NULL 0x0 258 #define TSP_SECFLT_USER_SEC 0x1 259 #define TSP_SECFLT_USER_PES 0x2 260 #define TSP_SECFLT_USER_PKT 0x3 261 #define TSP_SECFLT_USER_PCR 0x4 262 #define TSP_SECFLT_USER_TTX 0x5 263 /* 264 #define TSP_SECFLT_USER_EMM 0x6 265 #define TSP_SECFLT_USER_ECM 0x7 266 #define TSP_SECFLT_USER_OAD 0x8 267 */ 268 269 #define TSP_SEC_MATCH_INV 0x00000008 // HW 270 271 // for 272 // TSP_SECFLT_TYPE_SEC 273 // TSP_SECFLT_TYPE_PES 274 // TSP_SECFLT_TYPE_PKT 275 // TSP_SECFLT_TYPE_TTX 276 // TSP_SECFLT_TYPE_OAD 277 #define TSP_SECFLT_MODE_MASK 0x00000030 // software implementation 278 #define TSP_SECFLT_MODE_SHFT 4 279 #define TSP_SECFLT_MODE_CONTI 0x0 // SEC 280 #define TSP_SECFLT_MODE_ONESHOT 0x1 281 #define TSP_SECFLT_MODE_CRCCHK 0x2 282 // for TSP_SECFLT_TYPE_PCR 283 #define TSP_SECFLT_PCRRST 0x00000010 //[OBSOLETED] PCR 284 285 286 //[NOTE] update section filter 287 // It's not recommended for user updating section filter control register 288 // when filter is enable. There may be race condition. 289 #define TSP_SECFLT_STATE_MASK 0x000000C0 // software implementation 290 #define TSP_SECFLT_STATE_SHFT 6 291 #define TSP_SECFLT_STATE_OVERFLOW 0x1 292 #define TSP_SECFLT_STATE_DISABLE 0x2 293 294 #define TSP_SECFLT_BEMASK 0x0000FF00 //[Reserved] 295 296 297 // for 298 // TSP_SECFLT_SEL_BUF 299 #define TSP_SECFLT_SECBUF_MASK 0xFF000000 // [31:26] secbuf id 300 #define TSP_SECFLT_SECBUF_SHFT 24 301 #define TSP_SECFLT_SECBUF_MAX 0xFF // software usage 302 303 TSP32 Match[TSP_FILTER_DEPTH/sizeof(TSP32)]; 304 TSP32 Mask[TSP_FILTER_DEPTH/sizeof(TSP32)]; 305 /* 306 TSP32 BufStart; 307 TSP32 BufEnd; 308 TSP32 BufRead; 309 TSP32 BufWrite; 310 TSP32 BufCur; 311 */ 312 TSP32 _x24[(0x38-0x24)/sizeof(TSP32)]; // (0x00211024-0x0021103B)/4 313 314 TSP32 RmnCnt; 315 #define TSP_SECFLT_ALLOC_MASK 0x80000000 316 #define TSP_SECFLT_ALLOC_SHFT 31 317 #define TSP_SECFLT_OWNER_MASK 0x70000000 318 #define TSP_SECFLT_OWNER_SHFT 24 319 320 #define TSP_SECFLT_MODE_AUTO_CRCCHK 0x00100000 //sec flt mode bits are not enough, arbitrarily occupy here 321 322 #define TSP_SECBUF_RMNCNT_MASK 0x0000FFFF // TS/PES length 323 #define TSP_SECBUF_RMNCNT_SHFT 0 324 325 /* 326 // for 327 // TSP_SECFLT_TYPE_ECM 328 #define TSP_SECFLT_ECM_IDX_SHFT 16 329 #define TSP_SECFLT_ECM_IDX_MASK 0x00070000 330 #define TSP_SECFLT_ECM_IDX_NULL 0x00000007 // only alow 0 .. 5 331 */ 332 333 TSP32 CRC32; 334 TSP32 NMask[TSP_FILTER_DEPTH/sizeof(MS_U32)]; 335 TSP32 _x50[(0x80-0x50)/sizeof(TSP32)]; // (0x00211050-0x0021107F)/4 336 } REG_SecFlt; 337 338 typedef struct _REG_SecBuf 339 { 340 TSP32 Start; 341 #define TSP_SECBUF_START_MASK 0x1FFFFFF0 //section buffers of kaiser and keltic are "4" bits aligment 342 #define TSP_SECBUF_OWNER_MASK 0x60000000 343 #define TSP_SECBUF_OWNER_SHFT 29 344 #define TSP_SECBUF_ALLOC_MASK 0x80000000 345 #define TSP_SECBUF_ALLOC_SHFT 31 346 TSP32 End; 347 TSP32 Read; 348 TSP32 Write; 349 TSP32 Cur; 350 TSP32 _x38[(0xA4-0x38)/sizeof(TSP32)]; // (0x0021103C-0x002110A4)/4 351 } REG_SecBuf; 352 353 typedef struct _REG_Pid 354 { // CPU(byte) RIU(index) MIPS(0x1500/2+RIU)*4 355 REG_PidFlt Flt[TSP_PIDFLT_NUM]; // 0x00210000-0x00210007C 356 } REG_Pid; 357 358 typedef struct _REG_Sec 359 { // CPU(byte) RIU(index) MIPS(0x1500/2+RIU)*4 360 REG_SecFlt Flt[TSP_SECFLT_NUM]; 361 } REG_Sec; 362 363 364 typedef struct _REG_Buf 365 { 366 REG_SecBuf Buf[TSP_SECFLT_NUM]; 367 } REG_Buf; 368 369 370 //@NOTE TSP 0~1 371 typedef struct _REG_Ctrl 372 { 373 //---------------------------------------------- 374 // 0xBF802A00 MIPS direct access 375 //---------------------------------------------- 376 // Type Name Index(word) CPU(byte) MIPS(0x1500/2+index)*4 377 REG16 _xbf202a00; // 0xbf802a00 0x00 378 REG32 Str2mi_head2pvr1; // 0xbf802a04 0x01 379 #define TSP_HW_PVR1_BUF_HEAD2_MASK 0x0FFFFFFF 380 381 REG32 Str2mi_mid2pvr1; // 0xbf802a0c 0x03 ,wptr & mid share same register 382 #define TSP_HW_PVR1_BUF_MID2_MASK 0x0FFFFFFF 383 384 REG32 Str2mi_tail2pvr1; // 0xbf802a14 0x05 385 #define TSP_HW_PVR1_BUF_TAIL2_MASK 0x0FFFFFFF 386 387 REG32 Pcr_L; // 0xbf802a1c 0x07 388 #define TSP_PCR64_L32_MASK 0xFFFFFFFF 389 390 REG32 Pcr_H; // 0xbf802a24 0x09 391 #define TSP_PCR64_H32_MASK 0xFFFFFFFF // PCR64 Middle 64 392 393 REG16 Mobf_Filein_Idx; // 0xbf802a2c 0x0b 394 #define TSP_MOBF_FILEIN_MASK 0x0000001F 395 396 REG32 _xbf202a2c; // 0xbf802a30 0x0c 397 398 REG32 PVR2_Config; // 0xbf802a38 0x0e 399 #define TSP_PVR2_LPCR1_WLD 0x00000001 400 #define TSP_PVR2_LPCR1_RLD 0x00000002 401 #define TSP_PVR2_STR2MIU_DSWAP 0x00000004 402 #define TSP_PVR2_STR2MIU_EN 0x00000008 403 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010 404 #define TSP_PVR2_STR2MIU_BT_ORDER 0x00000020 405 #define TSP_PVR2_STR2MIU_PAUSE 0x00000040 406 #define TSP_PVR2_REG_PINGPONG_EN 0x00000080 407 #define TSP_PVR2_PVR_ALIGN_EN 0x00000100 408 #define TSP_PVR2_DMA_FLUSH_EN 0x00000200 409 #define TSP_PVR2_PKT192_EN 0x00000400 410 #define TSP_PVR2_BURST_LEN_MASK 0x00001800 411 #define TSP_PVR2_BURST_LEN_SHIFT 11 412 #define TSP_REC_DATA2_INV 0x00002000 413 #define TSP_V_BLOCK_DIS 0x00004000 414 #define TSP_V3d_BLOCK_DIS 0x00008000 415 #define TSP_A_BLOCK_DIS 0x00010000 416 #define TSP_AD_BLOCK_DIS 0x00020000 417 #define TSP_PVR1_BLOCK_DIS 0x00040000 418 #define TSP_PVR2_BLOCK_DIS 0x00080000 419 #define TSP_TS_IF2_EN 0x00100000 420 #define TSP_TS_DATA2_SWAP 0x00200000 421 #define TSP_P_SEL2 0x00400000 422 #define TSP_EXT_SYNC_SEL2 0x00800000 423 #define TSP_BYPASS_TSIF2 0x01000000 424 #define TSP_TEI_SKIP_PKT2 0x02000000 425 #define TSP_AC_BLOCK_DIS 0x04000000 426 #define TSP_ADD_BLOCK_DIS 0x08000000 427 #define TSP_CLR_LOCKED_PKT_CNT 0x20000000 428 #define TSP_CLR_PKT_CNT 0x40000000 429 #define TSP_CLR_PVR_OVERFLOW 0x80000000 430 431 REG32 PVR2_LPCR1; // 0xbf802a40 0x10 432 433 #define TSP_STR2MI2_ADDR_MASK 0x0FFFFFFF 434 REG32 Str2mi_head1_pvr2; // 0xbf802a48 0x12 435 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14 436 REG32 Str2mi_tail1_pvr2; // 0xbf802a58 0x16 437 REG32 Str2mi_head2_pvr2; // 0xbf802a60 0x18 438 REG32 Str2mi_mid2_pvr2; // 0xbf802a68 0x1a, PVR2 mid address & write point 439 REG32 Str2mi_tail2_pvr2; // 0xbf802a70 0x1c 440 REG32 Hw_SyncByte2; // 0xbf802a78 0x1e 441 #define TSP_HW_CFG2_PACKET_SYNCBYTE2_MASK 0x000000FF 442 #define TSP_HW_CFG2_PACKET_SYNCBYTE2_SHFT 0 443 #define TSP_HW_CFG2_PACKET_SIZE2_MASK 0x0000FF00 444 #define TSP_HW_CFG2_PACKET_SIZE2_SHFT 8 445 #define TSP_HW_CFG2_PACKET_CHK_SIZE2_MASK 0x00FF0000 446 #define TSP_HW_CFG2_PACKET_CHK_SIZE2_SHFT 16 447 448 REG32 Pkt_CacheW0; // 0xbf802a80 0x20 449 450 REG32 Pkt_CacheW1; // 0xbf802a88 0x22 451 452 REG32 Pkt_CacheW2; // 0xbf802a90 0x24 453 454 REG32 Pkt_CacheW3; // 0xbf802a98 0x26 455 456 REG32 Pkt_CacheIdx; // 0xbf802aa0 0x28 457 458 REG32 Pkt_DMA; // 0xbf802aa8 0x2a 459 #define TSP_SEC_DMAFIL_NUM_MASK 0x000000FF 460 #define TSP_SEC_DMAFIL_NUM_SHIFT 0 461 #define TSP_SEC_DMASRC_OFFSET_MASK 0x0000FF00 462 #define TSP_SEC_DMASRC_OFFSET_SHIFT 8 463 #define TSP_SEC_DMADES_LEN_MASK 0x00FF0000 464 #define TSP_SEC_DMADES_LEN_SHIFT 16 465 466 REG16 Hw_Config0; // 0xbf802ab0 0x2c 467 #define TSP_HW_CFG0_DATA_PORT_SEL 0x0001 //TSIF0 data port output select. 0: select live TS to be TSIF output 1: select data port to be TSIF output 468 #define TSP_HW_CFG0_TSIFO_SERL 0x0000 469 #define TSP_HW_CFG0_TSIF0_PARL 0x0002 470 #define TSP_HW_CFG0_TSIF0_EXTSYNC 0x0004 471 #define TSP_HW_CFG0_TSIF0_TS_BYPASS 0x0008 472 #define TSP_HW_CFG0_TSIF0_VPID_BYPASS 0x0010 473 #define TSP_HW_CFG0_TSIF0_APID_BYPASS 0x0020 474 #define TSP_HW_CFG0_WB_DMA_RESET 0x0040 475 #define TSP_HW_CFG0_PACKET_BUF_SIZE_MASK 0xFF00 476 #define TSP_HW_CFG0_PACKET_BUF_SIZE_SHIFT 8 477 478 REG16 Hw_PktSize0; // 0xbf802ab4 0x2d 479 #define TSP_HW_CFG0_PACKET_PIDFLT0_SIZE_MASK 0x00FF 480 #define TSP_HW_CFG0_PACKET_PIDFLT0_SIZE_SHIFT 0 481 #define TSP_HW_CFG0_PACKET_CHK_SIZE_MASK 0xFF00 482 #define TSP_HW_CFG0_PACKET_CHK_SIZE_SHFT 8 483 484 REG16 _xbf202ab8; // 0xbf802ab8 0x2e 485 486 REG16 TSP_DBG_PORT; // 0xbf802ab8 0x2f 487 #define TSP_DNG_DATA_PORT_MASK 0x00FF 488 #define TSP_DNG_DATA_PORT_SHIFT 0 489 490 REG32 Pcr_L_CmdQ; // 0xbf802ac0 0x30 491 REG16 Pcr_H_CmdQ; // 0xbf802ac8 0x32 492 #define TSP_REG_PCR_CMDQ_H 0x0001 493 494 REG16 Vd_Pid_Hit; // 0xbf802acc 0x33 495 #define TSP_VPID_MASK 0x1FFF 496 497 REG16 Aud_Pid_Hit; // 0xbf802ad0 0x34 498 #define TSP_APID_MASK 0x1FFF 499 500 REG16 Pkt_Info; // 0xbf802ad4 0x35 501 #define TSP_PKT_PID_8_12_CP_MASK 0x001F 502 #define TSP_PKT_PID_8_12_CP_SHIFT 0 503 #define TSP_PKT_PRI_MASK 0x0020 504 #define TSP_PKT_PRI_SHIFT 5 505 #define TSP_PKT_PLST_MASK 0x0040 506 #define TSP_PKT_PLST_SHIFT 6 507 #define TSP_PKT_ERR 0x0080 508 #define TSP_PKT_ERR_SHIFT 7 509 510 REG16 Pkt_Info2; // 0xbf802ad8 0x36 511 #define TSP_PKT_INFO_CC_MASK 0x000F 512 #define TSP_PKT_INFO_CC_SHFT 0 513 #define TSP_PKT_INFO_ADPCNTL_MASK 0x0030 514 #define TSP_PKT_INFO_ADPCNTL_SHFT 4 515 #define TSP_PKT_INFO_SCMB 0x00C0 516 #define TSP_PKT_INFO_SCMB_SHFT 6 517 #define TSP_PKT_PID_0_7_CP_MASK 0xFF00 518 #define TSP_PKT_PID_0_7_CP_SHIFT 8 519 520 REG16 AVFifoSts; // 0xbf802adc 0x37 521 #define TSP_VFIFO3D_EMPTY 0x0001 522 #define TSP_VFIFO3D_EMPTY_SHFT 0 523 #define TSP_VFIFO3D_FULL 0x0002 524 #define TSP_VFIFO3D_FULL_SHFT 1 525 #define TSP_VFIFO3D_LEVEL 0x000C 526 #define TSP_VFIFO3D_LEVEL_SHFT 2 527 #define TSP_VFIFO_EMPTY 0x0010 528 #define TSP_VFIFO_EMPTY_SHFT 4 529 #define TSP_VFIFO_FULL 0x0020 530 #define TSP_VFIFO_FULL_SHFT 5 531 #define TSP_VFIFO_LEVEL 0x00C0 532 #define TSP_VFIFO_LEVEL_SHFT 6 533 #define TSP_AFIFO_EMPTY 0x0100 534 #define TSP_AFIFO_EMPTY_SHFT 8 535 #define TSP_AFIFO_FULL 0x0200 536 #define TSP_AFIFO_FULL_SHFT 9 537 #define TSP_AFIFO_LEVEL 0x0C00 538 #define TSP_AFIFO_LEVEL_SHFT 10 539 #define TSP_AFIFOB_EMPTY 0x1000 540 #define TSP_AFIFOB_EMPTY_SHFT 12 541 #define TSP_AFIFOB_FULL 0x2000 542 #define TSP_AFIFOB_FULL_SHFT 13 543 #define TSP_AFIFOB_LEVEL 0xC000 544 #define TSP_AFIFOB_LEVEL_SHFT 14 545 546 REG32 SwInt_Stat; // 0xbf802ae0 0x38 547 #define TSP_SWINT_INFO_SEC_MASK 0x000000FF 548 #define TSP_SWINT_INFO_SEC_SHFT 0 549 #define TSP_SWINT_INFO_ENG_MASK 0x0000FF00 550 #define TSP_SWINT_INFO_ENG_SHFT 8 551 #define TSP_SWINT_STATUS_CMD_MASK 0x7FFF0000 552 #define TSP_SWINT_STATUS_CMD_SHFT 16 553 #define TSP_SWINT_STATUS_SEC_RDY 0x0001 554 #define TSP_SWINT_STATUS_REQ_RDY 0x0002 555 #define TSP_SWINT_STATUS_SEC_RDY_CRCERR 0x0003 556 #define TSP_SWINT_STATUS_BUF_OVFLOW 0x0006 557 #define TSP_SWINT_STATUS_SEC_CRCERR 0x0007 558 #define TSP_SWINT_STATUS_SEC_ERROR 0x0008 559 #define TSP_SWINT_STATUS_SYNC_LOST 0x0010 560 #define TSP_SWINT_STATUS_PKT_OVRUN 0x0020 561 #define TSP_SWINT_STATUS_DEBUG 0x0030 562 #define TSP_SWINT_CMD_DMA_PAUSE 0x0100 563 #define TSP_SWINT_CMD_DMA_RESUME 0x0200 564 #define TSP_SWINT_STATUS_SEC_GROUP 0x000F 565 #define TSP_SWINT_STATUS_GROUP 0x00FF 566 #define TSP_SWINT_CMD_GROUP 0x7F00 567 #define TSP_SWINT_CMD_STC_UPD 0x0400 568 #define TSP_SWINT_CTRL_FIRE 0x80000000 569 570 REG32 TsDma_Addr; // 0xbf802ae8 0x3a 571 572 REG32 TsDma_Size; // 0xbf802af0 0x3c 573 574 REG16 TsDma_Ctrl; // 0xbf802af8 0x3e 575 #define TSP_TSDMA_CTRL_START 0x0001 576 #define TSP_TSDMA_FILEIN_DONE 0x0002 577 #define TSP_TSDMA_INIT_TRUST 0x0004 578 #define TSP_TSDMA_STAT_ABORT 0x0080 579 580 REG16 TsDma_mdQ; // 0xbf802af8 0x3f 581 #define TSP_CMDQ_CNT_MASK 0x001F 582 #define TSP_CMDQ_CNT_SHFT 0 583 #define TSP_CMDQ_FULL 0x0040 584 #define TSP_CMDQ_EMPTY 0x0080 585 #define TSP_CMDQ_SIZE 16 586 #define TSP_CMDQ_WR_LEVEL_MASK 0x0300 587 #define TSP_CMDQ_WR_LEVEL_SHFT 8 588 589 REG32 MCU_Cmd; // 0xbf802b00 0x40 590 #define TSP_MCU_CMD_MASK 0x0000FFFF 591 #define TSP_MCU_CMD_NULL 0x00000000 592 #define TSP_MCU_CMD_READ 0x00000001 593 #define TSP_MCU_CMD_WRITE 0x00000002 594 #define TSP_MCU_CMD_ALIVE 0x00000100 595 #define TSP_MCU_CMD_DBG 0x00000200 596 #define TSP_MCU_CMD_BUFRST 0x00000400 597 #define TSP_MCU_CMD_SECRDYINT_DISABLE 0x00000800 598 #define TSP_MCU_CMD_SEC_CC_CHECK_DISABLE 0x00001000 599 #define TSP_MCU_CMD_INFO 0x00008000 600 #define INFO_FW_VERSION 0x0001 601 #define INFO_FW_DATE 0x0002 602 603 REG16 PktSize1; // 0xbf802b08 0x42 604 #define TSP_HW_CFG2_PACKET_CHK_SIZE1_MASK 0x00FF 605 #define TSP_HW_CFG2_PACKET_CHK_SIZE1_SHFT 0 606 #define TSP_HW_CFG2_PACKET_SYNCBYTE1_MASK 0xFF00 607 #define TSP_HW_CFG2_PACKET_SYNCBYTE1_SHFT 8 608 609 REG16 Hw_Config2; // 0xbf802b0C 0x43 610 #define TSP_HW_CFG2_PACKET_SIZE1_MASK 0x00FF 611 #define TSP_HW_CFG2_PACKET_SIZE1_SHFT 0 612 #define TSP_HW_CFG2_TSIF1_SERL 0x0000 613 #define TSP_HW_CFG2_TSIF1_PARL 0x0100 614 #define TSP_HW_CFG2_TSIF1_EXTSYNC 0x0200 615 #define TSP_HW_CFG2_TSIF1_TS_BYPASS 0x1000 616 617 REG16 Hw_PVRCfg; // 0xbf802b10 0x44 618 #define TSP_HW_CFG4_SECDMA_PRI_HIGH 0x0001 619 #define TSP_HW_CFG4_PVR_ENABLE 0x0002 620 #define TSP_HW_CFG4_PVR_ENDIAN_BIG 0x0004 // 1: record TS to MIU with big endian, 0: record TS to MIU with little endian 621 #define TSP_HW_CFG4_TSIF1_ENABLE 0x0008 // 1: enable ts interface 1 and vice versa 622 #define TSP_HW_CFG4_PVR_FLUSH 0x0010 // 1: str2mi_wadr <- str2mi_miu_head 623 #define TSP_HW_CFG4_PVRBUF_BYTEORDER_BIG 0x0020 // Byte order of 8-byte recoding buffer to MIU. 624 #define TSP_HW_CFG4_PVR_PAUSE 0x0040 625 #define TSP_HW_CFG4_MEMTSDATA_ENDIAN_BIG 0x0080 // 32-bit data byte order read from 8x64 FIFO when playing file. 626 #define TSP_HW_CFG4_TSIF0_ENABLE 0x0100 // 1: enable ts interface 0 and vice versa 627 #define TSP_SYNC_RISING_DETECT 0x0200 // Reset bit count when data valid signal of TS interface is low. 628 #define TSP_VALID_FALLING_DETECT 0x0400 // Reset bit count on the rising sync signal of TS interface. 629 #define TSP_HW_CFG4_TS_DATA0_SWAP 0x0800 // Set 1 to swap the bit order of TS0 DATA bus 630 #define TSP_HW_CFG4_TS_DATA1_SWAP 0x1000 // Set 1 to swap the bit order of TS1 DATA bus 631 #define TSP_HW_TSP2OUTAEON_INT_EN 0x4000 // Set 1 to force interrupt to outside AEON 632 #define TSP_HW_HK_INT_FORCE 0x8000 // Set 1 to force interrupt to HK_MCU 633 634 REG16 Hw_Config4; // 0xbf802b14 0x45 635 #define TSP_HW_CFG4_ALT_TS_SIZE 0x0001 // enable TS packets in 204 mode 636 #define TSP_HW_CFG4_PS_AUDC_EN 0x0002 // program stream audiodC enable 637 #define TSP_HW_CFG4_BYTE_ADDR_DMA 0x000D // prevent from byte enable bug, bit1~3 must enable togather 638 #define TSP_HW_DMA_MODE_MASK 0x0030 // Section filter DMA mode, 2'b00: Single.2'b01: Burst 2 bytes.2'b10: Burst 4 bytes.2'b11: Burst 8 bytes. 639 #define TSP_HW_DMA_MODE_SHIFT 4 640 #define TSP_HW_CFG4_WSTAT_CH_EN 0x0040 641 #define TSP_HW_CFG4_PS_VID_EN 0x0080 // program stream video enable 642 #define TSP_HW_CFG4_PS_AUD_EN 0x0100 // program stream audio enable 643 #define TSP_HW_CFG4_PS_AUDB_EN 0x0200 // program stream audioB enable 644 #define TSP_HW_CFG4_APES_ERR_RM_EN 0x0400 // Set 1 to enable removing APES error packet 645 #define TSP_HW_CFG4_VPES_ERR_RM_EN 0x0800 // Set 1 to enable removing VPES error packet 646 #define TSP_HW_CFG4_SEC_ERR_RM_EN 0x1000 // Set 1 to enable removing section error packet 647 #define TSP_HW_CFG4_PS_AUDD_EN 0x2000 // program stream audioD enable 648 #define TSP_HW_CFG4_DATA_CHK_2T 0x8000 // Set 1 to enable the patch of internal sync in "tsif" 649 650 REG32 NOEA_PC; // 0xbf802b18 0x46 651 652 REG16 Idr_Ctrl; // 0xbf802b20 0x48 653 #define TSP_IDR_START 0x0001 654 #define TSP_IDR_READ 0x0000 655 #define TSP_IDR_WRITE 0x0002 656 #define TSP_IDR_WR_ENDIAN_BIG 0x0004 657 #define TSP_IDR_WR_ADDR_AUTO_INC 0x0008 // Set 1 to enable address auto-increment after finishing read/write 658 #define TSP_IDR_WDAT0_TRIG_EN 0x0010 // WDAT0_TRIG_EN 659 #define TSP_IDR_MCUWAIT 0x0020 660 #define TSP_IDR_SOFT_RST 0x0080 // Set 1 to soft-reset the IND32 module 661 #define TSP_IDR_AUTO_INC_VAL_MASK 0x0F00 662 #define TSP_IDR_AUTO_INC_VAL_SHIFT 8 663 664 REG32 Idr_Addr; // 0xbf802b24 0x49 665 REG32 Idr_Write; // 0xbf802b2c 0x4b 666 REG32 Idr_Read; // 0xbf802b34 0x4d 667 668 REG16 Fifo_Status; // 0xbf802b3c 0x4f 669 #define TSP_V3D_FIFO_DISCON 0x0010 670 #define TSP_V3D_FIFO_OVERFLOW 0x0020 671 #define TSP_VD_FIFO_DISCON 0x0200 672 #define TSP_VD_FIFO_OVERFLOW 0x0800 673 #define TSP_AUB_FIFO_OVERFLOW 0x1000 674 #define TSP_AU_FIFO_OVERFLOW 0x2000 675 676 // only 25 bits supported in PVR address. 8 bytes address 677 #define TSP_STR2MI2_ADDR_MASK 0x0FFFFFFF 678 REG32 TsRec_Head; // 0xbf802b40 0x50 679 REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid address & write point 680 REG32 TsRec_Tail; // 0xbf802b50 0x54 681 REG32 _xbf802b58[2]; // 0xbf802b58 ~ 0xbf802b60 0x56~0x59 682 683 REG16 reg15b4; // 0xbf802b68 0x5a 684 #define TSP_VQ_DMAW_PROTECT_EN 0x0001 685 #define TSP_SEC_CB_PVR2_DAMW_PROTECT_EN 0x0002 686 #define TSP_PVR_PID_BYPASS 0x0008 // Set 1 to bypass PID in record 687 #define TSP_PVR_PID_BYPASS2 0x0010 // Set 1 to bypass PID in record2 688 #define TSP_BD_AUD_EN 0x0020 // Set 1 to enable the BD audio stream recognization ( core /extend audio stream) 689 #define TSP_BD2_AUD_EN 0x0200 // Set 1 to enable the BD audio stream recognization ( core /extend audio stream) 690 #define TSP_AVFIFO_RD_EN 0x0080 // 0: AFIFO and VFIFO read are connected to MVD and MAD, 1: AFIFO and VFIFO read are controlled by registers (0x15B5[2:0]) 691 #define TSP_AVFIFO_RD 0x0100 // If AVFIFO_RD_EN is 1, set to 1, then set to 0 would issue a read strobe to AFIFO or VFIFO 692 #define TSP_NMATCH_DISABLE 0x0800 693 #define TSP_PVR_INVERT 0x1000 // Set 1 to enable data payload invert for PVR record 694 #define TSP_PLY_FILE_INV_EN 0x2000 // Set 1 to enable data payload invert in pidflt0 file path 695 #define TSP_PLY_TS_INV_EN 0x4000 // Set 1 to enable data payload invert in pidflt0 TS path 696 #define TSP_FILEIN_BYTETIMER_ENABLE 0x8000 // Set 1 to enable byte timer in ts_if0 TS path 697 698 REG16 reg15b8; // 0xbf802b6C 0x5b 699 #define TSP_PVR1_PINGPONG 0x0001 // Set 1 to enable MIU addresses with pinpon mode 700 #define TSP_VQ_STATUS_SEL 0x0002 701 #define TSP_TEI_SKIPE_PKT_PID0 0x0004 // Set 1 to skip error packets in pidflt0 TS path 702 #define TSP_TEI_SKIPE_PKT_PID4 0x0008 // Set 1 to skip error packets in pidflt4 TS path 703 #define TSP_TEI_SKIPE_PKT_PID1 0x0010 // Set 1 to skip error packets in pidflt1 TS path 704 #define TSP_TEI_SKIPE_PKT_PID3 0x0020 // Set 1 to skip error packets in pidflt3 TS path 705 #define TSP_REMOVE_DUP_AV_PKT 0x0040 // Set 1 to remove duplicate A/V packet 706 #define TSP_64bit_PCR2_ld 0x0080 707 #define TSP_cnt_33b_ld 0x0100 708 #define TSP_FORCE_SYNCBYTE 0x0200 // Set 1 to force sync byte (8'h47) in ts_if0 and ts_if1 path. 709 #define TSP_SERIAL_EXT_SYNC_1T 0x0400 // Set 1 to detect serial-in sync without 8-cycle mode 710 #define TSP_BURST_LEN_MASK 0x1800 // 00,01: burst length = 4; 10,11: burst length = 1 711 #define TSP_BURST_LEN_SHIFT 11 712 #define TSP_MATCH_PID_SRC_MASK 0xE000 // Select the source of pid filter number with hit pid and match pid number with scramble information, 00 : from pkt_demux0, 01 : from pkt_demux_file, 10 : from pkt_demux1, 11 : from pkt_demux2 713 #define TSP_MATCH_PID_SRC_SHIFT 13 714 #define TSP_MATCH_PID_SRC_PKTDMX0 0 715 #define TSP_MATCH_PID_SRC_PKTDMX1 1 716 #define TSP_MATCH_PID_SRC_PKTDMX2 2 717 #define TSP_MATCH_PID_SRC_PKTDMX3 3 718 719 REG32 TSP_MATCH_PID_NUM; // 0xbf802b70 0x5c 720 721 REG32 TSP_IWB_WAIT; // 0xbf802b78 0x5e // Wait count settings for IWB when TSP CPU i-cache is enabled. 722 723 REG32 Cpu_Base; // 0xbf802b80 0x60 724 #define TSP_CPU_BASE_ADDR_MASK 0x0FFFFFFF 725 726 REG32 Qmem_Ibase; // 0xbf802b88 0x62 727 728 REG32 Qmem_Imask; // 0xbf802b90 0x64 729 730 REG32 Qmem_Dbase; // 0xbf802b98 0x66 731 732 REG32 Qmem_Dmask; // 0xbf802ba0 0x68 733 734 REG32 TSP_Debug; // 0xbf802ba8 0x6a 735 #define TSP_DEBUG_MASK 0x00FFFFFF 736 737 REG32 _xbf802bb0; // 0xbf802bb0 0x6c 738 739 REG32 TsFileIn_RPtr; // 0xbf802bb8 0x6e 740 #define TSP_FILE_RPTR_MASK 0x0FFFFFFF 741 REG32 TsFileIn_Timer; // 0xbf802bc0 0x70 742 #define TSP_FILE_TIMER_MASK 0x00FFFFFF 743 REG32 TsFileIn_Head; // 0xbf802bc8 0x72 744 #define TSP_FILE_ADDR_MASK 0x0FFFFFFF 745 REG32 TsFileIn_Mid; // 0xbf802bd0 0x74 746 747 REG32 TsFileIn_Tail; // 0xbf802bd8 0x76 748 749 REG16 Dnld_Ctrl_Addr; // 0xbf802be0 0x78 750 #define TSP_DNLD_ADDR_MASK 0xFFFF 751 #define TSP_DNLD_ADDR_SHFT 0 752 #define TSP_DNLD_ADDR_ALI_SHIFT 4 // Bit [11:4] of DMA_RADDR[19:0] 753 754 REG16 Dnld_Ctrl_Size; // 0xbf802be4 0x79 755 #define TSP_DNLD_NUM_MASK 0xFFFF 756 #define TSP_DNLD_NUM_SHFT 0 757 758 REG16 TSP_Ctrl; // 0xbf802be8 0x7a 759 #define TSP_CTRL_CPU_EN 0x0001 760 #define TSP_CTRL_SW_RST 0x0002 761 #define TSP_CTRL_DNLD_START 0x0004 762 #define TSP_CTRL_DNLD_DONE 0x0008 // See 0x78 for related information 763 #define TSP_CTRL_TSFILE_EN 0x0010 764 #define TSP_CTRL_R_PRIO 0x0020 765 #define TSP_CTRL_W_PRIO 0x0040 766 #define TSP_CTRL_ICACHE_EN 0x0100 767 #define TSP_CTRL_CPU2MI_R_PRIO 0x0400 768 #define TSP_CTRL_CPU2MI_W_PRIO 0x0800 769 #define TSP_CTRL_I_EL 0x0000 770 #define TSP_CTRL_I_BL 0x1000 771 #define TSP_CTRL_D_EL 0x0000 772 #define TSP_CTRL_D_BL 0x2000 773 #define TSP_CTRL_NOEA_QMEM_ACK_DIS 0x4000 774 #define TSP_CTRL_MEM_TS_WORDER 0x8000 775 776 REG16 TSP_SyncByte; // 0xbf802bec 0x7b 777 #define TSP_SYNC_BYTE_MASK 0x00FF 778 #define TSP_SYNC_BYTE_SHIFT 0 779 780 REG16 PKT_CNT; // 0xbf802bf0 0x7c 781 #define TSP_PKT_CNT_MASK 0x00FF 782 783 REG16 DBG_SEL; // 0xbf802bf4 0x7d 784 #define TSP_DBG_SEL_MASK 0xFFFF 785 #define TSP_DBG_SEL_SHIFT 0 786 787 REG16 HwInt_Stat; // 0xbf802bf8 0x7e 788 /* 789 7: audio/video packet error 790 6: DMA read done 791 5: HK_INT_FORCE. // it's trigure bit is at bank 15 44 bit[15] 792 4: TSP_FILE_RP meets TSP_FILE_TAIL. 793 3: TSP_FILE_RP meets TSP_FILE_MID. 794 2: HK_INT_FORCE. // it's trigure bit is at bank 15 39 bit[15] 795 1: STR2MI_WADR meets STR2MI_MID. 796 0: STR2MI_WADR meets STR2MI_TAIL." 797 */ 798 #define TSP_INT_EN_MASK 0x00FF // Tsp2hk_int enable bits. 799 #define TSP_INT_EN_SHIFT 0 800 #define TSP_HWINT_TSP_PVR_TAIL0_EN 0x0001 // currently not used in ISR 801 #define TSP_HWINT_TSP_PVR_MID0_EN 0x0002 // currently not used in ISR 802 #define TSP_HWINT_HW_PVR0_EN_MASK (TSP_HWINT_TSP_PVR_TAIL0_EN | TSP_HWINT_TSP_PVR_MID0_EN) 803 #define TSP_HWINT_TSP_HK_INT_FORCE_EN 0x0004 // currently not used in ISR 804 #define TSP_HWINT_TSP_FILEIN_MID_INT_EN 0x0008 // currently not used in ISR 805 #define TSP_HWINT_TSP_FILEIN_TAIL_INT_EN 0x0010 // currently not used in ISR 806 #define TSP_HWINT_TSP_SW_INT_EN 0x0020 807 #define TSP_HWINT_TSP_DMA_READ_DONE_EN 0x0040 // currently not used in ISR 808 #define TSP_HWINT_TSP_AV_PKT_ERR_EN 0x0080 // currently not used in ISR 809 #define TSP_HWINT_TSP_SUPPORT_ALL (TSP_HWINT_TSP_SW_INT_EN) 810 #define TSP_HWINT_ALL TSP_HWINT_TSP_SUPPORT_ALL 811 812 #define TSP_HWINT_STATUS_MASK 0xFF00 813 #define TSP_HWINT_STATUS_SHIFT 8 814 #define TSP_HWINT_TSP_PVR_TAIL0_STATUS 0x0100 815 #define TSP_HWINT_TSP_PVR_MID0_STATUS 0x0200 816 #define TSP_HWINT_HW_PVR0_STATUS_MASK (TSP_HWINT_TSP_PVR_TAIL0_STATUS | TSP_HWINT_TSP_PVR_MID0_STATUS) 817 #define TSP_HWINT_TSP_HK_INT_FORCE_STATUS 0x0400 818 #define TSP_HWINT_TSP_FILEIN_MID_INT_STATUS 0x0800 819 #define TSP_HWINT_TSP_FILEIN_TAIL_INT_STATUS 0x1000 820 #define TSP_HWINT_TSP_SW_INT_STATUS 0x2000 821 #define TSP_HWINT_TSP_DMA_READ_DONE 0x4000 822 #define TSP_HWINT_TSP_AV_PKT_ERR 0x8000 823 824 // following mask is merged with bank 15 7e(LOW BYTE) and bank 16 6c(HIGH BYTE) 825 #define TSP_HWINT_HW_PVR_ALL_MASK (TSP_HWINT_HW_PVR0_STATUS_MASK | TSP_HWINT_HW_PVR1_MASK) //@FIXME this is for all pvr interrupt but PVR 3 and 4 is not added 826 827 REG16 TSP_Ctrl1; // 0xbf802bfc 0x7f 828 // 0x7f: TSP_CTRL1: hidden in HwInt_Stat 829 #define TSP_CTRL1_FILEIN_TIMER_ENABLE 0x0001 830 #define TSP_CTRL1_TSP_FILE_NON_STOP 0x0002 //Set 1 to enable TSP file data read without timer check 831 #define TSP_CTRL1_FILEIN_PAUSE 0x0004 //Set 1 to pause file-in engine fetch data 832 #define TSP_CTRL1_FILE_CHECK_WP 0x0008 833 #define TSP_CTRL1_FILE_WP_SEL_MASK 0x0030 834 #define TSP_CTRL1_FILE_WP_FI 0x0010 835 #define TSP_CTRL1_FILE_WP_PVR 0x0020 836 #define TSP_CTRL1_STANDBY 0x0080 837 #define TSP_CTRL1_INT2NOEA 0x0100 838 #define TSP_CTRL1_INT2NOEA_FORCE 0x0200 839 #define TSP_CTRL1_FORCE_XIU_WRDY 0x0400 840 #define TSP_CTRL1_CMDQ_RESET 0x0800 841 #define TSP_CTRL1_DLEND_EN 0x1000 // Set 1 to enable little-endian mode in TSP CPU 842 #define TSP_CTRL1_PVR_CMD_QUEUE_ENABLE 0x2000 843 #define TSP_CTRL1_FILEIN_RADDR_READ 0x4000 844 #define TSP_CTRL1_DMA_RST 0x8000 845 846 //---------------------------------------------- 847 // 0xBF802C00 MIPS direct access 848 //---------------------------------------------- 849 REG32 MCU_Data0; // 0xbf802c00 0x00 850 #define TSP_MCU_DATA_ALIVE TSP_MCU_CMD_ALIVE 851 852 REG32 PVR1_LPcr1; // 0xbf802c08 0x02 853 854 REG32 LPcr2; // 0xbf802c10 0x04 855 856 REG16 reg160C; // 0xbf802c18 0x06 857 #define TSP_PVR1_LPCR1_WLD 0x0001 // Set 1 to load LPCR1 value (Default: 0) 858 #define TSP_PVR1_LPCR1_RLD 0x0002 // Set 1 to read LPCR1 value (Default: 1) 859 #define TSP_LPCR2_WLD 0x0004 // Set 1 to load LPCR2 value (Default: 0) 860 #define TSP_LPCR2_RLD 0x0008 // Set 1 to read LPCR2 value (Default: 1) 861 #define TSP_RECORD192_EN 0x0010 // 160C bit(5)enable TS packets with 192 bytes on record mode 862 #define TSP_FILEIN192_EN 0x0020 // 160C bit(5)enable TS packets with 192 bytes on file-in mode 863 #define TSP_ORZ_DMAW_PROT_EN 0x0080 // 160C bit(7) open RISC DMA write protection 864 #define TSP_CLR_PIDFLT_BYTE_CNT 0x0100 // Clear pidflt0_file byte counter 865 #define TSP_DOUBLE_BUF_DESC 0x4000 // 160d bit(6) remove buffer limitation, Force pinpong buffer to flush 866 #define TSP_TIMESTAMP_RESET 0x8000 // 160d bit(7) reset timestamp 867 868 REG16 reg160E; // 0xbf802c1C 0x07 869 #define TSP_VQTX0_BLOCK_DIS 0x0001 870 #define TSP_VQTX1_BLOCK_DIS 0x0002 871 #define TSP_VQTX2_BLOCK_DIS 0x0004 872 #define TSP_VQTX3_BLOCK_DIS 0x0008 873 #define TSP_DIS_MIU_RQ 0x0010 // Disable miu R/W request for reset TSP usage 874 #define TSP_RM_DMA_GLITCH 0x0080 // Fix sec_dma overflow glitch 875 #define TSP_RESET_VFIFO 0x0100 // Reset VFIFO -- ECO Done 876 #define TSP_RESET_AFIFO 0x0200 // Reset AFIFO -- ECO Done 877 #define TSP_RESET_AFIFO3 0x0400 // Reset AFIFOC -- ECO Done 878 #define TSP_CLR_ALL_FLT_MATCH 0x0800 // Set 1 to clean all flt_match in a packet 879 #define TSP_RESET_AFIFO2 0x1000 880 #define TSP_RESET_VFIFO3D 0x2000 881 #define TSP_PVR_WPRI_HIGH 0x4000 882 #define TSP_OPT_ORACESS_TIMING 0x8000 883 884 REG16 PktChkSizeFilein; // 0xbf802c20 0x08 885 #define TSP_PKT_SIZE_MASK 0x00ff 886 #define TSP_PKT192_BLK_DIS_FIN 0x0100 // Set 1 to disable file-in timestamp block scheme 887 #define TSP_AV_CLR 0x0200 // Clear AV FIFO overflow flag and in/out counter 888 #define TSP_HW_STANDBY_MODE 0x0400 // Set 1 to disable all SRAM in TSP for low power mode automatically 889 #define TSP_RESET_AFIFO4 0x4000 // Reset AFIFOC -- ECO Done 890 891 REG16 TSP_Cfg5; // 0xbf802c24 0x09 892 #define TSP_PREVENT_OVF_META 0x0001 893 #define TSP_OVF_META_SEL 0x0004 894 #define TSP_SYSTIME_MODE 0x0008 895 #define TSP_SEC_DMA_BURST_EN 0x0080 // Enable Section DMA burst 896 897 REG16 Dnld_AddrH; // 0xbf802c28 0x0a 898 #define TSP_DMA_RADDR_MSB_MASK 0x00FF 899 #define TSP_DMA_RADDR_MSB_SHIFT 0 900 901 REG16 TSP_Ctrl2; // 0xbf802c2c 0x0b 902 #define TSP_CMQ_WORD_EN 0x0040 // Set 1 to access CMDQ related registers in word. 903 #define TSP_AV_DIRECT_STOP 0x0080 //Set 1 to enable A/V fifo full pull back tsif0 file in 904 #define TSP_AV_DIRECT_STOP1 0x0100 //Set 1 to enable A/V fifo full pull back tsif1 file in 905 #define TSP_AV_DIRECT_STOP2 0x0200 //Set 1 to enable A/V fifo full pull back tsif2 file in 906 #define TSP_AV_DIRECT_STOP3 0x0400 //Set 1 to enable A/V fifo full pull back tsif3 file in 907 #define TSP_TS_OUT_EN 0x1000 // TS_CB out enable. for Serial input to parallel output 908 #define TSP_PS_VID_3D_EN 0x2000 //Set 1 to enable video 3D path in program stream mode 909 910 REG32 TsPidScmbStatTsin; // 0xbf802c30 0x0c 911 912 REG32 TsPidScmbStatFile; // 0xbf802c38 0x0e 913 914 REG32 PCR64_2_L; // 0xbf802c40 0x10 915 916 REG32 PCR64_2_H; // 0xbf802c48 0x12 917 918 #define TSP_DMAW_BND_MASK 0xFFFFFFFFUL 919 REG32 DMAW_LBND0; // 0xbf802c50 0x14 //sec1 protect 920 921 REG32 DMAW_UBND0; // 0xbf802c58 0x16 922 923 REG32 DMAW_LBND1; // 0xbf802c60 0x18 //sec2 protect 924 925 REG32 DMAW_UBND1; // 0xbf802c68 0x1A 926 927 REG32 HW2_CFG6; // 0xbf802c68 0x1C 928 929 REG32 HW2_CFG5; // 0xbf802c68 0x1E 930 931 REG32 VQ0_BASE; // 0xbf802c80 0x20 932 933 REG16 VQ0_SIZE; // 0xbf802c84 0x22 934 #define TSP_VQ0_SIZE_208PK_MASK 0xFFFF 935 #define TSP_VQ0_SIZE_208PK_SHIFT 0 936 937 REG16 VQ0_CTRL; // 0xbf802c88 0x23 938 #define TSP_VQ0_WR_THRESHOLD_MASK 0x000F 939 #define TSP_VQ0_WR_THRESHOLD_SHIFT 0 940 #define TSP_VQ0_PRIORTY_THRESHOLD_MASK 0x00F0 941 #define TSP_VQ0_PRIORTY_THRESHOL_SHIFT 4 942 #define TSP_VQ0_FORCE_FIRE_CNT_1K_MASK 0x0F00 943 #define TSP_VQ0_FORCE_FIRE_CNT_1K_SHIFT 8 944 #define TSP_VQ0_RESET 0x1000 945 #define TSP_VQ0_OVERFLOW_INT_EN 0x4000 // Enable the interrupt for overflow happened on Virtual Queue path 946 #define TSP_VQ0_CLR_OVERFLOW_INT 0x8000 // Clear the interrupt and the overflow flag 947 948 REG16 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 949 950 #define TSP_REQ_VQ_RX_THRESHOLD_MASKE 0x000E 951 #define TSP_REQ_VQ_RX_THRESHOLD_SHIFT 1 952 #define TSP_REQ_VQ_RX_THRESHOLD_LEN1 0x0000 953 #define TSP_REQ_VQ_RX_THRESHOLD_LEN2 0x0002 954 #define TSP_REQ_VQ_RX_THRESHOLD_LEN4 0x0004 955 #define TSP_REQ_VQ_RX_THRESHOLD_LEN8 0x0006 956 #define TSP_PIDFLT0_OVF_INT_EN 0x0040 957 #define TSP_PIDFLT0_CLR_OVF_INT 0x0080 958 #define TSP_PIDFLT1_OVF_INT_EN 0x0100 959 #define TSP_PIDFLT1_CLR_OVF_INT 0x0200 960 #define TSP_PIDFLT2_OVF_INT_EN 0x0400 961 #define TSP_PIDFLT2_CLR_OVF_INT 0x0800 962 963 REG16 _xbf202c94 ; // 0xbf802c94 0x25 964 965 REG16 MOBF_PVR1_Index[2]; // 0xbf3a2c98 0x26 966 #define TSP_MOBF_PVR1_INDEX_MASK 0x0000001F 967 #define TSP_MOBF_PVR1_INDEX_SHIFT 0 968 969 REG16 MOBF_PVR2_Index[2]; // 0xbf3a2cA0 0x28 970 #define TSP_MOBF_PVR2_INDEX_MASK 0x0000001F 971 #define TSP_MOBF_PVR2_INDEX_SHIFT 0 972 973 REG32 DMAW_LBND2; // 0xbf802ca8 0x2a //PVR protect 974 #define TSP_PVR_MASK 0x0FFFFFFFUL 975 976 REG32 DMAW_UBND2; // 0xbf802cb0 0x2c 977 978 REG32 DMAW_LBND3; // 0xbf802cb8 0x2e //PVR 2 protect 979 980 REG32 DMAW_UBND3; // 0xbf802cc0 0x30 981 982 REG32 DMAW_LBND4; // 0xbf802cc8 0x32 //PVR 3 protect 983 984 REG32 DMAW_UBND4; // 0xbf802cd0 0x34 985 986 REG32 ORZ_DMAW_LBND; // 0xbf802cd8 0x36 //CPU protect 987 #define TSP_ORZ_DMAW_LBND_MASK 0xffffffffUL //protect address is base on MIU unit (16byte aligment) 988 REG32 ORZ_DMAW_UBND; // 0xbf802ce0 0x38 989 #define TSP_ORZ_DMAW_UBND_MASK 0xffffffffUL 990 991 REG16 PIDFLT_PCR0; // 0xbf802ce8 0x3a 992 #define TSP_PIDFLT_PCR0_PID_MASK 0x1fff 993 #define TSP_PIDFLT_PCR0_EN 0x8000 994 995 996 REG16 PIDFLT_PCR1; // 0xbf802ce8 0x3b 997 #define TSP_PIDFLT_PCR1_PID_MASK 0x1fff 998 #define TSP_PIDFLT_PCR1_EN 0x8000 999 1000 REG32 HWPCR0_L; // 0xbf802cf0 0x3c 1001 REG32 HWPCR0_H; // 0xbf802cf8 0x3e 1002 1003 REG32 CA_CTRL; // 0xbf802d00 0x40 1004 #define TSP_CA_CTRL_MASK 0xffffffff 1005 #define TSP_CA0_INPUT_TSIF0_LIVEIN 0x00000001 1006 #define TSP_CA0_INPUT_TSIF0_FILEIN 0x00000002 1007 #define TSP_CA0_INPUT_TSIF1 0x00000004 1008 #define TSP_CA0_AVPAUSE 0x00000008 1009 #define TSP_CA0_OUTPUT_PKTDMX0_LIVE 0x00000010 1010 #define TSP_CA0_OUTPUT_PKTDMX0_FILE 0x00000020 1011 #define TSP_CA0_OUTPUT_PKTDMX1 0x00000040 //pkt_demux1 1012 #define TSP_CA0_INPUT_TSIF2 0x00001000 1013 #define TSP_CA0_OUTPUT_PKTDMX2 0x00002000 //pkt_demux2 1014 #define TSP_CA2_INPUT_TSIF2 0x00100000 1015 #define TSP_CA2_OUTPUT_REC2 0x00200000 //pkt_demux2 1016 #define TSP_CA2_INPUT_TSIF0_LIVEIN 0x01000000 1017 #define TSP_CA2_INPUT_TSIF0_FILEIN 0x02000000 1018 #define TSP_CA2_INPUT_TSIF1 0x04000000 1019 #define TSP_CA2_OUTPUT_PLAY_LIVE 0x10000000 1020 #define TSP_CA2_OUTPUT_PLAY_FILE 0x20000000 1021 #define TSP_CA2_OUTPUT_REC1 0x40000000 //pkt_demux1 1022 1023 REG16 OneWay; // 0xbf802d08 0x42 , 1024 #define TSP_ONEWAY_CAREC_DISABLE 0x0001 1025 #define TSP_ONEWAY_PVR 0x0002 1026 #define TSP_ONEWAY_PVR1 0x0004 1027 #define TSP_ONEWAY_FW 0x0008 1028 #define TSP_ONEWAY_QMEM 0x0010 1029 #define TSP_ONEWAY_PVR2 0x0020 1030 #define TSP_ONEWAY_FIQ 0x0040 1031 1032 REG16 _xbf202d0C; // 0xbf802d0C 0x43 1033 1034 REG32 HWPCR1_L; // 0xbf802d10 0x44 1035 REG32 HWPCR1_H; // 0xbf802d18 0x46 1036 1037 REG16 IND32_CMD; // 0xbf802d20 0x48 1038 1039 REG32 IND32_ADDR; // 0xbf802d24 0x49, Indirect address to TSP CPU 1040 1041 REG32 IND32_WDATA; // 0xbf802d2C 0x4B, Indirect write data to TSP CPUr 1042 1043 REG32 IND32_RDATA; // 0xbf802d34 0x4D, IND32_WDATA 1044 1045 REG16 _xbf202d3c; // 0xbf802d3C 0x4F 1046 1047 REG16 FIFO_Src; // 0xbf802d40 0x50 1048 #define TSP_AUD_SRC_MASK 0x0007 1049 #define TSP_AUD_SRC_SHIFT 0 1050 #define TSP_AUDB_SRC_MASK 0x0038 1051 #define TSP_AUDB_SRC_SHIFT 3 1052 #define TSP_VID_SRC_MASK 0x01C0 1053 #define TSP_VID_SRC_SHIFT 6 1054 #define TSP_VID3D_SRC_MASK 0x0E00 1055 #define TSP_VID3D_SRC_SHIFT 9 1056 #define TSP_PVR1_SRC_MASK 0x7000 1057 #define TSP_PVR1_SRC_SHIFT 12 1058 #define TSP_PVR2_SRC_MASK_L 0x8000 1059 #define TSP_PVR2_SRC_SHIFT_L 15 1060 1061 REG16 PCR_Cfg; // 0xbf802d44 0x51 1062 #define TSP_PVR2_SRC_MASK_H 0x0003 1063 #define TSP_PVR2_SRC_SHIFT_H 0 1064 #define TSP_AUDC_SRC_MASK 0x001C 1065 #define TSP_AUDC_SRC_SHIFT 2 1066 #define TSP_AUDD_SRC_MASK 0x00E0 1067 #define TSP_AUDD_SRC_SHIFT 5 1068 #define TSP_TEI_SKIP_PKT_PCR0 0x0100 1069 #define TSP_PCR0_RESET 0x0200 1070 #define TSP_PCR0_INT_CLR 0x0400 1071 #define TSP_PCR0_READ 0x0800 1072 #define TSP_TEI_SKIP_PKT_PCR1 0x1000 1073 #define TSP_PCR1_RESET 0x2000 1074 #define TSP_PCR1_INT_CLR 0x4000 1075 #define TSP_PCR1_READ 0x8000 1076 1077 REG32 STC_DIFF_BUF; // 0xbf802d48 0x52 1078 1079 REG32 STC_DIFF_BUF_H; // 0xbf802d50 0x54 1080 #define TSP_STC_DIFF_BUF_H_MASK 0x0000000F 1081 #define TSP_STC_DIFF_BUF_H_AHIFT 0 1082 1083 REG32 VQ1_Base; // 0xbf802d58 0x56 1084 1085 REG32 _xbf202d60_6C[2]; // 0xbf802d60 0x58~0x5B 1086 1087 REG16 VQ1_Size; // 0xbf802d70 0x5C 1088 #define TSP_VQ1_SIZE_208PK_MASK 0xffff 1089 #define TSP_VQ1_SIZE_208PK_SHIFT 0 1090 1091 REG16 VQ1_Config; // 0xbf802d74 0x5d 1092 #define TSP_VQ1_WR_THRESHOLD_MASK 0x000F 1093 #define TSP_VQ1_WR_THRESHOLD_SHIFT 0 1094 #define TSP_VQ1_PRI_THRESHOLD_MASK 0x00F0 1095 #define TSP_VQ1_PRI_THRESHOLD_SHIFT 4 1096 #define TSP_VQ1_FORCEFIRE_CNT_1K_MASK 0x0F00 1097 #define TSP_VQ1_FORCEFIRE_CNT_1K_SHIFT 8 1098 #define TSP_VQ1_RESET 0x1000 1099 #define TSP_VQ1_OVF_INT_EN 0x4000 1100 #define TSP_VQ1_CLR_OVF_INT 0x8000 1101 1102 REG32 VQ2_Base; // 0xbf802d78 0x5E 1103 1104 REG32 TS_WatchDog_Cnt; // 0xbf802d80 0x60 1105 #define TSP_TS_WATCH_DOG_MASK 0xFFFF0000 1106 #define TSP_TS_WATCH_DOG_SHIFT 16 1107 1108 REG32 Bist_Fail; // 0xbf802d88 0x62 1109 #define TSP_BIST_FAIL_STATUS_MASK 0x00FF0000 1110 #define TSP_BIST_FAIL_STATUS_SRAM1P192x8_MASK 0x00070000 1111 #define TSP_BIST_FAIL_STATUS_SRAM2P512x32w8 0x00080000 1112 #define TSP_BIST_FAIL_STATUS_SRAM2P16x128_MASK 0x00600000 1113 #define TSP_BIST_FAIL_STATUS_SRAM1P2048x32w8 0x00800000 1114 #define TSP_BIST_FAIL_STATUS_SRAM1P1024x32w8 0x01000000 1115 #define TSP_BIST_FAIL_STATUS_SRAM1P512x20 0x00200000 1116 1117 REG16 VQ2_Size; // 0xbf802d90 0x64 1118 #define TSP_VQ2_SIZE_208PK_MASK 0xffff 1119 #define TSP_VQ2_SIZE_208PK_SHIFT 0 1120 1121 REG16 VQ2_Config; // 0xbf802d90 0x65 1122 #define TSP_VQ2_WR_THRESHOLD_MASK 0x000F 1123 #define TSP_VQ2_WR_THRESHOLD_SHIFT 0 1124 #define TSP_VQ2_PRI_THRESHOLD_MASK 0x00F0 1125 #define TSP_VQ2_PRI_THRESHOLD_SHIFT 4 1126 #define TSP_VQ2_FORCEFIRE_CNT_1K_MASK 0x0F00 1127 #define TSP_VQ2_FORCEFIRE_CNT_1K_SHIFT 8 1128 #define TSP_VQ2_RESET 0x1000 1129 #define TSP_VQ2_OVF_INT_EN 0x4000 1130 #define TSP_VQ2_CLR_OVF_INT 0x8000 1131 1132 REG32 VQ_STATUS; // 0xbf802d98 0x66 1133 #define TSP_VQ_STATUS_MASK 0xFFFFFFFF 1134 #define TSP_VQ_STATUS_SHIFT 0 1135 #define TSP_VQ0_STATUS_READ_EVER_FULL 0x00001000 1136 #define TSP_VQ0_STATUS_READ_EVER_OVERFLOW 0x00002000 1137 #define TSP_VQ0_STATUS_EMPTY 0x00004000 1138 #define TSP_VQ0_STATUS_READ_BUSY 0x00008000 1139 #define TSP_VQ1_STATUS_READ_EVER_FULL 0x00010000 1140 #define TSP_VQ1_STATUS_READ_EVER_OVERFLOW 0x00020000 1141 #define TSP_VQ1_STATUS_EMPTY 0x00040000 1142 #define TSP_VQ1_STATUS_READ_BUSY 0x00080000 1143 #define TSP_VQ2_STATUS_READ_EVER_FULL 0x00100000 1144 #define TSP_VQ2_STATUS_READ_EVER_OVERFLOW 0x00200000 1145 #define TSP_VQ2_STATUS_EMPTY 0x00400000 1146 #define TSP_VQ2_STATUS_READ_BUSY 0x00800000 1147 #define TSP_VQ0_STATUS_TX_OVERFLOW 0x10000000 1148 #define TSP_VQ1_STATUS_TX_OVERFLOW 0x20000000 1149 #define TSP_VQ2_STATUS_TX_OVERFLOW 0x40000000 1150 1151 REG32 DM2MI_WAddr_Err; // 0xbf802da0 0x68 , DM2MI_WADDR_ERR0 1152 1153 REG32 ORZ_DMAW_WAddr_Err; // 0xbf802da8 0x6a , ORZ_WADDR_ERR0 1154 1155 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c 1156 /* 1157 [7] : PVR2 meet_tail or PVR2_meet_mid 1158 [6] : vq0, vq1, vq2, vq3 overflow interrupt 1159 [5] : all DMA write address not in the protect zone interrupt 1160 [4] : PVR_cb meet the mid or PVR_cb meet the tail 1161 [3] : pcr filter 0 update finish 1162 [2] : pcr filter 1 update finish 1163 [1] : OTV HW interrupt 1164 [0] : reserved 1165 */ 1166 #define TSP_HWINT2_EN_MASK 0x00FF 1167 #define TSP_HWINT2_EN_SHIFT 0 1168 #define TSP_HWINT2_OTV_EN 0x0002 1169 #define TSP_HWINT2_PCR1_UPDATE_END_EN 0x0004 1170 #define TSP_HWINT2_PCR0_UPDATE_END_EN 0x0008 1171 #define TSP_HWINT2_ALL_DMA_WADDR_NOT_IN_PROCT_Z_EN 0x0020 1172 #define TSP_HWINT2_VQ0_VQ1_VQ2_VQ3_OVERFLOW_EN 0x0040 1173 #define TSP_HWINT2_PVR2_MID_TAIL_STATUS_EN 0x0080 1174 #define TSP_HWINT_PVR (TSP_HWINT2_PVR2_MID_TAIL_STATUS_EN) //@FIXME check what is this doing 1175 #define TSP_HWINT2_SUPPORT_ALL (TSP_HWINT2_PCR0_UPDATE_END_EN|TSP_HWINT2_PCR1_UPDATE_END_EN|TSP_HWINT2_OTV_EN) 1176 #define TSP_HWINT2_ALL TSP_HWINT2_SUPPORT_ALL 1177 1178 #define TSP_HWINT2_STATUS_MASK 0xFF00 1179 #define TSP_HWINT2_STATUS_SHIFT 8 1180 #define TSP_HWINT2_OTV 0x0200 1181 #define TSP_HWINT2_PCR1_UPDATE_END 0x0400 1182 #define TSP_HWINT2_PCR0_UPDATE_END 0x0800 1183 #define TSP_HWINT2_ALL_DMA_WADDR_NOT_IN_PROCT_Z 0x2000 1184 #define TSP_HWINT2_VQ0_VQ1_VQ2_VQ3_OVERFLOW 0x4000 1185 #define TSP_HWINT2_PVR2_MID_TAIL_STATUS 0x8000 1186 1187 REG32 SwInt_Stat1_H; // 0xbf802dB4 0x6d 1188 1189 REG16 _xbf202dbc; // 0xbf802dBC 0x6f 1190 1191 REG32 TimeStamp_FileIn; // 0xbf802dC0 0x70 1192 1193 REG16 HW2_Config3; // 0xbf802dC8 0x72 1194 #define TSP_PVR_DMAW_PROTECT_EN 0x0001 1195 #define TSP_WADDR_ERR_SRC_SEL_MASK 0x0006 1196 #define TSP_WADDR_ERR_SRC_SEL_SHIFT 1 1197 #define TSP_WADDR_ERR_SRC_PVR 0x0000 1198 #define TSP_WADDR_ERR_SRC_VQ 0x0002 1199 #define TSP_WADDR_ERR_SRC_SEC_CB 0x0004 1200 #define TSP_RM_OVF_GLITCH 0x0008 1201 #define TSP_FILEIN_RADDR_READ 0x0010 1202 #define TSP_DUP_PKT_CNT_CLR 0x0040 1203 #define TSP_DMA_FLUSH_EN 0x0080 //PVR1, PVR2 dma flush 1204 #define TSP_REC_AT_SYNC_DIS 0x0100 1205 #define TSP_PVR1_ALIGN_EN 0x0200 1206 #define TSP_REC_FORCE_SYNC_EN 0x0400 1207 #define TSP_RM_PKT_DEMUX_PIPE 0x0800 1208 #define TSP_VQ_EN 0x4000 1209 #define TSP_VQ2PINGPONG_EN 0x8000 1210 1211 REG16 PVRConfig; // 0xbf802dCC 0x73 1212 #define TSP_PVR1_REC_ALL_EN 0x0001 1213 #define TSP_PVR2_REC_ALL_EN 0x0002 1214 #define TSP_REC_NULL 0x0004 1215 #define TSP_REC_ALL_OLD 0x0008 1216 #define TSP_MATCH_PID_SEL_MASK 0x0700 1217 #define TSP_MATCH_PID_SEL_SHIFT 8 1218 #define TSP_MATCH_PID_LD 0x8000 1219 1220 REG32 VQ3_Base; //0x74~75 1221 1222 REG16 VQ3_Size; // 0x76 1223 #define TSP_VQ3_SIZE_208PK_MASK 0xffff 1224 #define TSP_VQ3_SIZE_208PK_SHIFT 0 1225 1226 REG16 VQ3_Config; //0x77 1227 #define TSP_VQ3_WR_THRESHOLD_MASK 0x000F 1228 #define TSP_VQ3_WR_THRESHOLD_SHIFT 0 1229 #define TSP_VQ3_PRI_THRESHOLD_MASK 0x00F0 1230 #define TSP_VQ3_PRI_THRESHOLD_SHIFT 4 1231 #define TSP_VQ3_FORCEFIRE_CNT_1K_MASK 0x0F00 1232 #define TSP_VQ3_FORCEFIRE_CNT_1K_SHIFT 8 1233 #define TSP_VQ3_RESET 0x1000 1234 #define TSP_VQ3_OVF_INT_EN 0x4000 1235 #define TSP_VQ3_CLR_OVF_INT 0x8000 1236 1237 REG32 VQ_RX_Status; // 0xbf802de0 0x78 1238 #define VQ_RX_ARBITER_MODE_MASK 0x0000000F 1239 #define VQ_RX_ARBITER_MODE_SHIFT 0 1240 #define VQ_RX0_PRI_MASK 0x000000F0 1241 #define VQ_RX0_PRI_SHIFT 4 1242 #define VQ_RX1_PRI_MASK 0x00000F00 1243 #define VQ_RX1_PRI_SHIFT 8 1244 #define VQ_RX2_PRI_MASK 0x0000F000 1245 #define VQ_RX2_PRI_SHIFT 12 1246 1247 REG32 _xbf802de8; // 0xbf802dC0 0x7a 1248 1249 REG32 MCU_Data1; // 0xbf802dC0 0x7c 1250 } REG_Ctrl; 1251 1252 //TSP 3 1253 typedef struct _REG_Ctrl2 //TSP3 0x1702 1254 { 1255 REG16 CFG_00; // 0x00 1256 #define CFG_00_TSP_FILE_IN_TSIF1_EN 0x0001 //Set 1: Enable FILE_input 1257 #define CFG_00_MEM_TS_DATA_ENDIAN_TSIF1 0x0002 //Set 1 to swap the byte order of TSIF1 DMA DATA bus 1258 #define CFG_00_TSP_FILE_SEGMENT_TSIF1 0x0004 1259 #define CFG_00_FILEIN_RADDR_READ_TSIF1 0x0008 //Read file DMA read address 1260 #define CFG_00_MEM_TS_W_ORDER_TSIF1 0x0010 //Set 1 to swap the word order of TSIF1 MIU DATA bus 1261 #define CFG_00_DIS_MIU_RQ_TSIF1 0x0020 //Disable the MIU request 1262 #define CFG_00_RST_TS_FIN1 0x0040 //reset TSIF1 1263 #define CFG_00_RST_FILEIN_TSIF1 0x0080 //reset the TSIF1 file in path 1264 #define CFG_00_RST_CMDQ_FILEIN_TSIF1 0x0100 //reset the file in TSIF1 command queue 1265 #define CFG_00_WB_RST_FILEIN_TSIF1 0x0200 //reset DMA to TSIF FSM in TSP clock Domain 1266 #define CFG_00_RST_WB_DMA_FILEIN_TSIF1 0x0400 //reset TSIF1 DMA in TSP clock Domain 1267 #define CFG_00_FILE2MI_PRI_TSIF1 0x0800 //Set 1: Higher MIU ABT read priority 1268 #define CFG_00_RST_READ_DMA_1 0x1000 //reset TSIF1 DMA in MIU clock Domain 1269 #define CFG_00_LPCR2_LOAD_TSIF1 0x2000 //Load lpcr2 from TSIF1 90k counter 1270 #define CFG_00_LPCR2_LOAD_BUF1 0x4000 //Load lpcr2 from pdflt1_buffer 90k counter 1271 #define CFG_00_LPCR2_LOAD_BUF0 0x8000 //Load lpcr2 from pdflt0_buffer 90k counter 1272 REG16 CFG_01; // 0x01 1273 #define CFG_01_TSP_FILE_SEGMENT1 0x0001 1274 #define CFG_01_TIMER_EN1 0x0002 //1: enable byte delay timer for TSIF1 filein path 0: packet delay timer 1275 #define CFG_01_PKT192_EN1 0x0004 //Set 1 to enable TS packets with 192 bytes on file-in mode. (Blocking TS packets by timestamp) 1276 #define CFG_01_PKT192_BLK_DISABLE1 0x0008 //Set 1 to disable file-in timestamp block scheme 1277 #define CFG_01_LPCR2_WLD1 0x0010 //Set PCR to TSIF1 90k counter 1278 #define CFG_01_TS_DATA_PORT_SEL1 0x0020 //TSIF1 data port output select. 0: select live TS to be TSIF output 1: select data port to be TSIF output 1279 #define CFG_01_PDFLT2_FILE_SRC 0x00c0 //00:disable 01:tsif0 file in port 10:tsif1 file in port 11:disable 1280 #define CFG_01_PDFLT2_FILE_SRC_SHIFT 6 1281 1282 #define CFG_01_PCR0_SRC_MASK 0x0f00 1283 #define CFG_01_PCR0_SRC_SHIFT 8 1284 #define CFG_01_PCR0_SRC_TSIF0 0x0 1285 #define CFG_01_PCR0_SRC_TSIF1 0x1 1286 #define CFG_01_PCR0_SRC_TSIF2 0x2 1287 #define CFG_01_PCR0_SRC_TSIF3 0x3 1288 #define CFG_01_PCR0_SRC_TSIF4 0x4 1289 #define CFG_01_PCR0_SRC_TSIF5 0x5 1290 #define CFG_01_PCR0_SRC_PKT_MERGE0 0x8 1291 #define CFG_01_PCR0_SRC_PKT_MERGE1 0x9 1292 #define CFG_01_PCR0_SRC_MM_FILEIN0 0xa 1293 #define CFG_01_PCR0_SRC_MM_FILEIN1 0xb 1294 #define CFG_01_PCR0_SRC_FIQ0 0xc 1295 #define CFG_01_PCR0_SRC_FIQ1 0xd 1296 1297 #define CFG_01_PCR1_SRC_MASK 0xf000 1298 #define CFG_01_PCR1_SRC_SHIFT 12 1299 #define CFG_01_PCR1_SRC_TSIF0 0x0 1300 #define CFG_01_PCR1_SRC_TSIF1 0x1 1301 #define CFG_01_PCR1_SRC_TSIF2 0x2 1302 #define CFG_01_PCR1_SRC_TSIF3 0x3 1303 #define CFG_01_PCR1_SRC_TSIF4 0x4 1304 #define CFG_01_PCR1_SRC_TSIF5 0x5 1305 #define CFG_01_PCR1_SRC_PKT_MERGE0 0x8 1306 #define CFG_01_PCR1_SRC_PKT_MERGE1 0x9 1307 #define CFG_01_PCR1_SRC_MM_FILEIN0 0xa 1308 #define CFG_01_PCR1_SRC_MM_FILEIN1 0xb 1309 #define CFG_01_PCR1_SRC_FIQ0 0xc 1310 #define CFG_01_PCR1_SRC_FIQ1 0xd 1311 REG16 CFG_02; 1312 #define CFG_02_PKT_CHK_SIZE_FIN1 0x00ff //(Packet Size - 1) for sync detection in TSIF1 1313 #define CFG_02_PKT_DEMUX_SIZE_1 0xff00 //(Packet Size - 1) for sync detection in pkt_demux1 1314 #define CFG_02_PKT_DEMUX_SIZE_1_SHIFT 8 1315 REG16 CFG_03; 1316 #define CFG_03_TSP_FILE_TIMER1 0xffff //Bit [15:0] of timer threshold for TS file playback data fetch from MIU. 1317 REG16 CFG_04; 1318 #define CFG_04_TSP_FILEIN_ABORT_ECO_TSIF0 0x0001 1319 #define CFG_04_TSP_FILEIN_ABORT_ECO_TSIF1 0x0002 1320 #define CFG_04_TSP_FILEIN_ABORT_ECO_TSIF2 0x0004 1321 #define CFG_04_TSP_FILEIN_ABORT_ECO_TSIF3 0x0008 1322 REG16 CFG_05; 1323 #define CFG_05_TSP_FILEIN_TSIF2 0x0001 //Set 1 to swap the word order of TSIF2 MIU DATA bus 1324 #define CFG_05_MEM_TS_DATA_EDIAN_TSIF2 0x0002 //Set 1 to swap the byte order of TSIF2 DMA DATA bus 1325 #define CFG_05_TSP_FILE_SEGMENT_TSIF2 0x0004 //set 0 to enable file in alignment mdoe 1326 #define CFG_05_FILEIN_RDDR_READ_TSIF2 0x0008 //Read file DMA read address 1327 #define CFG_05_MEM_TS_W_ORDER_TSIF2 0x0010 //Set 1: Enable FILE_input 1328 #define CFG_05_DIS_MIU_RQ_TSIF2 0x0020 //Disable the MIU request 1329 #define CFG_05_RST_TS_FIN2 0x0040 //reset TSIF2 1330 #define CFG_05_RST_FILEIN_TSIF2 0x0080 //reset the TSIF2 file in path 1331 #define CFG_05_RST_CMDQ_FILEIN_TSIF2 0x0100 //reset the file in TSIF2 command queue 1332 #define CFG_05_WB_RST_FILEIN_TSIF2 0x0200 //reset DMA to TSIF FSM in TSP clock Domain 1333 #define CFG_05_RST_WB_DMA_FILEIN_TSIF2 0x0400 //reset TSIF2 DMA in TSP clock Domain 1334 #define CFG_05_FILE2MI_PRI_TSIF2 0x0800 //Set 1: Higher MIU ABT read priority 1335 #define CFG_05_RST_READ_DMA_2 0x1000 //reset TSIF1 DMA in MIU clock Domain 1336 #define CFG_05_LPCR2_LOAD_TSIF2 0x2000 //Load lpcr2 from TSIF2 90k counter 1337 #define CFG_05_LPCR2_LOAD_BUF2 0x4000 //Load lpcr2 from pdflt2_buffer 90k counter 1338 REG16 CFG_06; 1339 #define CFG_06_TSP_FILE_SEGMENT2 0x0001 //set 0 to enable file in alignment mdoe 1340 #define CFG_06_TSP_TIMER_EN2 0x0002 //1: enable byte delay timer for TSIF2 filein path 0: packet delay timer 1341 #define CFG_06_TSP_PKT192_EN2 0x0004 //Set 1 to enable TS packets with 192 bytes on file-in mode. (Blocking TS packets by timestamp) 1342 #define CFG_06_TSP_PKT192_BLK_DISABLE2 0x0008 //Set 1 to disable file-in timestamp block scheme 1343 #define CFG_06_LPCR2_WLD2 0x0010 //Set PCR to TSIF2 90k counter 1344 #define CFG_06_TS_DATA_PORT_SEL2 0x0020 //TSIF2 data port output select. 0: select live TS to be TSIF output 1: select data port to be TSIF output 1345 #define CFG_06_PIDFLT5_FILE_SRC 0x00C0 //pdflt5 file in source 00:disable 01:tsif2 file in port 10:tsif3 file in port 11:disable 1346 #define CFG_06_PIDFLT5_FILE_SRC_SHIFT 6 1347 #define CFG_06_PCR0_ID_SEL 0x0700 //pkt merge multi-stream id select 0: stream 0 1: stream 1 2: stream 2 3: stream 3 1348 #define CFG_06_PCR0_ID_SEL_SHFIT 8 1349 #define CFG_06_PCR1_ID_SEL 0x3800 //pkt merge multi-stream id select 0: stream 0 1: stream 1 2: stream 2 3: stream 3 1350 #define CFG_06_PCR1_ID_SEL_SHFIT 11 1351 REG16 CFG_07; 1352 #define CFG_07_PKT_CHK_SIZE_FILEIN2 0x00ff //(Packet Size �V 1) for sync detection in TSIF2 1353 #define CFG_07_PKTDMX_SIZE2 0xff00 //(Packet Size �V 1) for sync detection in pkt_demux2 1354 #define CFG_07_PKTDMX_SIZE2_SHIFT 8 1355 REG16 CFG_08; 1356 #define CFG_08_TSP_FILE_TIMER2 0x00ff 1357 REG16 CFG_09; // reserved 1358 REG16 CFG_0A; 1359 #define CFG_0A_TSP_FILE_IN_TSIF3 0x0001 //Set 1: Enable FILE_input 1360 #define CFG_0A_MEM_TS_DATA_EDIAN_TSIF3 0x0002 //Set 1 to swap the byte order of TSIF3 DMA DATA bus 1361 #define CFG_0A_TSP_FILE_SEGMENT_TSIF3 0x0004 //set 0 to enable file in alignment mdoe 1362 #define CFG_0A_FILEIN_RADDR_READ_TSIF3 0x0008 //Read file DMA read address 1363 #define CFG_0A_MEM_TS_W_ORDER_TSIF3 0x0010 //Set 1: Enable FILE_input 1364 #define CFG_0A_DIS_MIU_RQ_TSIF3 0x0020 //Set 1 to swap the byte order of TSIF3 DMA DATA bus 1365 #define CFG_0A_RST_TS_FIN3 0x0040 //set 0 to enable file in alignment mdoe 1366 #define CFG_0A_RST_FILEIN_TSIF3 0x0080 //Read file DMA read address 1367 #define CFG_0A_RST_CMDQ_FILEIN_TSIF3 0x0100 //reset the file in TSIF3 command queue 1368 #define CFG_0A_WB_RST_FILEIN_TSIF3 0x0200 //reset DMA to TSIF FSM in TSP clock Domain 1369 #define CFG_0A_RST_WB_DMA_FILEIN_TSIF3 0x0400 //reset TSIF3 DMA in TSP clock Domain 1370 #define CFG_0A_FILE2MI_PRI_TSIF3 0x0800 //Set 1: Higher MIU ABT read priority 1371 #define CFG_0A_RST_READ_DMA_3 0x1000 //reset TSIF3 DMA in MIU clock Domain 1372 #define CFG_0A_LPCR2_LOAD_TSIF3 0x2000 //Load lpcr2 from TSIF3 90k counter 1373 #define CFG_0A_LPCR2_LOAD_BUF3 0x4000 //Load lpcr2 from pdflt3_buffer 90k counter 1374 REG16 CFG_0B; 1375 #define CFG_0B_TSP_FILE_SEGMENT3 0x0001 //set 0 to enable file in alignment mdoe 1376 #define CFG_0B_TIMER_EN3 0x0002 //1: enable byte delay timer for TSIF3 filein path 0: packet delay timer 1377 #define CFG_0B_PKT192_EN3 0x0004 //Set 1 to enable TS packets with 192 bytes on file-in mode. (Blocking TS packets by timestamp) 1378 #define CFG_0B_PKT192_BLK_DISABLE3 0x0008 //Set 1 to disable file-in timestamp block scheme 1379 #define CFG_0B_LPCR2_WLD3 0x0010 //Set PCR to TSIF3 90k counter 1380 #define CFG_0B_TS_DATA_PORT_SEL3 0x0020 //TSIF3 data port output select. 0: select live TS to be TSIF output 1: select data port to be TSIF output 1381 #define CFG_0B_P_SEL3 0x0040 //select parallel TS interface for TSIF3 1382 #define CFG_0B_EXT_SYNC_SEL3 0x0080 //select exteranl sync for ts_if3 1383 #define CFG_0B_TS_IF3_EN 0x0100 //set 1 tsif3 live in enable 1384 #define CFG_0B_TS_DATA3_SWAP 0x0200 //tsif3 live in bit order swap 1385 REG16 CFG_0C; 1386 #define CFG_0C_PKT_CHK_SIZE_FILEIN3 0x00ff //(Packet Size �V 1) for sync detection in TSIF3 1387 #define CFG_0C_PKT_DMX_SIZE3 0xff00 //(Packet Size �V 1) for sync detection in pkt_demux3 1388 #define CFG_0C_PKT_DMX_SIZE3_SHIFT 8 1389 1390 REG16 CFG_0D; 1391 #define CFG_0D_TSP_FILE_TIMER3 0xffff //Bit [15:0] of timer threshold for TS file playback data fetch from MIU. 1392 1393 REG16 CFG_0E; 1394 #define CFG_0E_PKT_DEMUX_SIZE_0 0x00ff //(Packet Size - 1) for sync detection in pkt_demux0 1395 #define CFG_0E_PKT_SIZE3 0xff00 //(Packet Size �V 1) for sync detection in pkt_flt3 1396 #define CFG_0E_PKT_SIZE3_SHIFT 8 1397 1398 REG16 CFG_0F; 1399 #define CFG_0F_PKT_CHK_SIZE3 0x00ff //(Packet Size �V 1) for sync detection in TSIF3. 1400 #define CFG_0F_SYNC_BYTE3 0xff00 //Sync byte for TSIF3 1401 #define CFG_0F_SYNC_BYTE3_SHIFT 8 1402 1403 REG16 CFG_10; 1404 #define CFG_10_RESET_PDFLT0 0x0001 //reset Pdflt0 1405 #define CFG_10_RESET_PDFLT1 0x0002 //reset Pdflt1 1406 #define CFG_10_RESET_PDFLT2 0x0004 //reset Pdflt2 1407 #define CFG_10_RESET_PDFLT3 0x0008 //reset Pdflt3 1408 REG16 CFG_11; 1409 #define CFG_11_RECEIVE_BUF0_SRC 0x0003 //Receive BUF0 input Stream source selection 00: pkt_merge0 01: pkt_merge1 10: Dscrmb 1410 #define CFG_11_RECEIVE_BUF0_SRC_SHIFT 0 1411 #define CFG_11_RECEIVE_BUF1_SRC 0x000c //Receive BUF1 input Stream source selection 00: pkt_merge0 01: pkt_merge1 10: Dscrmb 1412 #define CFG_11_RECEIVE_BUF1_SRC_SHIFT 2 1413 #define CFG_11_RECEIVE_BUF2_SRC 0x0030 //Receive BUF2 input Stream source selection 00: pkt_merge0 01: pkt_merge1 10: Dscrmb 1414 #define CFG_11_RECEIVE_BUF2_SRC_SHIFT 4 1415 #define CFG_11_RECEIVE_BUF3_SRC 0x00c0 //Receive BUF3 input Stream source selection 00: pkt_merge0 01: pkt_merge1 10: Dscrmb 1416 #define CFG_11_RECEIVE_BUF3_SRC_SHIFT 6 1417 REG16 CFG_12; 1418 #define CFG_12_TIMESTAMP_SEL_PVR1 0x0001 //PVR1 timestamp sel 0:local timestamp 1:stream timestamp 1419 #define CFG_12_TIMESTAMP_SEL_PVR2 0x0002 //PVR2 timestamp sel 0:local timestamp 1:stream timestamp 1420 #define CFG_12_TIMESTAMP_SEL_PVR3 0x0004 //PVR3 timestamp sel 0:local timestamp 1:stream timestamp 1421 #define CFG_12_TIMESTAMP_SEL_PVR4 0x0008 //PVR4 timestamp sel 0:local timestamp 1:stream timestamp 1422 1423 #define CFG_12_REG_REST_RBF0 0x0010 //reset Receive buffer0 1424 #define CFG_12_REG_REST_RBF1 0x0020 //reset Receive buffer1 1425 #define CFG_12_REG_REST_RBF2 0x0040 //reset Receive buffer2 1426 #define CFG_12_REG_REST_RBF3 0x0080 //reset Receive buffer2 1427 1428 #define CFG_12_REG_REST_PDBF0 0x0400 //reset Pdflt_buf0 1429 #define CFG_12_REG_REST_PDBF1 0x0800 //reset Pdflt_buf1 1430 #define CFG_12_REG_REST_PDBF2 0x1000 //reset Pdflt_buf2 1431 #define CFG_12_REG_REST_PDBF3 0x2000 //reset Pdflt_buf3 1432 REG16 CFG_13; 1433 #define CFG_13_LPCR_WLD0 0x0001 //Set PCR to pdflt_buf0 90k counter 1434 #define CFG_13_LPCR_EN0 0x0002 //Enable Pdflt_buf0 90k counter 1435 #define CFG_13_LPCR_WLD1 0x0004 //Set PCR to pdflt_buf1 90k counter 1436 #define CFG_13_LPCR_EN1 0x0008 //Enable Pdflt_buf1 90k counter 1437 #define CFG_13_LPCR_WLD2 0x0010 //Set PCR to pdflt_bu 1438 #define CFG_13_LPCR_EN2 0x0020 //Enable Pdflt_buf1 90k counter 1439 #define CFG_13_LPCR_WLD3 0x0040 //Set PCR to pdflt_bu 1440 #define CFG_13_LPCR_EN3 0x0080 //Enable Pdflt_buf1 90k counter 1441 #define CFG_13_REG_RESET_ABT0 0x4000 //reset pkt_merge0 1442 #define CFG_13_REG_RESET_ABT1 0x8000 //reset pkt_merge1 1443 REG16 CFG_14; 1444 #define CFG_14_ABT_PORT0_SRC 0x0007 //pkt_merge0 input Stream source selection 0: tsif0 stream 1: tsif1 stream 2: tsif2 stream 3: tsif3 stream 4: tsif4 stream 5: tsif5 stream 1445 #define CFG_14_ABT_PORT0_SRC_SHIFT 0 1446 #define CFG_14_ABT_PORT1_SRC 0x0038 //pkt_merge0 input Stream source selection 1: tsif0 stream 1: tsif1 stream 2: tsif2 stream 3: tsif3 stream 4: tsif4 stream 5: tsif5 stream 1447 #define CFG_14_ABT_PORT1_SRC_SHIFT 3 1448 #define CFG_14_ABT_PORT2_SRC 0x01c0 //pkt_merge0 input Stream source selection 2: tsif0 stream 1: tsif1 stream 2: tsif2 stream 3: tsif3 stream 4: tsif4 stream 5: tsif5 stream 1449 #define CFG_14_ABT_PORT2_SRC_SHIFT 6 1450 #define CFG_14_ABT_PORT3_SRC 0x1E00 //pkt_merge0 input Stream source selection 2: tsif0 stream 1: tsif1 stream 2: tsif2 stream 3: tsif3 stream 4: tsif4 stream 5: tsif5 stream 1451 #define CFG_14_ABT_PORT3_SRC_SHIFT 9 1452 REG16 CFG_15; 1453 #define CFG_15_RBUF_FULL_LEVEL 0x0038 1454 #define CFG_15_PVR3_SRC 0x0e00 //PVR3 input path sel 000: pkt_demux0 001: pkt_demux1 010: pkt_demux2 011: pkt_demux3 100: pkt_demux4 101: pkt_demux5 1455 #define CFG_15_PVR3_SRC_SHIFT 9 1456 #define CFG_15_PVR4_SRC 0x7000 //PVR4input path sel 000: pkt_demux0 001: pkt_demux1 010: pkt_demux2 011: pkt_demux3 100: pkt_demux4 101: pkt_demux5 1457 #define CFG_15_PVR4_SRC_SHIFT 12 1458 1459 REG16 CFG_16; 1460 #define CFG_16_PVR3_REG_PINGPONG_EN 0x0001 //set 1 to enable the pingpong buffer of PVR3 1461 #define CFG_16_PVR3_STR2MI_EN 0x0002 //set 1 to enable PVR3 1462 #define CFG_16_PVR3_STR2MI_RST_WADR 0x0004 //set 1 to reset the PVR3 write pointer to the head address 1463 #define CFG_16_PVR3_STR2MI_PAUSE 0x0008 //set 1 to pause PVR3 1464 #define CFG_16_PVR3_PKT192_EN 0x0010 //set 1 to enable 192 mode of PVR3 1465 #define CFG_16_PVR3_BURST_LEN_MASK 0x0060 //the PVR3 dma burst length 00 : burst 8 01 : burst 4 10/11 : burst 1 1466 #define CFG_16_PVR3_BURST_LEN_SHIFT 5 1467 #define CFG_16_PVR3_LPCR1_WLD 0x0080 //set 1 to write the value of lpcr1 from the register to the lpcr1_buf for PVR3 1468 #define CFG_16_PVR3_PVR_ALIGN_EN 0x0100 //set 1 to enable the function of alignment of PVR3 1469 #define CFG_16_PVR3_STR2MI_DSWAP 0x0200 //set 1 to swap the bit order of stream2miu data bus of PVR3 1470 #define CFG_16_PVR3_STR2MI_BT_ORDER 0x0400 //Byte order of 16-byte recoding buffer to MIU of PVR3 0: Little endian. 1: Big endian 1471 #define CFG_16_REC_DATA3_INV_EN 0x0800 //Set 1 to enable data payload invert for PVR record 1472 #define CFG_16_PVR3_BLOCK_DIS 0x1000 //set 1 to disable the PVR3 fifo blocking mechanism 1473 #define CFG_16_PID_BYPASS3_REC 0x2000 //0: record PES 1: record 188/192 1474 #define CFG_16_REC_ALL3 0x4000 //set 1 to record all 1475 #define CFG_16_PVR3_LPCR1_RLD 0x8000 //set 1 to read the value of lpcr1 from the register to the lpcr1_buf for PVR3 1476 REG32 CFG_17_18; 1477 #define CFG_17_18_PVR3_STR2MI_HEAD 0xffffffff //[31:27] : reserved [26:0] : MIU start address1 of TS recoding buffer for PVR3 1478 REG32 CFG_19_1A; 1479 #define CFG_19_1A_PVR3_STR2MI_MID 0xffffffff //[31:27] : reserved [26:0] : MIU middle address1 of TS recoding buffer for PVR3. 1480 REG32 CFG_1B_1C; 1481 #define CFG_1B_1C_PVR3_STR2MI_TAIL 0xffffffff //[31:27] : reserved [26:0] : MIU tail address1 of TS recoding buffer for PVR3. 1482 REG32 CFG_1D_1E; 1483 #define CFG_1D_1E_PVR3_STR2MI_HEAD2 0xffffffff //[31:27] : reserved [26:0] : MIU start address2 of TS recoding buffer for PVR3 1484 REG32 CFG_1F_20; 1485 #define CFG_1F_20_PVR3_STR2MI_MID2 0xffffffff //[31:27] : reserved [26:0] : MIU middle address2 of TS recoding buffer for PVR3. 1486 REG32 CFG_21_22; 1487 #define CFG_21_22_PVR3_STR2MI_TAIL2 0xffffffff //[31:27] : reserved [26:0] : MIU tail address2 of TS recoding buffer for PVR3. 1488 1489 REG16 CFG_23; 1490 #define CFG_23_PVR4_REG_PINGPONG_EN 0x0001 //set 1 to enable the pingpong buffer of PVR4 1491 #define CFG_23_PVR4_STR2MI_EN 0x0002 //set 1 to enable PVR4 1492 #define CFG_23_PVR4_STR2MI_RST_WADR 0x0004 //set 1 to reset the PVR4 write pointer to the head address 1493 #define CFG_23_PVR4_STR2MI_PAUSE 0x0008 //set 1 to pause PVR4 1494 #define CFG_23_PVR4_PKT192_EN 0x0010 //set 1 to enable 192 mode of PVR4 1495 #define CFG_23_PVR4_BURST_LEN_MASK 0x0060 //the PVR4 dma burst length 00 : burst 8 01 : burst 4 10/11 : burst 1 1496 #define CFG_23_PVR4_BURST_LEN_SHIFT 5 1497 #define CFG_23_PVR4_LPCR1_WLD 0x0080 //set 1 to write the value of lpcr1 from the register to the lpcr1_buf for PVR4 1498 #define CFG_23_PVR4_PVR_ALIGN_EN 0x0100 //set 1 to enable the function of alignment of PVR4 1499 #define CFG_23_PVR4_STR2MI_DSWAP 0x0200 //set 1 to swap the bit order of stream2miu data bus of PVR4 1500 #define CFG_23_PVR4_STR2MI_BT_ORDER 0x0400 //Byte order of 16-byte recoding buffer to MIU of PVR4 0: Little endian. 1: Big endian 1501 #define CFG_23_REC_DATA4_INV_EN 0x0800 //Set 1 to enable data payload invert for PVR record 1502 #define CFG_23_PVR4_BLOCK_DIS 0x1000 //set 1 to disable the PVR4 fifo blocking mechanism 1503 #define CFG_23_PID_BYPASS4_REC 0x2000 //0: record PES 1: record 188/192 1504 #define CFG_23_REC_ALL4 0x4000 //set 1 to record all 1505 #define CFG_23_PVR4_LPCR1_RLD 0x8000 //set 1 to read the value of lpcr1 from the register to the lpcr1_buf for PVR4 1506 1507 REG32 CFG_24_25; 1508 #define CFG_24_25_PVR4_STR2MI_HEAD 0xffffffff //[31:27] : reserved [26:0] : MIU start address1 of TS recoding buffer for PVR4 1509 REG32 CFG_26_27; 1510 #define CFG_26_27_PVR4_STR2MI_MID 0xffffffff //[31:27] : reserved [26:0] : MIU middle address1 of TS recoding buffer for PVR4 1511 REG32 CFG_28_29; 1512 #define CFG_28_29_PVR4_STR2MI_TAIL 0xffffffff //[31:27] : reserved [26:0] : MIU tail address1 of TS recoding buffer for PVR4 1513 REG32 CFG_2A_2B; 1514 #define CFG_2A_2B_PVR4_STR2MI_HEAD2 0xffffffff //[31:27] : reserved [26:0] : MIU start address2 of TS recoding buffer for PVR4 1515 REG32 CFG_2C_2D; 1516 #define CFG_2C_2D_PVR4_STR2MI_MID2 0xffffffff //[31:27] : reserved [26:0] : MIU middle address2 of TS recoding buffer for PVR4 1517 REG32 CFG_2E_2F; 1518 #define CFG_2E_2F_PVR4_STR2MI_TAIL2 0xffffffff //[31:27] : reserved [26:0] : MIU tail address2 of TS recoding buffer for PVR4 1519 1520 REG32 CFG_30_31; 1521 #define CFG_30_31_REG_TSP_FILEIN_RADDR_TSIF1 0xffffffff //Read start address [23:0] (byte unit) in tsif1 and command queue mode 1522 REG32 CFG_32_33; 1523 #define CFG_32_33_REG_TSP_FILEIN_RNUM_TSIF1 0xffffffff //Read number [23:0] (byte unit) in tsif1 and command queue mode 1524 REG16 CFG_34; 1525 #define CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_START 0x0001 //bit[0] Set 1 to start tsif1 in command 1526 #define CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_DONE 0x0002 //bit[1] 1 : FileIn done 1527 #define CFG_34_REG_TSP_FILEIN_INIT_TRUST_TSIF1 0x0004 //bit[2] filein_init_trust for tsif1 1528 #define CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_ABORT 0x0010 //bit[4] Set 1 to abort tsif1 in command queue mode 1529 REG32 CFG_35_36; 1530 #define CFG_35_36_TSP_FILEIN_RADDR_TSIF2 0xffffffff //[31:24] : reserved [23:0] : Read start address [15:0] [23:16](byte unit) in tsif2 and command queue mode 1531 REG32 CFG_37_38; 1532 #define CFG_37_38_TSP_FILEIN_RNUM_TSIF2 0xffffffff //[31:24] : reserved [23:0] : Read number [15:0] [23:16] (byte unit) in tsif2 and command queue mode 1533 REG16 CFG_39; 1534 #define CFG_39_FILEIN_CTRL_TSIF2_START 0x0001 //bit[0] Set 1 to start tsif2 in command 1535 #define CFG_39_FILEIN_CTRL_TSIF2_DONE 0x0002 //bit[1] 1: FileIn done 1536 #define CFG_39_FILEIN_INIT_TRUST_TSIF2 0x0004 //bit[2] filein_init_trust for tsif2 1537 #define CFG_39_FILEIN_CTRL_TSIF2_ABORT 0x0010 //bit[4] Set 1 to abort tsif2 in command queue mode 1538 REG32 CFG_3A_3B; 1539 #define CFG_3A_3B_TSP_FILEIN_RADDR_TSIF3 0xffffffff //[31:24] : reserved [23:0] : Read start address [15:0] [23:16](byte unit) in tsif2 and command queue mode 1540 REG32 CFG_3C_3D; 1541 #define CFG_3C_3D_TSP_FILEIN_RNUM_TSIF3 0xffffffff //[31:24] : reserved [23:0] : Read number [15:0] [23:16] (byte unit) in tsif2 and command queue mode 1542 REG16 CFG_3E; 1543 #define CFG_3E_FILEIN_CTRL_TSIF3_START 0x0001 //bit[0] Set 1 to start tsif2 in command 1544 #define CFG_3E_FILEIN_CTRL_TSIF3_DONE 0x0002 //bit[1] 1: FileIn done 1545 #define CFG_3E_FILEIN_INIT_TRUST_TSIF3 0x0004 //bit[2] filein_init_trust for tsif3 1546 #define CFG_3E_FILEIN_CTRL_TSIF3_ABORT 0x0010 //bit[4] Set 1 to abort tsif2 in command queue mode 1547 REG16 CFG_3F; 1548 #define CFG_3F_REG_TSIF1_CMD_QUEUE_WR_CNT 0x001f 1549 #define CFG_3F_REG_TSIF1_CMD_QUEUE_FIFO_FULL 0x0040 1550 #define CFG_3F_REG_TSIF1_CMD_QUEUE_FIFO_EMPTY 0x0080 1551 #define CFG_3F_REG_TSIF1_CMD_QUEUE_WR_LEVEL 0x0300 1552 #define CFG_3F_REG_TSIF1_CMD_QUEUE_LEVEL_SHIFT 8 1553 #define CFG_3F_REG_TSIF1_CMD_QUEUE_SIZE 16 1554 REG16 CFG_40; 1555 #define CFG_40_REG_TSIF2_CMD_QUEUE_WR_CNT 0x001f 1556 #define CFG_40_REG_TSIF2_CMD_QUEUE_FIFO_FULL 0x0040 1557 #define CFG_40_REG_TSIF2_CMD_QUEUE_FIFO_EMPTY 0x0080 1558 #define CFG_40_REG_TSIF2_CMD_QUEUE_WR_LEVEL 0x0300 1559 #define CFG_40_REG_TSIF2_CMD_QUEUE_LEVEL_SHIFT 8 1560 #define CFG_40_REG_TSIF2_CMD_QUEUE_SIZE 16 1561 REG16 CFG_41; 1562 #define CFG_41_REG_TSIF3_CMD_QUEUE_WR_CNT 0x001f 1563 #define CFG_41_REG_TSIF3_CMD_QUEUE_FIFO_FULL 0x0040 1564 #define CFG_41_REG_TSIF3_CMD_QUEUE_FIFO_EMPTY 0x0080 1565 #define CFG_41_REG_TSIF3_CMD_QUEUE_WR_LEVEL 0x0300 1566 #define CFG_41_REG_TSIF3_CMD_QUEUE_LEVEL_SHIFT 8 1567 #define CFG_41_REG_TSIF3_CMD_QUEUE_SIZE 16 1568 REG32 CFG_42_43; 1569 #define CFG_42_43_REG_TIMESTAMP_TSP_FILEIN_TSIF1 0xffffffff //tsif1 pkt timestamp 1570 REG32 CFG_44_45; 1571 #define CFG_44_45_REG_TIMESTAMP_TSP_FILEIN_TSIF2 0xffffffff //tsif2 pkt timestamp 1572 REG32 CFG_46_47; 1573 #define CFG_46_47_REG_TIMESTAMP_TSP_FILEIN_TSIF3 0xffffffff //tsif3 pkt timestamp 1574 REG16 CFG_48; 1575 #define CFG_48_REG_INT0 0xffff 1576 REG16 CFG_49; 1577 REG16 CFG_4A_4F[6]; 1578 REG32 CFG_50_51; 1579 #define CFG_50_51_LPCR2_TSIF1_RD 0xffffffff //tsif1 90k counter value 1580 REG32 CFG_52_53; 1581 #define CFG_52_53_LPCR2_TSIF2_RD 0xffffffff //tsif2 90k counter value 1582 REG32 CFG_54_55; 1583 #define CFG_54_55_LPCR2_TSIF3_RD 0xffffffff //tsif3 90k counter value 1584 REG32 CFG_56_57; 1585 #define CFG_56_57_LPCR2_BUF0_RD 0xffffffff // pdflt_buf0 90k counter value 1586 REG32 CFG_58_59; 1587 #define CFG_58_59_LPCR2_BUF1_RD 0xffffffff // pdflt_buf1 90k counter value 1588 REG32 CFG_5A_5B; 1589 #define CFG_5A_5B_LPCR2_BUF2_RD 0xffffffff // pdflt_buf2 90k counter value 1590 REG32 CFG_5C_5D; 1591 #define CFG_5C_5D_LPCR2_BUF3_RD 0xffffffff // pdflt_buf3 90k counter value 1592 REG32 CFG_5E_5F; 1593 #define CFG_5E_5F_LPCR2_BUF4_RD 0xffffffff // pdflt_buf4 90k counter value 1594 REG32 CFG_60_61; 1595 #define CFG_60_61_LPCR2_BUF5_RD 0xffffffff // pdflt_buf5 90k counter value 1596 REG32 CFG_62_63; 1597 #define CFG_62_63_LPCR2_PVR3_RD 0xffffffff // PVR3 90k counter value 1598 REG32 CFG_64_65; // Reserved 1599 #define CFG_64_65_LPCR2_PVR4_RD 0xffffffff // PVR4 90k counter value 1600 REG32 CFG_66_67; 1601 #define CFG_66_67_PVR3_STR2MI_WADR_R 0xffffffff // PVR3 write point 1602 REG32 CFG_68_69; 1603 #define CFG_68_69_PVR4_STR2MI_WADR_R 0xffffffff // PVR4 write point 1604 REG32 CFG_6A_6B; 1605 #define CFG_6A_6B_TSP2MI_RADDR_S_TSIF1 0x0fffffff // tsif1 DMA read point 1606 REG32 CFG_6C_6D; 1607 #define CFG_6C_6D_TSP2MI_RADDR_S_TSIF2 0x0fffffff // tsif2 DMA read point 1608 REG32 CFG_6E_6F; 1609 #define CFG_6E_6F_TSP2MI_RADDR_S_TSIF3 0x0fffffff // tsif3 DMA read point 1610 REG16 CFG_70; 1611 #define CFG_70_MATCHECED_VPID_3D_MASK 0x1fff 1612 #define CFG_70_CHANGE_VPID_3D 0x4000 1613 REG16 CFG_71; 1614 #define CFG_71_MATCHECED_APID_B_MASK 0x1fff 1615 #define CFG_71_CHANGE_APID_B 0x4000 1616 REG16 CFG_72; 1617 #define CFG_72_MERGE_FIFO_STATUS 0x1fff 1618 REG16 CFG_73; 1619 #define CFG_73_PVR_STATUS_PVR3_FIFO_MASK 0x000f 1620 #define CFG_73_PVR_STATUS_PVR3_FIFO_SHIFT 0 1621 #define CFG_73_PVR_STATUS_PVR3_EVER_OVERFLOW_MASK 0x0001 1622 #define CFG_73_PVR_STATUS_PVR3_EVER_OVERFLOW_SHIFT 4 1623 #define CFG_73_PVR_STATUS_PVR3_STR2MI_INT_MASK 0x0006 1624 #define CFG_73_PVR_STATUS_PVR3_STR2MI_INT_SHIFT 5 1625 #define CFG_73_PVR_STATUS_PVR4_FIFO_MASK 0x000f 1626 #define CFG_73_PVR_STATUS_PVR4_FIFO_SHIFT 8 1627 #define CFG_73_PVR_STATUS_PVR4_EVER_OVERFLOW_MASK 0x0001 1628 #define CFG_73_PVR_STATUS_PVR4_EVER_OVERFLOW_SHIFT 12 1629 #define CFG_73_PVR_STATUS_PVR4_STR2MI_INT_MASK 0x0006 1630 #define CFG_73_PVR_STATUS_PVR4_STR2MI_INT_SHIFT 13 1631 REG16 CFG_74; 1632 #define CFG_74_MATCHECED_APID_C_MASK 0x1fff 1633 #define CFG_74_CHANGE_APID_C 0x4000 1634 REG16 CFG_75; 1635 #define CFG_75_FI_MOBF_INDEC_TSIF1_MASK 0x0000001F 1636 REG16 CFG_76; 1637 #define CFG_76_FI_MOBF_INDEC_TSIF2_MASK 0x0000001F 1638 REG16 CFG_77; 1639 #define CFG_77_FI_MOBF_INDEC_TSIF3_MASK 0x0000001F 1640 REG16 CFG_78_7B[4]; 1641 #define CFG_78_PVR3_INDEX 0x0000001F 1642 REG16 CFG_7C; 1643 #define CFG_7C_MATCHECED_APID_D_MASK 0x1fff 1644 #define CFG_7C_CHANGE_APID_D 0x4000 1645 } REG_Ctrl2; 1646 1647 //TSP 4 1648 typedef struct _REG_Ctrl3 1649 { 1650 REG16 CFG3_00_09[10]; // 0x00 ~ 0x09 1651 REG16 CFG3_0A; // 0x0A 1652 #define CFG3_0A_REG_PDFLT_BF0_CAVID 0x001F 1653 #define CFG3_0A_REG_PDFLT_BF1_CAVID 0x03E0 1654 #define CFG3_0A_REG_PDFLT_BF2_CAVID 0x7C00 1655 REG16 CFG3_0B; // 0x0B 1656 REG16 CFG3_0C; // 0x0C 1657 #define CFG3_0C_RBF0_PASS_MODE 0x0001 1658 #define CFG3_0C_RBF1_PASS_MODE 0x0002 1659 #define CFG3_0C_RBF2_PASS_MODE 0x0004 1660 #define CFG3_0C_RBF3_PASS_MODE 0x0008 1661 1662 #define CFG3_0C_PKTDMX_CC_DROP_MSAK 0x03C0 1663 #define CFG3_0C_PKTDMX_CC_DROP_SHIFT 0x0006 1664 #define CFG3_0C_PIDFLT0_DUP_CC_SKIP 0x0040 1665 #define CFG3_0C_PIDFLT1_DUP_CC_SKIP 0x0080 1666 #define CFG3_0C_PIDFLT2_DUP_CC_SKIP 0x0100 1667 #define CFG3_0C_PIDFLT3_DUP_CC_SKIP 0x0200 1668 1669 REG16 CFG3_0D; // 0x0D 1670 #define CFG3_0D_PIDFLT0_ADP_DUP_CC_SKIP 0x0001 1671 #define CFG3_0D_PIDFLT1_ADP_DUP_CC_SKIP 0x0002 1672 #define CFG3_0D_PIDFLT2_ADP_DUP_CC_SKIP 0x0004 1673 #define CFG3_0D_PIDFLT3_ADP_DUP_CC_SKIP 0x0008 1674 REG16 CFG3_0E; // 0x0E 1675 #define CFG3_0E_PDFBUF_FULL_SEL 0x0007 1676 #define CFG3_0E_PKT_MERGE_TIMESTAMP_SRC_SEL 0x01F8 //reg_pkt_merge_timestamp_src_sel=> 1677 #define CFG3_0E_PIDBUF0_TIMESTAMP_27M 0x0008 //pdflt buffer 0 timestamp sel 1: 27m 0: 90k 1678 #define CFG3_0E_PIDBUF1_TIMESTAMP_27M 0x0010 //pdflt buffer 1 timestamp sel 1: 27m 0: 90k 1679 #define CFG3_0E_PIDBUF2_TIMESTAMP_27M 0x0020 //pdflt buffer 2 timestamp sel 1: 27m 0: 90k 1680 #define CFG3_0E_PIDBUF3_TIMESTAMP_27M 0x0040 //pdflt buffer 3 timestamp sel 1: 27m 0: 90k 1681 #define CFG3_0E_STREAM2MIU1_C27M 0x0200 //reg_stream2miu1_c90k_sel=>Stream2miu1 timestamp sel 1: 27m 0: 90k 1682 #define CFG3_0E_STREAM2MIU2_C27M 0x0400 //reg_stream2miu2_c90k_sel=>Stream2miu2 timestamp sel 1: 27m 0: 90k 1683 #define CFG3_0E_STREAM2MIU3_C27M 0x0800 //reg_stream2miu3_c90k_sel=>Stream2miu3 timestamp sel 1: 27m 0: 90k 1684 #define CFG3_0E_STREAM2MIU4_C27M 0x1000 //reg_stream2miu4_c90k_sel=>Stream2miu4 timestamp sel 1: 27m 0: 90k 1685 REG16 CFG3_0F; // 0x0F 1686 #define CFG3_0F_TSIF0_C27M 0x0001 //reg_tsif0_c90k_sel=>Tsif0 timestamp sel 1: 27m 0: 90k 1687 #define CFG3_0F_TSIF1_C27M 0x0002 //reg_tsif1_c90k_sel=>Tsif1 timestamp sel 1: 27m 0: 90k 1688 #define CFG3_0F_TSIF2_C27M 0x0004 //reg_tsif2_c90k_sel=>Tsif2 timestamp sel 1: 27m 0: 90k 1689 #define CFG3_0F_TSIF3_C27M 0x0008 //reg_tsif3_c90k_sel=>Tsif3 timestamp sel 1: 27m 0: 90k 1690 REG16 CFG3_10; // 0x10 1691 #define CFG3_10_TSO0_SRC 0x0007 //reg_tso0_src 1692 #define CFG3_10_TSO0_SRC_SHIFT 0 1693 #define CFG3_10_TSO0_SRC_PKTDMX0 0x0001 1694 #define CFG3_10_TSO0_SRC_PKTDMX1 0x0002 1695 #define CFG3_10_TSO0_SRC_PKTDMX2 0x0004 1696 #define CFG3_10_TSO1_SRC 0x0038 //reg_tso1_src 1697 #define CFG3_10_TSO1_SRC_SHIFT 3 1698 #define CFG3_10_TSO1_SRC_PKTDMX0 0x0001 1699 #define CFG3_10_TSO1_SRC_PKTDMX1 0x0002 1700 #define CFG3_10_TSO1_SRC_PKTDMX2 0x0004 1701 #define CFG3_10_TSO0_BLOCK_DIS 0x1000 //reg_tso0_block_dis 1702 #define CFG3_10_TSO1_BLOCK_DIS 0x2000 //reg_tso1_block_dis 1703 #define CFG3_10_PS_MODE_SRC_MASK 0x01C0 1704 #define CFG3_10_PS_MODE_SRC_SHIFT 6 1705 1706 REG16 CFG3_11; // 0x11 1707 REG32 CFG3_12_13; // reg_dmaw_lbnd4 1708 REG32 CFG3_14_15; //reg_dmaw_ubnd4 1709 REG16 CFG3_16; // 0x16 1710 #define CFG3_16_FIXED_DMA_RSTART_OTP_ONEWAY_LOAD_FW 0x8000 1711 REG16 CFG3_17; // 0x17 1712 #define CFG3_17_INIT_TIMESTAMP_TSIF_0 0x0040 1713 #define CFG3_17_INIT_TIMESTAMP_TSIF_1 0x0080 1714 #define CFG3_17_INIT_TIMESTAMP_TSIF_2 0x0100 1715 #define CFG3_17_INIT_TIMESTAMP_TSIF_3 0x0200 1716 REG16 CFG3_18_1D[6]; // 0x18 ~ 0x1D 1717 REG16 CFG3_1E; // 0X1E 1718 #define CFG3_1E_TSIF0_SPD_RESET 0x0001 //Tsif0 SPD rest 1719 #define CFG3_1E_TSIF1_SPD_RESET 0x0002 //Tsif1 SPD rest 1720 #define CFG3_1E_TSIF2_SPD_RESET 0x0004 //Tsif2 SPD rest 1721 #define CFG3_1E_TSIF3_SPD_RESET 0x0008 //Tsif3 SPD rest 1722 REG16 CFG3_1F; // 0x1F 1723 REG16 CFG3_20; // 0x20 1724 #define CFG3_20_PIDFLT0_CLR_REPLACE_EN_MASK 0x000F //reg_pdflt0_clear_replace_en=>clear pdflt 0 cc replace function flag 1725 #define CFG3_20_PIDFLT1_CLR_REPLACE_EN_MASK 0x00F0 //reg_pdflt1_clear_replace_en=>clear pdflt 0 cc replace function flag 1726 #define CFG3_20_PIDFLT2_CLR_REPLACE_EN_MASK 0x0F00 //reg_pdflt2_clear_replace_en=>clear pdflt 0 cc replace function flag 1727 #define CFG3_20_PIDFLT3_CLR_REPLACE_EN_MASK 0xF000 //reg_pdflt3_clear_replace_en=>clear pdflt 0 cc replace function flag 1728 REG16 CFG3_21; // 0x21 1729 #define CFG3_21_TSIF0_FILE_PAUSE 0x0100 // Set 1 to inform TSIF(file-in engine) back-end pipe is full 1730 #define CFG3_21_TSIF1_FILE_PAUSE 0x0200 // and don't transmit data 1731 #define CFG3_21_TSIF2_FILE_PAUSE 0x0400 1732 #define CFG3_21_TSIF3_FILE_PAUSE 0x0800 1733 REG16 CFG3_22; 1734 #define CFG3_22_PVR1_PKT_MEET_SIZE_L_MASK 0xFFFF //PVR1 callback PKT Meet Size 1735 REG16 CFG3_23; 1736 #define CFG3_23_PVR1_PKT_MEET_SIZE_H_MASK 0x00FF 1737 #define CFG3_23_PVR1_STR2MI_CNT_CLR 0x0100 1738 #define CFG3_23_PVR1_STR2MI_CNT_INTMODE 0x0200 1739 #define CFG3_23_PVR1_STR2MI_SYNC_INTMODE 0x0400 1740 REG16 CFG3_24; 1741 #define CFG3_24_PVR2_PKT_MEET_SIZE_L_MASK 0xFFFF //PVR2 callback PKT Meet Size 1742 REG16 CFG3_25; 1743 #define CFG3_25_PVR2_PKT_MEET_SIZE_H_MASK 0x00FF 1744 #define CFG3_25_PVR2_STR2MI_CNT_CLR 0x0100 1745 #define CFG3_25_PVR2_STR2MI_CNT_INTMODE 0x0200 1746 #define CFG3_25_PVR2_STR2MI_SYNC_INTMODE 0x0400 1747 REG16 CFG3_26; 1748 #define CFG3_26_PVR3_PKT_MEET_SIZE_L_MASK 0xFFFF //PVR3 callback PKT Meet Size 1749 REG16 CFG3_27; 1750 #define CFG3_27_PVR3_PKT_MEET_SIZE_H_MASK 0x00FF 1751 #define CFG3_27_PVR3_STR2MI_CNT_CLR 0x0100 1752 #define CFG3_27_PVR3_STR2MI_CNT_INTMODE 0x0200 1753 #define CFG3_27_PVR3_STR2MI_SYNC_INTMODE 0x0400 1754 REG16 CFG3_28_29[2]; // 0x28 ~ 0x29 1755 REG16 CFG3_2A; 1756 #define CFG3_2A_PKTDMX0_TRACE_MARK_V_EN 0x0001 1757 #define CFG3_2A_PKTDMX0_TRACE_MARK_V3D_EN 0x0002 1758 #define CFG3_2A_PKTDMX0_TRACE_MARK_A_EN 0x0004 1759 #define CFG3_2A_PKTDMX0_TRACE_MARK_AB_EN 0x0008 1760 #define CFG3_2A_PKTDMX1_TRACE_MARK_V_EN 0x0020 1761 #define CFG3_2A_PKTDMX1_TRACE_MARK_V3D_EN 0x0040 1762 #define CFG3_2A_PKTDMX1_TRACE_MARK_A_EN 0x0080 1763 #define CFG3_2A_PKTDMX1_TRACE_MARK_AB_EN 0x0100 1764 #define CFG3_2A_PKTDMX2_TRACE_MARK_V_EN 0x0400 1765 #define CFG3_2A_PKTDMX2_TRACE_MARK_V3D_EN 0x0800 1766 #define CFG3_2A_PKTDMX2_TRACE_MARK_A_EN 0x1000 1767 #define CFG3_2A_PKTDMX2_TRACE_MARK_AB_EN 0x2000 1768 REG16 CFG3_2B; 1769 #define CFG3_2B_PKTDMX3_TRACE_MARK_V_EN 0x0001 1770 #define CFG3_2B_PKTDMX3_TRACE_MARK_V3D_EN 0x0002 1771 #define CFG3_2B_PKTDMX3_TRACE_MARK_A_EN 0x0004 1772 #define CFG3_2B_PKTDMX3_TRACE_MARK_AB_EN 0x0008 1773 #define CFG3_2B_PKTDMX4_TRACE_MARK_V_EN 0x0020 1774 #define CFG3_2B_PKTDMX4_TRACE_MARK_V3D_EN 0x0040 1775 #define CFG3_2B_PKTDMX4_TRACE_MARK_A_EN 0x0080 1776 #define CFG3_2B_PKTDMX4_TRACE_MARK_AB_EN 0x0100 1777 REG16 CFG3_2C; 1778 #define CFG3_2C_PDFLT0_NDS_TEST_MODE 0x0001 1779 #define CFG3_2C_PDFLT1_NDS_TEST_MODE 0x0002 1780 #define CFG3_2C_PDFLT2_NDS_TEST_MODE 0x0004 1781 #define CFG3_2C_PDFLT3_NDS_TEST_MODE 0x0008 1782 #define CFG3_2C_AVFIFO_READ_SEL_MASK 0x01C0 1783 #define CFG3_2C_AVFIFO_READ_SEL_SHIFT 6 1784 #define CFG3_2C_AVFIFO_READ_SEL_V 0 1785 #define CFG3_2C_AVFIFO_READ_SEL_A 1 1786 #define CFG3_2C_AVFIFO_READ_SEL_AB 2 1787 #define CFG3_2C_AVFIFO_READ_SEL_V3D 3 1788 #define CFG3_2C_AVFIFO_READ_SEL_AC 4 1789 #define CFG3_2C_AVFIFO_READ_SEL_AD 5 1790 #define CFG3_2C_DEBUG_WR_SRC_SEL_MASK 0x0E00 1791 REG16 CFG3_2D; 1792 #define CFG3_2D_FIXED_RM_PINPONG_SYCN_IN_ECO 0x0001 // fixed_rm_pinpong_sycn_in_eco 1793 #define CFG3_2D_VPID_3D_BYPASS 0x0002 // reg_vpid_3d_bypass 1794 #define CFG3_2D_APID_B_BYPASS 0x0004 // reg_apid_b_bypass 1795 #define CFG3_2D_APID_C_BYPASS 0x0008 // reg_apid_b_bypass 1796 #define CFG3_2D_APID_D_BYPASS 0x0010 // reg_apid_b_bypass 1797 #define CFG3_2D_PKT_DEMUX0_TRACE_MARK_AD 0x0020 // reg_pkt_demux0_trace_mark_ad_en=>set 1 enable trace mark function in pktdemux0 audio d path 1798 #define CFG3_2D_PKT_DEMUX1_TRACE_MARK_AD 0x0040 // reg_pkt_demux1_trace_mark_ad_en=>set 1 enable trace mark function in pktdemux0 audio d path 1799 #define CFG3_2D_PKT_DEMUX2_TRACE_MARK_AD 0x0080 // reg_pkt_demux2_trace_mark_ad_en=>set 1 enable trace mark function in pktdemux0 audio d path 1800 #define CFG3_2D_PKT_DEMUX3_TRACE_MARK_AD 0x0100 // reg_pkt_demux3_trace_mark_ad_en=>set 1 enable trace mark function in pktdemux0 audio d path 1801 #define CFG3_2D_FILTER_NULL_PKT 0x0800 1802 REG16 CFG3_2E_30[3]; //reserved 1803 REG16 CFG3_31; // 0x31 1804 #define CFG3_31_PVR1_MEET_SIZE_CNT_R_MASK 0x00FF 1805 #define CFG3_31_PVR2_MEET_SIZE_CNT_R_MASK 0xFF00 1806 REG16 CFG3_32; // 0x32 1807 #define CFG3_31_PVR3_MEET_SIZE_CNT_R_MASK 0x00FF 1808 REG16 CFG3_33; 1809 #define TSP_AFIFOC_EMPTY 0x0002 1810 #define TSP_AFIFOC_EMPTY_SHFT 1 1811 #define TSP_AFIFOC_FULL 0x0004 1812 #define TSP_AFIFOC_FULL_SHFT 2 1813 #define TSP_AFIFOC_LEVEL 0x0018 1814 #define TSP_AFIFOC_LEVEL_SHFT 3 1815 #define TSP_AFIFOD_EMPTY 0x1000 1816 #define TSP_AFIFOD_EMPTY_SHFT 12 1817 #define TSP_AFIFOD_FULL 0x4000 1818 #define TSP_AFIFOD_FULL_SHFT 13 1819 #define TSP_AFIFOD_LEVEL 0xC000 1820 #define TSP_AFIFOD_LEVEL_SHFT 14 1821 REG16 CFG3_34; // 0x34 1822 #define CFG3_34_DUP_PKT_SKIP_V 0x0001 //reg_dup_pkt_skip_v 1823 #define CFG3_34_DUP_PKT_SKIP_V3D 0x0002 //reg_dup_pkt_skip_v3d 1824 #define CFG3_34_DUP_PKT_SKIP_A 0x0004 //reg_dup_pkt_skip_a 1825 #define CFG3_34_DUP_PKT_SKIP_AB 0x0008 //reg_dup_pkt_skip_ab 1826 #define CFG3_34_DUP_PKT_SKIP_AC 0x0010 //reg_dup_pkt_skip_ac 1827 #define CFG3_34_DUP_PKT_SKIP_AD 0x0020 //reg_dup_pkt_skip_ad 1828 #define CFG3_34_MASK_SRC_V_EN 0x0100 //mask_scr_vid_en 1829 #define CFG3_34_MASK_SRC_V3D_EN 0x0200 //mask_scr_v3d_en 1830 #define CFG3_34_MASK_SRC_A_EN 0x0400 //mask_scr_aud_en 1831 #define CFG3_34_MASK_SRC_AB_EN 0x0800 //mask_scr_aud_b_en 1832 #define CFG3_34_MASK_SRC_AC_EN 0x1000 //mask_scr_aud_c_en 1833 #define CFG3_34_MASK_SRC_AD_EN 0x2000 //mask_scr_aud_d_en 1834 #define CFG3_34_FIX_192_TIMER_0_EN 0x4000 //reg_fix_192_timer_0_en 1835 #define CFG3_34_TSP2MI_REQ_MCM_DISABLE 0x8000 //reg_tsp2mi_req_mcm_disable 1836 REG16 CFG3_35; // 0x35 1837 #define HW4_CFG35_BLK_AD_SCMBTIS_TSP 0x0001 1838 #define HW4_CFG35_PUSI_3BYTE_MODE 0x0002 1839 #define HW4_CFG35_PKT_MERGE_AUTO_RST 0x0004 1840 #define HW4_CFG35_AES_OUT_BT_ORDER 0x0008 1841 #define HW4_CFG35_AES_IN_BT_ORDER 0x0010 1842 #define HW4_CFG35_PREVENT_PID_TABLE_SRAM_COLLISION 0x0020 1843 #define HW4_CFG35_RW_CONDITION_0 0x0040 1844 #define HW4_CFG35_RW_CONDITION_1 0x0080 1845 #define HW4_CFG35_PUSI_UPDATE_SCMB_BIT 0x0100 1846 #define HW4_CFG35_BYPASS_TIMESTAMP_SEL1 0x0200 1847 #define HW4_CFG35_BYPASS_TIMESTAMP_SEL2 0x0400 1848 #define HW4_CFG35_BYPASS_TIMESTAMP_SEL3 0x0800 1849 #define HW4_CFG35_BYPASS_TIMESTAMP_SEL4 0x1000 1850 #define HW4_CFG35_CLR_SRAM_COLLISION 0x2000 1851 #define HW4_CFG35_PREVENT_SRAM_COLLISION 0x4000 1852 #define HW4_CFG35_BYPASS_FILEIN_TO_FIQ 0x8000 1853 REG16 CFG3_36; 1854 #define HW4_CFG36_PKT130_PSI_EN0 0x0001 //rvu setting 1855 #define HW4_CFG36_PKT130_TEI_EN0 0x0002 1856 #define HW4_CFG36_PKT130_ERR_CLR0 0x0004 1857 #define HW4_CFG36_PKT130_EN0 0x0008 1858 #define HW4_CFG36_PKT130_TIMESTAMP_EN0 0x0010 1859 #define HW4_CFG36_PKT130_PID_12_TIE_0_EN0 0x0020 1860 #define HW4_CFG36_PAYLOAD_128_MODE_EN0 0x0040 1861 #define HW4_CFG36_PKT130_PSI_EN1 0x0100 1862 #define HW4_CFG36_PKT130_TEI_EN1 0x0200 1863 #define HW4_CFG36_PKT130_ERR_CLR1 0x0400 1864 #define HW4_CFG36_PKT130_EN1 0x0800 1865 #define HW4_CFG36_PKT130_TIMESTAMP_EN1 0x1000 1866 #define HW4_CFG36_PKT130_PID_12_TIE_0_EN1 0x2000 1867 #define HW4_CFG36_PAYLOAD_128_MODE_EN1 0x4000 1868 REG16 CFG3_37; 1869 #define HW4_CFG37_3WIRE_SERIAL_MODE_TS0 0x0001 1870 #define HW4_CFG37_3WIRE_SERIAL_MODE_TS1 0x0002 1871 #define HW4_CFG37_3WIRE_SERIAL_MODE_TS2 0x0004 1872 #define HW4_CFG37_3WIRE_SERIAL_MODE_TS3 0x0008 1873 #define HW4_CFG37_NON_188_CNT_MODE 0x0100 1874 #define HW4_CFG37_MASK_SCR_PVR1_EN 0x0200 1875 #define HW4_CFG37_MASK_SCR_PVR2_EN 0x0400 1876 #define HW4_CFG37_MASK_SCR_PVR3_EN 0x0800 1877 #define HW4_CFG37_MASK_SCR_PVR4_EN 0x1000 1878 #define HW4_CFG37_RST_CC_MODE 0x2000 1879 #define HW4_CFG37_DIS_CNTR_INC_BY_PL 0x4000 // 1=without payload 0=with payload ??? 1880 REG16 CFG3_38; 1881 #define HW4_CFG38_LOAD_SPS_KEY1 0x0001 1882 #define HW4_CFG38_LOAD_SPS_KEY2 0x0002 1883 #define HW4_CFG38_LOAD_SPS_KEY3 0x0004 1884 #define HW4_CFG38_LOAD_SPS_KEY4 0x0008 1885 #define HW4_CFG38_PKT192_SPS_EN1 0x0010 1886 #define HW4_CFG38_PKT192_SPS_EN2 0x0020 1887 #define HW4_CFG38_PKT192_SPS_EN3 0x0040 1888 #define HW4_CFG38_PKT192_SPS_EN4 0x0080 1889 #define HW4_CFG38_CA_PVR1_SEL_MASK 0x0300 1890 #define HW4_CFG38_CA_PVR1_SEL_SHIFT 8 1891 #define HW4_CFG38_CA_PVR2_SEL_MASK 0x0C00 1892 #define HW4_CFG38_CA_PVR2_SEL_SHIFT 10 1893 #define HW4_CFG38_CA_PVR3_SEL_MASK 0x3000 1894 #define HW4_CFG38_CA_PVR3_SEL_SHIFT 12 1895 #define HW4_CFG38_CA_PVR4_SEL_MASK 0xC000 1896 #define HW4_CFG38_CA_PVR4_SEL_SHIFT 14 1897 REG16 CFG3_39; 1898 #define HW4_CFG39_FLUSH_PVR_DATA 0x0001 1899 #define HW4_CFG39_FLUSH_PVR1_DATA 0x0002 1900 #define HW4_CFG39_FLUSH_PVR2_DATA 0x0004 1901 #define HW4_CFG39_FLUSH_PVR3_DATA 0x0008 1902 REG16 CFG3_3A; 1903 #define HW4_CFG3A_LOAD_SPD_KEY0 0x0001 1904 #define HW4_CFG3A_LOAD_SPD_KEY1 0x0002 1905 #define HW4_CFG3A_LOAD_SPD_KEY2 0x0004 1906 #define HW4_CFG3A_LOAD_SPD_KEY3 0x0008 1907 #define HW4_CFG3A_LOAD_SPD_KEY4 0x0010 1908 #define HW4_CFG3A_LOAD_SPD_KEY5 0x0020 1909 REG16 CFG3_3B_3F[5]; 1910 REG16 CFG3_40; 1911 #define HW4_CFG40_HW_SEMAPHORE0_MASK 0xFFFF 1912 REG16 CFG3_41; 1913 #define HW4_CFG41_HW_SEMAPHORE1_MASK 0xFFFF 1914 REG16 CFG3_42; 1915 #define HW4_CFG42_HW_SEMAPHORE2_MASK 0xFFFF 1916 REG16 CFG3_43; 1917 #define HW4_CFG43_SRC_AES_PVR_KEY_MASK 0x0007 1918 #define HW4_CFG43_SRC_AES_PVR1_KEY 0x0000 1919 #define HW4_CFG43_SRC_AES_PVR2_KEY 0x0001 1920 #define HW4_CFG43_SRC_AES_PVR3_KEY 0x0002 1921 #define HW4_CFG43_SRC_AES_PVR4_KEY 0x0003 1922 #define HW4_CFG43_SRC_AES_FI_KEY_MASK 0x0038 1923 #define HW4_CFG43_SRC_AES_FI_KEY_SHIFT 3 1924 #define HW4_CFG43_SRC_AES_FI0_KEY 0x0000 1925 #define HW4_CFG43_SRC_AES_FI1_KEY 0x0001 1926 #define HW4_CFG43_SRC_AES_FI2_KEY 0x0002 1927 #define HW4_CFG43_SRC_AES_FI3_KEY 0x0003 1928 REG32 CFG3_44_45; //pause time0 for PVR1+ FIQ application 1929 REG32 CFG3_46_47; //pause time1 for PVR2+ FIQ application 1930 REG32 CFG3_48_49; //pause time2 for PVR3+ FIQ application 1931 REG32 CFG3_4A_4B; //pause time3 for PVR4+ FIQ application 1932 REG16 CFG3_4C_4F[4]; 1933 REG32 CFG3_50_51; 1934 REG16 CFG3_52; 1935 #define CFG3_52_SPD_TSIF0_BYPASS 0x0001 1936 #define CFG3_52_SPD_TSIF1_BYPASS 0x0002 1937 #define CFG3_52_SPD_TSIF2_BYPASS 0x0004 1938 #define CFG3_52_SPD_TSIF3_BYPASS 0x0008 1939 REG16 CFG3_53; 1940 #define CFG3_53_WB_FSM_RESET 0x0001 1941 REG16 CFG3_54_57[4]; 1942 REG16 CFG3_58_5F[8]; 1943 REG16 CFG3_60_67[8]; //AES KEY PVR 1944 REG16 CFG3_68_6F[8]; //AES KEY FILEIN 1945 REG16 CFG3_70_71[2]; //BIST fail status 1946 REG16 CFG3_72; 1947 #define CFG3_72_PIDFLT_PCR_SCR_ID_MASK 0x00ff 1948 #define CFG3_72_PIDFLT_PCR0_SCR_ID_SHIFT 0 1949 #define CFG3_72_PIDFLT_PCR1_SCR_ID_SHIFT 8 1950 REG16 CFG3_73; 1951 #define CFG3_73_PVR1_DMAW_PROTECT_EN 0x0001 1952 #define CFG3_73_PVR2_DMAW_PROTECT_EN 0x0002 1953 #define CFG3_73_PVR3_DMAW_PROTECT_EN 0x0004 1954 #define CFG3_73_PVR4_DMAW_PROTECT_EN 0x0008 1955 #define CFG3_73_FILEIN0_DMAR_PROTECT_EN 0x0010 1956 #define CFG3_73_FILEIN1_DMAR_PROTECT_EN 0x0020 1957 #define CFG3_73_FILEIN2_DMAR_PROTECT_EN 0x0040 1958 #define CFG3_73_FILEIN3_DMAR_PROTECT_EN 0x0080 1959 #define CFG3_73_MMFI0_DMAR_PROTECT_EN 0x0400 1960 #define CFG3_73_MMFI1_DMAR_PROTECT_EN 0x0800 1961 #define CFG3_73_FILEIN0_ILLEGAL_ADDR_0 0x1000 1962 #define CFG3_73_FILEIN1_ILLEGAL_ADDR_0 0x2000 1963 #define CFG3_73_FILEIN2_ILLEGAL_ADDR_0 0x4000 1964 #define CFG3_73_FILEIN3_ILLEGAL_ADDR_0 0x8000 1965 REG16 CFG3_74; 1966 #define CFG3_74_MMFI0_ILLEGAL_ADDR_0 0x0004 1967 #define CFG3_74_MMFI1_ILLEGAL_ADDR_0 0x0008 1968 #define CFG3_74_FILEIN0_ILLEGAL_MIU_NS_EN 0x0010 1969 #define CFG3_74_FILEIN1_ILLEGAL_MIU_NS_EN 0x0020 1970 #define CFG3_74_FILEIN2_ILLEGAL_MIU_NS_EN 0x0040 1971 #define CFG3_74_FILEIN3_ILLEGAL_MIU_NS_EN 0x0080 1972 #define CFG3_74_MMFI0_ILLEGAL_MIU_NS_EN 0x0400 1973 #define CFG3_74_MMFI1_ILLEGAL_MIU_NS_EN 0x0800 1974 #define CFG3_74_DIS_FILEIN0_ADDR_LEN_BY_TEE 0x1000 1975 #define CFG3_74_DIS_FILEIN1_ADDR_LEN_BY_TEE 0x2000 1976 #define CFG3_74_DIS_FILEIN2_ADDR_LEN_BY_TEE 0x4000 1977 #define CFG3_74_DIS_FILEIN3_ADDR_LEN_BY_TEE 0x8000 1978 REG16 CFG3_75; 1979 #define CFG3_75_DIS_MMFI0_ADDR_LEN_BY_TEE 0x0004 1980 #define CFG3_75_DIS_MMFI1_ADDR_LEN_BY_TEE 0x0008 1981 } REG_Ctrl3; 1982 1983 //@TODO There is FIQ Bank in TSP6 bank 1984 //TSP 6 1985 typedef struct _REG_Ctrl4 1986 { 1987 REG16 CFG4_00_53[84]; 1988 REG16 CFG4_54; 1989 #define CFG4_54_RVU_PSI_EN2 0x0001 1990 #define CFG4_54_RVU_TEI_EN2 0x0002 1991 #define CFG4_54_RVU_ERR_CLR2 0x0004 1992 #define CFG4_54_RVU_EN2 0x0008 1993 #define CFG4_54_RVU_TIMESTAMP_EN2 0x0010 1994 #define CFG4_54_RVU_PID_12_TIE_0_EN2 0x0020 1995 #define CFG4_54_PAYLOAD_128_MODE_EN2 0x0040 1996 1997 #define CFG4_54_RVU_PSI_EN3 0x0100 1998 #define CFG4_54_RVU_TEI_EN3 0x0200 1999 #define CFG4_54_RVU_ERR_CLR3 0x0400 2000 #define CFG4_54_RVU_EN3 0x0800 2001 #define CFG4_54_RVU_TIMESTAMP_EN3 0x1000 2002 #define CFG4_54_RVU_PID_12_TIE_0_EN3 0x2000 2003 #define CFG4_54_PAYLOAD_128_MODE_EN3 0x4000 2004 REG16 CFG4_55; 2005 #define CFG4_55_RVU_PSI_EN4 0x0001 2006 #define CFG4_55_RVU_TEI_EN4 0x0002 2007 #define CFG4_55_RVU_ERR_CLR4 0x0004 2008 #define CFG4_55_RVU_EN4 0x0008 2009 #define CFG4_55_RVU_TIMESTAMP_EN4 0x0010 2010 #define CFG4_55_RVU_PID_12_TIE_0_EN4 0x0020 2011 #define CFG4_55_PAYLOAD_128_MODE_EN4 0x0040 2012 }REG_Ctrl4; 2013 2014 //TSP 7 2015 typedef struct _REG_Ctrl5 2016 { 2017 REG16 CFG5_00; 2018 REG16 CFG5_01; 2019 REG16 CFG5_02; 2020 REG16 CFG5_03; 2021 REG16 CFG5_04; 2022 REG16 Drop_Dis_PKT_Cnt_0; 2023 REG16 Drop_Dis_PKT_Cnt_1; 2024 REG16 Drop_Dis_PKT_Cnt_2; 2025 REG16 Drop_Dis_PKT_Cnt_3; 2026 REG16 CFG5_09; 2027 REG16 CFG5_0A; 2028 REG16 CFG5_0B; 2029 REG16 CFG5_0C; 2030 REG16 Locked_PKT_Cnt; //0x0D : reg_locked_pkt_cnt 2031 REG16 Av_PKT_Cnt; //0x0E : aud_pkt /vid_pkt 2032 REG16 CFG5_0F_16[8]; 2033 REG16 Av_PKT_Cnt1; //0x17 : aud_b_pkt /vid_3d_pkt 2034 REG16 CFG5_18; 2035 REG16 Err_PKT_Cnt; //0x19 : reg_err_pkt_cnt 2036 REG16 CFG5_1A_1C[3]; 2037 REG16 Input_PKT_Cnt; //0x1D : reg_input_pkt_cnt 2038 REG16 CFG5_1E_6F[82]; 2039 REG16 CFG5_70; 2040 #define CFG5_70_ERR_PKT_SRC_SEL_SHIFT 0 2041 #define CFG5_70_ERR_PKT_SRC_SEL_MASK 0x0007 2042 #define CFG5_70_INPUT_PKT_SRC_SEL_SHIT 3 2043 #define CFG5_70_INPUT_PKT_SRC_SEL_MASK 0x0038 2044 REG16 CFG5_71; 2045 #define CFG5_71_ERR_PKT_CNT_0_LOAD 0x0001 2046 #define CFG5_71_ERR_PKT_CNT_1_LOAD 0x0002 2047 #define CFG5_71_ERR_PKT_CNT_2_LOAD 0x0004 2048 #define CFG5_71_ERR_PKT_CNT_3_LOAD 0x0008 2049 #define CFG5_71_INPUT_PKT_CNT_0_LOAD 0x0100 2050 #define CFG5_71_INPUT_PKT_CNT_1_LOAD 0x0200 2051 #define CFG5_71_INPUT_PKT_CNT_2_LOAD 0x0400 2052 #define CFG5_71_INPUT_PKT_CNT_3_LOAD 0x0800 2053 REG16 CFG5_72; 2054 #define CFG5_72_ERR_PKT_CNT_0_CLR 0x0001 2055 #define CFG5_72_ERR_PKT_CNT_1_CLR 0x0002 2056 #define CFG5_72_ERR_PKT_CNT_2_CLR 0x0004 2057 #define CFG5_72_ERR_PKT_CNT_3_CLR 0x0008 2058 #define CFG5_72_INPUT_PKT_CNT_0_CLR 0x0100 2059 #define CFG5_72_INPUT_PKT_CNT_1_CLR 0x0200 2060 #define CFG5_72_INPUT_PKT_CNT_2_CLR 0x0400 2061 #define CFG5_72_INPUT_PKT_CNT_3_CLR 0x0800 2062 REG16 CFG5_73; 2063 REG16 CFG5_74; 2064 REG16 CFG5_75; 2065 REG16 CFG5_76; 2066 REG16 CFG5_77; 2067 #define CFG5_77_PIDFLT_SRC_SEL2_SHIFT 0 //pkt dmx 2 2068 #define CFG5_77_PIDFLT_SRC_SEL2_MASK 0x0007 2069 #define CFG5_77_PIDFLT_SRC_SEL3_SHIFT 3 //pkt dmx 3 2070 #define CFG5_77_PIDFLT_SRC_SEL3_MASK 0x0038 2071 REG16 CFG5_78; 2072 #define CFG5_78_AUDC_SRC_MASK 0x0007 2073 #define CFG5_78_AUDC_SRC_SHIFT 0 2074 #define CFG5_78_AUDD_SRC_MASK 0x0038 2075 #define CFG5_78_AUDD_SRC_SHIFT 3 2076 2077 #define CFG5_78_PIDFLT_SRC_SEL_MMFI0_SHIFT 6 // MMFI0 2078 #define CFG5_78_PIDFLT_SRC_SEL_MMFI0_MASK 0x01C0 2079 #define CFG5_78_PIDFLT_SRC_SEL_MMFI1_SHIFT 9 // MMFI1 2080 #define CFG5_78_PIDFLT_SRC_SEL_MMFI1_MASK 0x0E00 2081 REG16 CFG5_79; 2082 REG16 CFG5_7A; 2083 #define CFG5_7A_LOCKED_PKT_CNT_0_LOAD 0x0001 2084 #define CFG5_7A_LOCKED_PKT_CNT_1_LOAD 0x0002 2085 #define CFG5_7A_LOCKED_PKT_CNT_2_LOAD 0x0004 2086 #define CFG5_7A_LOCKED_PKT_CNT_3_LOAD 0x0008 2087 #define CFG5_7A_A_PKT_CNT_LOAD 0x0100 2088 #define CFG5_7A_V_PKT_CNT_LOAD 0x0200 2089 #define CFG5_7A_AD_PKT_CNT_LOAD 0x0400 2090 #define CFG5_7A_V3D_PKT_CNT_LOAD 0x0800 2091 #define CFG5_7A_ADC_PKT_CNT_LOAD 0x1000 2092 #define CFG5_7A_ADD_PKT_CNT_LOAD 0x2000 2093 REG16 CFG5_7B; 2094 #define CFG5_7B_DROP_PKT_CNT_V_LOAD 0x0001 2095 #define CFG5_7B_DROP_PKT_CNT_V3D_LOAD 0x0002 2096 #define CFG5_7B_DROP_PKT_CNT_A_LOAD 0x0004 2097 #define CFG5_7B_DROP_PKT_CNT_AD_LOAD 0x0008 2098 #define CFG5_7B_DROP_PKT_CNT_ADC_LOAD 0x0010 2099 #define CFG5_7B_DROP_PKT_CNT_ADD_LOAD 0x0020 2100 #define CFG5_7B_DIS_PKT_CNT_V_LOAD 0x0100 2101 #define CFG5_7B_DIS_PKT_CNT_V3D_LOAD 0x0200 2102 #define CFG5_7B_DIS_PKT_CNT_A_LOAD 0x0400 2103 #define CFG5_7B_DIS_PKT_CNT_AD_LOAD 0x0800 2104 #define CFG5_7B_DIS_PKT_CNT_ADC_LOAD 0x1000 2105 #define CFG5_7B_DIS_PKT_CNT_ADD_LOAD 0x2000 2106 REG16 CFG5_7C; 2107 #define CFG5_7C_LOCKED_PKT_CNT_0_CLR 0x0001 2108 #define CFG5_7C_LOCKED_PKT_CNT_1_CLR 0x0002 2109 #define CFG5_7C_LOCKED_PKT_CNT_2_CLR 0x0004 2110 #define CFG5_7C_LOCKED_PKT_CNT_3_CLR 0x0008 2111 #define CFG5_7C_A_PKT_CNT_CLR 0x0100 2112 #define CFG5_7C_V_PKT_CNT_CLR 0x0200 2113 #define CFG5_7C_AD_PKT_CNT_CLR 0x0400 2114 #define CFG5_7C_V3D_PKT_CNT_CLR 0x0800 2115 #define CFG5_7C_ADC_PKT_CNT_CLR 0x1000 2116 #define CFG5_7C_ADD_PKT_CNT_CLR 0x2000 2117 REG16 CFG5_7D; 2118 #define CFG5_7D_DROP_PKT_CNT_V_CLR 0x0001 2119 #define CFG5_7D_DROP_PKT_CNT_V3D_CLR 0x0002 2120 #define CFG5_7D_DROP_PKT_CNT_A_CLR 0x0004 2121 #define CFG5_7D_DROP_PKT_CNT_AD_CLR 0x0008 2122 #define CFG5_7D_DROP_PKT_CNT_ADC_CLR 0x0010 2123 #define CFG5_7D_DROP_PKT_CNT_ADD_CLR 0x0020 2124 #define CFG5_7D_DIS_PKT_CNT_V_CLR 0x0100 2125 #define CFG5_7D_DIS_PKT_CNT_V3D_CLR 0x0200 2126 #define CFG5_7D_DIS_PKT_CNT_A_CLR 0x0400 2127 #define CFG5_7D_DIS_PKT_CNT_AD_CLR 0x0800 2128 #define CFG5_7D_DIS_PKT_CNT_ADC_CLR 0x1000 2129 #define CFG5_7D_DIS_PKT_CNT_ADD_CLR 0x2000 2130 REG16 CFG5_7E; 2131 #define CFG5_7E_AUDA_SRC_MASK 0x0007 2132 #define CFG5_7E_AUDA_SRC_SHIFT 0 2133 #define CFG5_7E_VID_SRC_MASK 0x0038 2134 #define CFG5_7E_VID_SRC_SHIFT 3 2135 #define CFG5_7E_AUDB_SRC_MASK 0x01C0 2136 #define CFG5_7E_AUDB_SRC_SHIFT 6 2137 #define CFG5_7E_VID_3D_SRC_MASK 0x1E00 2138 #define CFG5_7E_VID_3D_SRC_SHIFT 9 2139 #define AV_PKT_SRC_PKTDMX0 0x0000 2140 #define AV_PKT_SRC_PKTDMX1 0x0001 2141 #define AV_PKT_SRC_PKTDMX2 0x0002 2142 #define AV_PKT_SRC_PKTDMX3 0x0003 2143 #define AV_PKT_SRC_PKTDMX4 0x0004 2144 #define AV_PKT_SRC_PKTDMX5 0x0005 2145 #define AV_PKT_SRC_MMFI0 0x0006 2146 #define AV_PKT_SRC_MMFI1 0x0007 2147 2148 REG16 CFG5_7F; 2149 #define CFG5_7F_DROP_PKT_MODE 0x0002 //choose the source of the reg_pkt_cnt 0: dis_cont_pkt 1: drop_pkt_cnt 2150 #define CFG5_7F_PIDFLT_SRC_SEL_SHIFT 2 //pkt dmx 0 2151 #define CFG5_7F_PIDFLT_SRC_SEL_MASK 0x001C 2152 #define CFG5_7F_TSIF_SRC_SEL_SHIFT 5 2153 #define CFG5_7F_TSIF_SRC_SEL_MASK 0x00E0 2154 #define TSIF_SRC_SEL_TSIF0 0x000 2155 #define TSIF_SRC_SEL_TSIF1 0x001 2156 #define TSIF_SRC_SEL_TSIF2 0x002 2157 #define TSIF_SRC_SEL_TSIF3 0x003 2158 2159 #define CFG5_7F_AV_PKT_SRC_SEL 0x0100 //choose the source of the Av_PKT_Cnt 0 : vid_pkt_cnt/vid_3d_pkt_cnt 1 : aud_pkt_cnt/aud_b_pkt_cnt 2160 #define CFG5_7F_CLR_SRC_SHIFT 9 2161 #define CFG5_7F_CLR_SRC_MASK 0x0E00 2162 #define CFG5_7F_CLR_SRC_PKTDMX0 0x0000 2163 #define CFG5_7F_CLR_SRC_PKTDMX1 0x0001 2164 #define CFG5_7F_CLR_SRC_PKTDMX2 0x0002 2165 #define CFG5_7F_CLR_SRC_PKTDMX3 0x0003 2166 #define CFG5_7F_CLR_SRC_PKTDMX4 0x0004 2167 #define CFG5_7F_CLR_SRC_PKTDMX5 0x0005 2168 #define CFG5_7F_CLR_SRC_MMFI0 0x0006 2169 #define CFG5_7F_CLR_SRC_MMFI1 0x0007 2170 2171 #define CFG5_7F_PIDFLT_SRC_SEL1_SHIFT 13 //pkt dmx 1 2172 #define CFG5_7F_PIDFLT_SRC_SEL1_MASK 0xE000 2173 #define DIS_DROP_CNT_V 0 2174 #define DIS_DROP_CNT_V3D 1 2175 #define DIS_DROP_CNT_A 2 2176 #define DIS_DROP_CNT_AD 3 2177 #define DIS_DROP_CNT_ADC 4 2178 #define DIS_DROP_CNT_ADD 5 2179 2180 } REG_Ctrl5; 2181 2182 //TSP 8 2183 typedef struct _REG_Ctrl6 2184 { 2185 REG16 SyncByte_tsif0[4]; //0x00~0x03 2186 #define TSP_SYNC_BYTE_MAASK0 0x00FF //byte 0 2187 #define TSP_SYNC_BYTE_MAASK1 0xFF00 //byte 1 2188 #define TSP_SYNC_BYTE_SHIFT0 0 2189 #define TSP_SYNC_BYTE_SHIFT1 8 2190 REG16 SourceId_tsif0[2]; //0x04~0x05 2191 #define TSP_SRCID_MASK0 0x000F //soruce 0 2192 #define TSP_SRCID_MASK1 0x00F0 //soruce 1 2193 #define TSP_SRCID_MASK2 0x0F00 //soruce 2 2194 #define TSP_SRCID_MASK3 0xF000 //soruce 3 2195 #define TSP_SRCID_SHIFT0 0 2196 #define TSP_SRCID_SHIFT1 4 2197 #define TSP_SRCID_SHIFT2 8 2198 #define TSP_SRCID_SHIFT3 12 2199 REG16 SyncByte_tsif1[4]; //0x06~0x09 2200 REG16 SourceId_tsif1[2]; //0x0a~0x0b 2201 REG16 SyncByte_tsif2[4]; //0x0c~0x0f 2202 REG16 SourceId_tsif2[2]; //0x10~0x11 2203 REG16 SyncByte_tsif3[4]; //0x12~0x15 2204 REG16 SourceId_tsif3[2]; //0x16~0x17 2205 REG16 CFG6_18_23[12]; //0x18~0x23 2206 REG16 pkt_converter[4]; //0x24~0x27 2207 #define TSP_PKT_CONVERTER_MODE_MASK 0x0007 2208 #define TSP_PKT_188Mode 0 2209 #define TSP_PKT_CIMode 1 2210 #define TSP_PKT_OpenCableMode 2 2211 #define TSP_PKT_ATSMode 3 2212 #define TSP_PKT_MxLMode 4 2213 #define TSP_PKT_FORCE_SYNC_47 0x0008 2214 #define TSP_BYPASS_PKT_CONVERTER 0x0010 2215 #define TSP_BYPASS_SRC_ID_PARSER 0x0020 2216 #define TSP_SRC_ID_FLT_EN 0x0040 2217 #define TSP_MXL_PKT_HEADER_MASK 0x0F80 //add pkt num 2218 #define TSP_MXL_PKT_HEADER_SHIFT 7 2219 REG16 CFG6_28_29[2]; 2220 REG16 CFG6_2A; 2221 #define CLR_PKT_CONVERTER_OVERFLOW 0x0001 2222 #define TSP_TSIF0_TSO_BLK_EN 0x0002 2223 #define TSP_TSIF0_TS1_BLK_EN 0x0004 2224 #define TSP_TSIF0_TS2_BLK_EN 0x0008 2225 #define TSP_TSIF0_TS3_BLK_EN 0x0010 2226 #define FIXED_TIMESTAMP_RING_BACK_EN 0x0080 2227 #define FIXED_LPCR_RING_BACK_EN 0x0400 2228 #define FIXED_VQ_MIU_REG_FLUSH 0x2000 2229 REG16 CFG6_2B; 2230 #define TSP_RESET_WB_DMA_FSM_TSIF1 0x0001 2231 #define TSP_RESET_WB_DMA_FSM_TSIF2 0x0002 2232 #define TSP_RESET_WB_DMA_FSM_TSIF3 0x0004 2233 #define TSP_RESET_WB_DMA_FSM_TSIF4 0x0008 2234 #define TSP_FIX_FILTER_NULL_PKT 0x4000 2235 REG16 CFG6_2C_REG_MIU_SEL_FILEIN_MM; 2236 #define REG_MIU_SEL_FILEIN0_MASK 0x0003 2237 #define REG_MIU_SEL_FILEIN0_SHIFT 0 2238 #define REG_MIU_SEL_FILEIN1_MASK 0x000C 2239 #define REG_MIU_SEL_FILEIN1_SHIFT 2 2240 #define REG_MIU_SEL_FILEIN2_MASK 0x0030 2241 #define REG_MIU_SEL_FILEIN2_SHIFT 4 2242 #define REG_MIU_SEL_FILEIN3_MASK 0x00C0 2243 #define REG_MIU_SEL_FILEIN3_SHIFT 6 2244 #define REG_MIU_SEL_MMFI0_MASK 0x0300 2245 #define REG_MIU_SEL_MMFI0_SHIFT 8 2246 #define REG_MIU_SEL_MMFI1_MASK 0x0C00 2247 #define REG_MIU_SEL_MMFI1_SHIFT 10 2248 REG16 CFG6_2D_REG_MIU_SEL_FW; 2249 #define REG_MIU_SEL_VQ_MASK 0x0003 2250 #define REG_MIU_SEL_VQ_SHIFT 0 2251 #define REG_MIU_SEL_OR_ADDR_MASK 0x000C 2252 #define REG_MIU_SEL_OR_ADDR_SHIFT 2 2253 #define REG_MIU_SEL_SECTION_MASK 0x0030 2254 #define REG_MIU_SEL_SECTION_SHIFT 4 2255 #define REG_MIU_SEL_MERGE_EN_MASK 0xFF00 2256 REG16 CFG6_2E_REG_MIU_PVR_FQ; 2257 #define REG_MIU_SEL_PVR1_MASK 0x0003 2258 #define REG_MIU_SEL_PVR1_SHIFT 0 2259 #define REG_MIU_SEL_PVR2_MASK 0x000C 2260 #define REG_MIU_SEL_PVR2_SHIFT 2 2261 #define REG_MIU_SEL_PVR3_MASK 0x0030 2262 #define REG_MIU_SEL_PVR3_SHIFT 4 2263 #define REG_MIU_SEL_PVR4_MASK 0x00C0 2264 #define REG_MIU_SEL_PVR4_SHIFT 6 2265 #define REG_MIU_SEL_FIQ0_MASK 0x0300 2266 #define REG_MIU_SEL_FIQ0_SHIFT 8 2267 #define REG_MIU_SEL_FIQ1_MASK 0x0C00 2268 #define REG_MIU_SEL_FIQ1_SHIFT 10 2269 #define REG_MIU_SEL_FIQ2_MASK 0x3000 2270 #define REG_MIU_SEL_FIQ2_SHIFT 12 2271 #define REG_MIU_SEL_FIQ3_MASK 0xC000 2272 #define REG_MIU_SEL_FIQ3_SHIFT 14 2273 REG16 CFG6_2F; 2274 REG32 CFG6_30_31; // filein0 lower DMA read bound 2275 REG32 CFG6_32_33; // filein0 upper DMA read bound 2276 REG32 CFG6_34_35; // filein1 lower DMA read bound 2277 REG32 CFG6_36_37; // filein1 upper DMA read bound 2278 REG32 CFG6_38_39; // filein2 lower DMA read bound 2279 REG32 CFG6_3A_3B; // filein2 upper DMA read bound 2280 REG32 CFG6_3C_3D; // filein3 lower DMA read bound 2281 REG32 CFG6_3E_3F; // filein3 upper DMA read bound 2282 #define TSP_FILEIN_DMAR_BND_MASK 0x0FFFFFFFUL 2283 REG16 CFG6_40_47[8]; // @Not used 2284 REG32 CFG6_48_49; // mmfi0 lower DMA read bound 2285 REG32 CFG6_4A_4B; // mmfi0 upper DMA read bound 2286 REG32 CFG6_4C_4D; // mmfi1 lower DMA read bound 2287 REG32 CFG6_4E_4F; // mmfi1 upper DMA read bound 2288 #define TSP_MMFI_DMAR_BND_MASK 0x0FFFFFFFUL 2289 REG32 CFG6_50_51; // initial packet timestamp value (tsif0) 2290 REG32 CFG6_52_53; // initial packet timestamp value (tsif1) 2291 REG32 CFG6_54_55; // initial packet timestamp value (tsif2) 2292 REG32 CFG6_56_57; // initial packet timestamp value (tsif3) 2293 REG16 CFG6_58_5B[4]; // @Not used 2294 REG32 CFG6_5C_5D; // initial packet timestamp value (mmfi0) 2295 REG32 CFG6_5E_5F; // initial packet timestamp value (mmfi1) 2296 } REG_Ctrl6; 2297 2298 //TSP9 2299 typedef struct _REG_Ctrl7 2300 { 2301 REG16 CFG7_00_03[4]; //SPD CTR mode counter IV 2302 REG16 CFG7_04; //SPD CTR mode IV MAX (FILEIN) 2303 #define CFG7_04_CTR_IV_SPD_MAX_1K 0x0001 2304 #define CFG7_04_CTR_IV_SPD_MAX_2K 0x0002 2305 #define CFG7_04_CTR_IV_SPD_MAX_4K 0x0004 2306 #define CFG7_04_CTR_IV_SPD_MAX_8K 0x0008 2307 #define CFG7_04_CTR_IV_SPD_MAX_16K 0x0010 2308 #define CFG7_04_CTR_IV_SPD_MAX_32K 0x0020 2309 #define CFG7_04_CTR_IV_SPD_MAX_64K 0x0040 2310 #define CFG7_04_CTR_IV_SPD_MAX_128K 0x0080 2311 REG16 CFG7_05; //SPD CTR mode control (FILEIN) 2312 #define CFG7_05_CTR_MODE_SPD_FILEIN 0x0001 2313 #define CFG7_05_UPDATE_CTR_MODE_CNT_IV_SPD_FILEIN 0x0002 2314 #define CFG7_05_LOAD_INIT_CNT_SPD 0x0004 2315 #define CFG7_05_SPD_ONEWAY 0x8000 2316 REG16 CFG7_06_0F[10]; 2317 } REG_Ctrl7; 2318 2319 //TSP10 2320 typedef struct _REG_Ctrl8 2321 { 2322 REG16 CFG8_00_03[4]; //SPS CTR mode counter IV 2323 REG16 CFG8_04; //SPS CTR mode IV MAX (PVR 1) 2324 #define CFG8_04_CTR_IV_SPS_MAX_1K 0x0001 2325 #define CFG8_04_CTR_IV_SPS_MAX_2K 0x0002 2326 #define CFG8_04_CTR_IV_SPS_MAX_4K 0x0004 2327 #define CFG8_04_CTR_IV_SPS_MAX_8K 0x0008 2328 #define CFG8_04_CTR_IV_SPS_MAX_16K 0x0010 2329 #define CFG8_04_CTR_IV_SPS_MAX_32K 0x0020 2330 #define CFG8_04_CTR_IV_SPS_MAX_64K 0x0040 2331 #define CFG8_04_CTR_IV_SPS_MAX_128K 0x0080 2332 REG16 CFG8_05; //SPS CTR mode control (PVR 1) 2333 #define CFG8_05_CTR_MODE_SPS_PVR1 0x0001 2334 #define CFG8_05_UPDATE_CTR_MODE_CNT_IV_SPS_PVR1 0x0002 2335 #define CFG8_05_LOAD_INIT_CNT_SPS1 0x0004 2336 #define CFG8_05_SPS_ONEWAY1 0x8000 2337 REG16 CFG8_06_0F[10]; 2338 } REG_Ctrl8; 2339 2340 2341 #endif 2342