1 #ifndef _TSP2_REG_H_ 2 #define _TSP2_REG_H_ 3 typedef struct _REG32 4 { 5 volatile MS_U16 low; 6 volatile MS_U16 _null_l; 7 volatile MS_U16 high; 8 volatile MS_U16 _null_h; 9 } REG32; 10 11 typedef struct _REG16 12 { 13 volatile MS_U16 data; //[jerry] not to name "low" 14 volatile MS_U16 _null; 15 } REG16; 16 17 typedef struct _TSP32 18 { 19 volatile MS_U32 reg32; 20 } TSP32; 21 22 23 //######################################################################### 24 //#### Hardware Capability Macro Start 25 //######################################################################### 26 27 #define TSP_TSIF_NUM 4 28 #define TSP_PVRENG_NUM 4 29 #define TSP_PVR_IF_NUM 4 30 #define TSP_OTVENG_NUM 4 31 #define STC_ENG_NUM 2 32 #define TSP_PCRFLT_NUM STC_ENG_NUM 33 34 #define TSP_PIDFLT_NUM 192 35 #define TSP_SECFLT_NUM 192 36 #define TSP_SECBUF_NUM 192 37 38 #define TSP_MERGESTREAM_NUM 8 39 40 //@NOTE: accroding to width of FW/VQ/SEC buffer base addr , lower / upper bound may be different 41 #define TSP_FW_BUF_LOW_BUD 0 42 #define TSP_FW_BUF_UP_BUD ((1ULL << 32) - 1) // base addr: bits[31:4] , unit: 16-bytes (bits[3:0]) 43 // base addr = {reg_dma_raddr_msb(8-bits),reg_dma_raddr(16-bits),4'b0(4-bits)} 44 #define TSP_VQ_BUF_LOW_BUD 0 45 #define TSP_VQ_BUF_UP_BUD ((1ULL << 32) - 1) // base addr: bits[31:0] , unit: 1-byte 46 #define TSP_SEC_BUF_LOW_BUD 0 47 #define TSP_SEC_BUF_UP_BUD ((1ULL << 32) - 1) // base addr: bits[31:0] , unit: 1-byte 48 49 50 //@Note : Compatible for Kastor drvtsp2.c HWCL of PCR2,PCR3 51 #define TSP_HWINT3_PCR2_UPDATE_END_EN 0x0000 52 #define TSP_HWINT3_PCR3_UPDATE_END_EN 0x0000 53 #define TSP_HWINT3_PCR2_UPDATE_END 0x0000 54 #define TSP_HWINT3_PCR3_UPDATE_END 0x0000 55 #define TSP_HWINT3_ALL 0x0000 56 57 58 59 //######################################################################### 60 //#### Hardware Capability Macro End 61 //######################################################################### 62 63 64 // PID Filter 65 typedef TSP32 REG_PidFlt; // 0x210000 66 67 // TSIF 68 #define TSP_PIDFLT_TSIF_MASK 0x0000E000 69 #define TSP_PIDFLT_TSIF_SHFT 13 70 71 #define TSP_FILTER_DEPTH 16 72 73 // CLKGEN0 Bank:0x100B 74 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x1600 + ((addr)<<2)))) 75 #define REG_CLKGEN0_DC0_SYTNTH 0x05 76 #define REG_CLKGEN0_STC_CW_SEL 0x0002 77 #define REG_CLKGEN0_STC_CW_EN 0x0004 78 #define REG_CLKGEN0_STC1_CW_SEL 0x0200 79 #define REG_CLKGEN0_STC1_CW_EN 0x0400 80 #define REG_CLKGEN0_DC0_STC_CW_L 0x06 81 #define REG_CLKGEN0_DC0_STC_CW_H 0x07 82 #define REG_CLKGEN0_DC0_STC1_CW_L 0x08 83 #define REG_CLKGEN0_DC0_STC1_CW_H 0x09 84 85 #define REG_CLKGEN0_S2P_IN_CLK_SRC 0x0C 86 #define REG_CLKGEN0_S2P_IN_CLK_SHIFT 0 87 #define REG_CLKGEN0_S2P1_IN_CLK_SHIFT 8 88 89 #define REG_CLKGEN0_S2P_IN_CLK_MASK 0x1F 90 #define REG_CLKGEN0_S2P_IN_CLK_DISABLE 0x0001 91 #define REG_CLKGEN0_S2P_IN_CLK_INVERT 0x0002 92 #define REG_CLKGEN0_S2P_IN_CLK_SRC_SHIFT 2 93 #define REG_CLKGEN0_S2P_IN_CLK_SRC_MASK 0x7 94 95 #define REG_CLKGEN0_TSO0_CLK 0x27 96 #define REG_CLKGEN0_TSO0_SHIFT 0 97 #define REG_CLKGEN0_TS0_CLK 0x28 98 #define REG_CLKGEN0_TS0_SHIFT 0 99 #define REG_CLKGEN0_TS1_CLK 0x28 100 #define REG_CLKGEN0_TS1_SHIFT 8 101 #define REG_CLKGEN0_TS2_CLK 0x29 102 #define REG_CLKGEN0_TS2_SHIFT 0 103 #define REG_CLKGEN0_TS3_CLK 0x29 104 #define REG_CLKGEN0_TS3_SHIFT 8 105 #define REG_CLKGEN0_TS_MASK 0x003F // 4 bit each 106 #define REG_CLKGEN0_TS_DISABLE 0x0001 107 #define REG_CLKGEN0_TS_INVERT 0x0002 108 #define REG_CLKGEN0_TS_SRC_SHIFT 2 109 #define REG_CLKGEN0_TS_SRC_MASK 0x000F 110 #define REG_CLKGEN0_TS_SRC_EXT0 0x0000 111 #define REG_CLKGEN0_TS_SRC_EXT1 0x0001 112 #define REG_CLKGEN0_TS_SRC_EXT2 0x0002 113 #define REG_CLKGEN0_TS_SRC_EXT3 0x0003 114 #define REG_CLKGEN0_TS_SRC_EXT4 0x0004 115 #define REG_CLKGEN0_TS_SRC_EXT5 0x0005 116 #define REG_CLKGEN0_TS_SRC_EXT6 0x0006 117 #define REG_CLKGEN0_TS_SRC_TSO0 0x0007 118 //@NOTE Not support internal demod in KANO 119 #define REG_CLKGEN0_TS_SRC_DMD0 0x000F 120 121 //get TSP Clk Gen bank 122 #define REG_CLKGEN0_TSP_CLK 0x2A 123 #define REG_CLKGEN0_TSP_CLK_MASK 0x001F 124 #define REG_CLKGEN0_TSP_SHIFT 0 125 #define REG_CLKGEN0_TSP_DISABLE 0x0001 126 #define REG_CLKGEN0_TSP_INVERT 0x0002 127 //SRC 128 #define REG_CLKGEN0_TSP_SRC_SHIFT 2 129 #define REG_CLKGEN0_TSP_SRC_MASK 0x0007 130 #define REG_CLKGEN0_TSP_SRC_192MHZ 0x0000 131 #define REG_CLKGEN0_TSP_SRC_172MHZ 0x0001 132 #define REG_CLKGEN0_TSP_SRC_144MHZ 0x0002 133 #define REG_CLKGEN0_TSP_SRC_108MHZ 0x0003 134 #define REG_CLKGEN0_TSP_SRC_XTAL 0x0007 135 136 //get STC0/1 Clk Gen bank 137 #define REG_CLKGEN0_STC0_CLK 0x2A 138 #define REG_CLKGEN0_STC0_MASK 0x0F00 139 #define REG_CLKGEN0_STC0_SHIFT 8 140 #define REG_CLKGEN0_STC1_CLK 0x2A 141 #define REG_CLKGEN0_STC1_MASK 0xF000 142 #define REG_CLKGEN0_STC1_SHIFT 12 143 144 #define REG_CLKGEN0_STC_DISABLE 0x0001 145 #define REG_CLKGEN0_STC_INVERT 0x0002 146 //SRC 147 #define REG_CLKGEN0_STC_SRC_SHIFT 2 148 #define REG_CLKGEN0_STC_SRC_MASK 0x0003 149 #define REG_CLKGEN0_STC_SRC_SYNTH 0x0000 150 #define REG_CLKGEN0_STC_SRC_ONE 0x0001 151 #define REG_CLKGEN0_STC_SRC_27M 0x0002 152 #define REG_CLKGEN0_STC_SRC_XTAL 0x0003 153 154 #define REG_CLKGEN0_STAMP_CLK 0x2F 155 #define REG_CLKGEN0_STAMP_MASK 0x0F00 156 #define REG_CLKGEN0_STAMP_SHIFT 8 157 #define REG_CLKGEN0_STAMP_DISABLE 0x0001 158 #define REG_CLKGEN0_STAMP_INVERT 0x0002 159 160 #define REG_CLKGEN0_PARSER_CLK 0x39 161 #define REG_CLKGEN0_PARSER_MASK 0x0F00 162 #define REG_CLKGEN0_PARSER_SHIFT 8 163 #define REG_CLKGEN0_PARSER_DISABLE 0x0001 164 #define REG_CLKGEN0_PARSER_INVERT 0x0002 165 166 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x3c00UL + ((addr)<<2)))) 167 #define REG_TOP_TS0_MUX 0x38 168 #define REG_TOP_TS0_SHIFT 0x0 169 #define REG_TOP_TS1_MUX 0x38 170 #define REG_TOP_TS1_SHIFT 0x4 171 #define REG_TOP_TS2_MUX 0x38 172 #define REG_TOP_TS2_SHIFT 0x8 173 #define REG_TOP_TS3_MUX 0x38 174 #define REG_TOP_TS3_SHIFT 0xC 175 176 177 #define REG_TOP_TSO0_MUX 0x3A 178 #define REG_TOP_TSO0_SHIFT 0 179 180 #define REG_TOP_TS_SRC_MASK 0x000F 181 #define REG_TOP_TS_SRC_EXT0 0x0000 182 #define REG_TOP_TS_SRC_EXT1 0x0001 183 #define REG_TOP_TS_SRC_EXT2 0x0002 184 #define REG_TOP_TS_SRC_EXT3 0x0003 185 #define REG_TOP_TS_SRC_EXT4 0x0004 186 #define REG_TOP_TS_SRC_EXT5 0x0005 187 #define REG_TOP_TS_SRC_EXT6 0x0006 188 #define REG_TOP_TS_SRC_TSO0 0x0007 189 //@NOTE Not support internal demod in KANO 190 #define REG_TOP_TS_SRC_DMD0 0x0008 191 192 #define REG_TOP_TSO4_5_MUX 0x3B 193 #define REG_TOP_TSO4_SHIFT 0 194 #define REG_TOP_TSO4_MASK 0x0003 195 #define REG_TOP_TSO5_SHIFT 4 196 #define REG_TOP_TSO5_MASK 0x0003 197 198 #define REG_TOP_TS_PADMUX_MODE 0x02 199 #define REG_TOP_TS0MODE_MASK 0x1 200 #define REG_TOP_TS0MODE_SHIFT 0 201 #define REG_TOP_TS0MODE_PARALLEL 1 202 #define REG_TOP_TS1MODE_MASK 0x3 203 #define REG_TOP_TS1MODE_SHIFT 1 204 #define REG_TOP_TS1MODE_INPUT 1 205 #define REG_TOP_TS2MODE_MASK 0x3 206 #define REG_TOP_TS2MODE_SHIFT 3 207 #define REG_TOP_TS2MODE_PARALLEL 1 208 #define REG_TOP_TS2MODE_4WIRED 2 209 #define REG_TOP_TS2MODE_3WIRED 3 210 211 #define REG_TOP_TS_OUTPUT_MODE 0x07 212 #define REG_TOP_TS_OUT_MODE_MASK 0x3 213 #define REG_TOP_TS_OUT_MODE_SHIFT 14 214 #define REG_TOP_TS_OUT_MODE_TSO 1 215 #define REG_TOP_TS_OUT_MODE_S2P 2 216 #define REG_TOP_TS_OUT_MODE_S2P1 3 217 218 #define REG_TOP_TSP_BOOT_CLK_SEL 0x54 219 #define REG_TOP_TSP_BOOT_CLK_SEL_MASK 0x0100 220 #define REG_TOP_TSP_BOOT_CLK_SEL_TSP 0x0000 221 222 #define REG_TOP_TSP_3WIRE_MODE 0x11 223 #define REG_TOP_TSP_TS0_3WIRE_EN 0x01 224 #define REG_TOP_TSP_TS1_3WIRE_EN 0x02 225 226 #define REG_TOP_TSP_3WIRE_MODE1 0x7b 227 #define REG_TOP_TSP_TS2_3WIRE_EN 0x01 228 #define REG_TOP_TSP_TS3_3WIRE_EN 0x02 229 230 231 232 #define TSP_MMFI_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x27E00 + ((addr)<<2)))) 233 #define REG_MMFI_TSP_SEL_SRAM 0x70 234 #define REG_MMFI_TSP_SEL_SRAM_EN 0x0002 235 236 #define TSP_TSO_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0xE0C00 + ((addr)<<2)))) 237 #define REG_TSO_TSP_CONFIG0 0x1C 238 #define REG_TSO_TSP_S2P_MASK 0x001F 239 #define REG_TSO_TSP_S2P_EN 0x0001 240 #define REG_TSO_TSP_S2P_TS_SIN_C0 0x0002 241 #define REG_TSO_TSP_S2P_TS_SIN_C1 0x0004 242 #define REG_TSO_TSP_S2P_3WIRE 0x0008 243 #define REG_TSO_TSP_BYPASS_S2P 0x0010 244 245 #define REG_TSO_TSP_S2P1_MASK 0x1F00 246 #define REG_TSO_TSP_S2P1_EN 0x0100 247 #define REG_TSO_TSP_S2P1_TS_SIN_C0 0x0200 248 #define REG_TSO_TSP_S2P1_TS_SIN_C1 0x0400 249 #define REG_TSO_TSP_S2P1_3WIRE 0x0800 250 #define REG_TSO_TSP_BYPASS_S2P1 0x1000 251 252 253 typedef struct _REG_SecFlt 254 { 255 TSP32 Ctrl; 256 // Software Usage Flags 257 #define TSP_SECFLT_USER_MASK 0x00000007 258 #define TSP_SECFLT_USER_SHFT 0 259 #define TSP_SECFLT_USER_NULL 0x0 260 #define TSP_SECFLT_USER_SEC 0x1 261 #define TSP_SECFLT_USER_PES 0x2 262 #define TSP_SECFLT_USER_PKT 0x3 263 #define TSP_SECFLT_USER_PCR 0x4 264 #define TSP_SECFLT_USER_TTX 0x5 265 /* 266 #define TSP_SECFLT_USER_EMM 0x6 267 #define TSP_SECFLT_USER_ECM 0x7 268 #define TSP_SECFLT_USER_OAD 0x8 269 */ 270 271 #define TSP_SEC_MATCH_INV 0x00000008 // HW 272 273 // for 274 // TSP_SECFLT_TYPE_SEC 275 // TSP_SECFLT_TYPE_PES 276 // TSP_SECFLT_TYPE_PKT 277 // TSP_SECFLT_TYPE_TTX 278 // TSP_SECFLT_TYPE_OAD 279 #define TSP_SECFLT_MODE_MASK 0x00000030 // software implementation 280 #define TSP_SECFLT_MODE_SHFT 4 281 #define TSP_SECFLT_MODE_CONTI 0x0 // SEC 282 #define TSP_SECFLT_MODE_ONESHOT 0x1 283 #define TSP_SECFLT_MODE_CRCCHK 0x2 284 // for TSP_SECFLT_TYPE_PCR 285 #define TSP_SECFLT_PCRRST 0x00000010 //[OBSOLETED] PCR 286 287 288 //[NOTE] update section filter 289 // It's not recommended for user updating section filter control register 290 // when filter is enable. There may be race condition. 291 #define TSP_SECFLT_STATE_MASK 0x000000C0 // software implementation 292 #define TSP_SECFLT_STATE_SHFT 6 293 #define TSP_SECFLT_STATE_OVERFLOW 0x1 294 #define TSP_SECFLT_STATE_DISABLE 0x2 295 296 #define TSP_SECFLT_BEMASK 0x0000FF00 //[Reserved] 297 298 299 // for 300 // TSP_SECFLT_SEL_BUF 301 #define TSP_SECFLT_SECBUF_MASK 0xFF000000 // [31:26] secbuf id 302 #define TSP_SECFLT_SECBUF_SHFT 24 303 #define TSP_SECFLT_SECBUF_MAX 0xFF // software usage 304 305 TSP32 Match[TSP_FILTER_DEPTH/sizeof(TSP32)]; 306 TSP32 Mask[TSP_FILTER_DEPTH/sizeof(TSP32)]; 307 /* 308 TSP32 BufStart; 309 TSP32 BufEnd; 310 TSP32 BufRead; 311 TSP32 BufWrite; 312 TSP32 BufCur; 313 */ 314 TSP32 _x24[(0x38-0x24)/sizeof(TSP32)]; // (0x00211024-0x0021103B)/4 315 316 TSP32 RmnCnt; 317 #define TSP_SECFLT_ALLOC_MASK 0x80000000 318 #define TSP_SECFLT_ALLOC_SHFT 31 319 #define TSP_SECFLT_OWNER_MASK 0x70000000 320 #define TSP_SECFLT_OWNER_SHFT 24 321 322 #define TSP_SECFLT_MODE_AUTO_CRCCHK 0x00100000 //sec flt mode bits are not enough, arbitrarily occupy here 323 324 #define TSP_SECBUF_RMNCNT_MASK 0x0000FFFF // TS/PES length 325 #define TSP_SECBUF_RMNCNT_SHFT 0 326 327 /* 328 // for 329 // TSP_SECFLT_TYPE_ECM 330 #define TSP_SECFLT_ECM_IDX_SHFT 16 331 #define TSP_SECFLT_ECM_IDX_MASK 0x00070000 332 #define TSP_SECFLT_ECM_IDX_NULL 0x00000007 // only alow 0 .. 5 333 */ 334 335 TSP32 CRC32; 336 TSP32 NMask[TSP_FILTER_DEPTH/sizeof(MS_U32)]; 337 TSP32 _x50[(0x80-0x50)/sizeof(TSP32)]; // (0x00211050-0x0021107F)/4 338 } REG_SecFlt; 339 340 typedef struct _REG_SecBuf 341 { 342 TSP32 Start; 343 #define TSP_SECBUF_START_MASK 0x1FFFFFF0 //section buffers of kaiser and keltic are "4" bits aligment 344 #define TSP_SECBUF_OWNER_MASK 0x60000000 345 #define TSP_SECBUF_OWNER_SHFT 29 346 #define TSP_SECBUF_ALLOC_MASK 0x80000000 347 #define TSP_SECBUF_ALLOC_SHFT 31 348 TSP32 End; 349 TSP32 Read; 350 TSP32 Write; 351 TSP32 Cur; 352 TSP32 _x38[(0xA4-0x38)/sizeof(TSP32)]; // (0x0021103C-0x002110A4)/4 353 } REG_SecBuf; 354 355 typedef struct _REG_Pid 356 { // CPU(byte) RIU(index) MIPS(0x1500/2+RIU)*4 357 REG_PidFlt Flt[TSP_PIDFLT_NUM]; // 0x00210000-0x00210007C 358 } REG_Pid; 359 360 typedef struct _REG_Sec 361 { // CPU(byte) RIU(index) MIPS(0x1500/2+RIU)*4 362 REG_SecFlt Flt[TSP_SECFLT_NUM]; 363 } REG_Sec; 364 365 366 typedef struct _REG_Buf 367 { 368 REG_SecBuf Buf[TSP_SECFLT_NUM]; 369 } REG_Buf; 370 371 372 //@NOTE TSP 0~1 373 typedef struct _REG_Ctrl 374 { 375 //---------------------------------------------- 376 // 0xBF802A00 MIPS direct access 377 //---------------------------------------------- 378 // Type Name Index(word) CPU(byte) MIPS(0x1500/2+index)*4 379 REG16 _xbf202a00; // 0xbf802a00 0x00 380 REG32 Str2mi_head2pvr1; // 0xbf802a04 0x01 381 #define TSP_HW_PVR1_BUF_HEAD2_MASK 0x0FFFFFFF 382 383 REG32 Str2mi_mid2pvr1; // 0xbf802a0c 0x03 ,wptr & mid share same register 384 #define TSP_HW_PVR1_BUF_MID2_MASK 0x0FFFFFFF 385 386 REG32 Str2mi_tail2pvr1; // 0xbf802a14 0x05 387 #define TSP_HW_PVR1_BUF_TAIL2_MASK 0x0FFFFFFF 388 389 REG32 Pcr_L; // 0xbf802a1c 0x07 390 #define TSP_PCR64_L32_MASK 0xFFFFFFFF 391 392 REG32 Pcr_H; // 0xbf802a24 0x09 393 #define TSP_PCR64_H32_MASK 0xFFFFFFFF // PCR64 Middle 64 394 395 REG16 Mobf_Filein_Idx; // 0xbf802a2c 0x0b 396 #define TSP_MOBF_FILEIN_MASK 0x0000001F 397 398 REG32 _xbf202a2c; // 0xbf802a30 0x0c 399 400 REG32 PVR2_Config; // 0xbf802a38 0x0e 401 #define TSP_PVR2_LPCR1_WLD 0x00000001 402 #define TSP_PVR2_LPCR1_RLD 0x00000002 403 #define TSP_PVR2_STR2MIU_DSWAP 0x00000004 404 #define TSP_PVR2_STR2MIU_EN 0x00000008 405 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010 406 #define TSP_PVR2_STR2MIU_BT_ORDER 0x00000020 407 #define TSP_PVR2_STR2MIU_PAUSE 0x00000040 408 #define TSP_PVR2_REG_PINGPONG_EN 0x00000080 409 #define TSP_PVR2_PVR_ALIGN_EN 0x00000100 410 #define TSP_PVR2_DMA_FLUSH_EN 0x00000200 411 #define TSP_PVR2_PKT192_EN 0x00000400 412 #define TSP_PVR2_BURST_LEN_MASK 0x00001800 413 #define TSP_PVR2_BURST_LEN_SHIFT 11 414 #define TSP_REC_DATA2_INV 0x00002000 415 #define TSP_V_BLOCK_DIS 0x00004000 416 #define TSP_V3d_BLOCK_DIS 0x00008000 417 #define TSP_A_BLOCK_DIS 0x00010000 418 #define TSP_AD_BLOCK_DIS 0x00020000 419 #define TSP_PVR1_BLOCK_DIS 0x00040000 420 #define TSP_PVR2_BLOCK_DIS 0x00080000 421 #define TSP_TS_IF2_EN 0x00100000 422 #define TSP_TS_DATA2_SWAP 0x00200000 423 #define TSP_P_SEL2 0x00400000 424 #define TSP_EXT_SYNC_SEL2 0x00800000 425 #define TSP_BYPASS_TSIF2 0x01000000 426 #define TSP_TEI_SKIP_PKT2 0x02000000 427 #define TSP_AC_BLOCK_DIS 0x04000000 428 #define TSP_ADD_BLOCK_DIS 0x08000000 429 #define TSP_CLR_LOCKED_PKT_CNT 0x20000000 430 #define TSP_CLR_PKT_CNT 0x40000000 431 #define TSP_CLR_PVR_OVERFLOW 0x80000000 432 433 REG32 PVR2_LPCR1; // 0xbf802a40 0x10 434 435 #define TSP_STR2MI2_ADDR_MASK 0x0FFFFFFF 436 REG32 Str2mi_head1_pvr2; // 0xbf802a48 0x12 437 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14 438 REG32 Str2mi_tail1_pvr2; // 0xbf802a58 0x16 439 REG32 Str2mi_head2_pvr2; // 0xbf802a60 0x18 440 REG32 Str2mi_mid2_pvr2; // 0xbf802a68 0x1a, PVR2 mid address & write point 441 REG32 Str2mi_tail2_pvr2; // 0xbf802a70 0x1c 442 REG32 Hw_SyncByte2; // 0xbf802a78 0x1e 443 #define TSP_HW_CFG2_PACKET_SYNCBYTE2_MASK 0x000000FF 444 #define TSP_HW_CFG2_PACKET_SYNCBYTE2_SHFT 0 445 #define TSP_HW_CFG2_PACKET_SIZE2_MASK 0x0000FF00 446 #define TSP_HW_CFG2_PACKET_SIZE2_SHFT 8 447 #define TSP_HW_CFG2_PACKET_CHK_SIZE2_MASK 0x00FF0000 448 #define TSP_HW_CFG2_PACKET_CHK_SIZE2_SHFT 16 449 450 REG32 Pkt_CacheW0; // 0xbf802a80 0x20 451 452 REG32 Pkt_CacheW1; // 0xbf802a88 0x22 453 454 REG32 Pkt_CacheW2; // 0xbf802a90 0x24 455 456 REG32 Pkt_CacheW3; // 0xbf802a98 0x26 457 458 REG32 Pkt_CacheIdx; // 0xbf802aa0 0x28 459 460 REG32 Pkt_DMA; // 0xbf802aa8 0x2a 461 #define TSP_SEC_DMAFIL_NUM_MASK 0x000000FF 462 #define TSP_SEC_DMAFIL_NUM_SHIFT 0 463 #define TSP_SEC_DMASRC_OFFSET_MASK 0x0000FF00 464 #define TSP_SEC_DMASRC_OFFSET_SHIFT 8 465 #define TSP_SEC_DMADES_LEN_MASK 0x00FF0000 466 #define TSP_SEC_DMADES_LEN_SHIFT 16 467 468 REG16 Hw_Config0; // 0xbf802ab0 0x2c 469 #define TSP_HW_CFG0_DATA_PORT_SEL 0x0001 //TSIF0 data port output select. 0: select live TS to be TSIF output 1: select data port to be TSIF output 470 #define TSP_HW_CFG0_TSIFO_SERL 0x0000 471 #define TSP_HW_CFG0_TSIF0_PARL 0x0002 472 #define TSP_HW_CFG0_TSIF0_EXTSYNC 0x0004 473 #define TSP_HW_CFG0_TSIF0_TS_BYPASS 0x0008 474 #define TSP_HW_CFG0_TSIF0_VPID_BYPASS 0x0010 475 #define TSP_HW_CFG0_TSIF0_APID_BYPASS 0x0020 476 #define TSP_HW_CFG0_WB_DMA_RESET 0x0040 477 #define TSP_HW_CFG0_PACKET_BUF_SIZE_MASK 0xFF00 478 #define TSP_HW_CFG0_PACKET_BUF_SIZE_SHIFT 8 479 480 REG16 Hw_PktSize0; // 0xbf802ab4 0x2d 481 #define TSP_HW_CFG0_PACKET_PIDFLT0_SIZE_MASK 0x00FF 482 #define TSP_HW_CFG0_PACKET_PIDFLT0_SIZE_SHIFT 0 483 #define TSP_HW_CFG0_PACKET_CHK_SIZE_MASK 0xFF00 484 #define TSP_HW_CFG0_PACKET_CHK_SIZE_SHFT 8 485 486 REG16 _xbf202ab8; // 0xbf802ab8 0x2e 487 488 REG16 TSP_DBG_PORT; // 0xbf802ab8 0x2f 489 #define TSP_DNG_DATA_PORT_MASK 0x00FF 490 #define TSP_DNG_DATA_PORT_SHIFT 0 491 492 REG32 Pcr_L_CmdQ; // 0xbf802ac0 0x30 493 REG16 Pcr_H_CmdQ; // 0xbf802ac8 0x32 494 #define TSP_REG_PCR_CMDQ_H 0x0001 495 496 REG16 Vd_Pid_Hit; // 0xbf802acc 0x33 497 #define TSP_VPID_MASK 0x1FFF 498 499 REG16 Aud_Pid_Hit; // 0xbf802ad0 0x34 500 #define TSP_APID_MASK 0x1FFF 501 502 REG16 Pkt_Info; // 0xbf802ad4 0x35 503 #define TSP_PKT_PID_8_12_CP_MASK 0x001F 504 #define TSP_PKT_PID_8_12_CP_SHIFT 0 505 #define TSP_PKT_PRI_MASK 0x0020 506 #define TSP_PKT_PRI_SHIFT 5 507 #define TSP_PKT_PLST_MASK 0x0040 508 #define TSP_PKT_PLST_SHIFT 6 509 #define TSP_PKT_ERR 0x0080 510 #define TSP_PKT_ERR_SHIFT 7 511 512 REG16 Pkt_Info2; // 0xbf802ad8 0x36 513 #define TSP_PKT_INFO_CC_MASK 0x000F 514 #define TSP_PKT_INFO_CC_SHFT 0 515 #define TSP_PKT_INFO_ADPCNTL_MASK 0x0030 516 #define TSP_PKT_INFO_ADPCNTL_SHFT 4 517 #define TSP_PKT_INFO_SCMB 0x00C0 518 #define TSP_PKT_INFO_SCMB_SHFT 6 519 #define TSP_PKT_PID_0_7_CP_MASK 0xFF00 520 #define TSP_PKT_PID_0_7_CP_SHIFT 8 521 522 REG16 AVFifoSts; // 0xbf802adc 0x37 523 #define TSP_VFIFO3D_EMPTY 0x0001 524 #define TSP_VFIFO3D_EMPTY_SHFT 0 525 #define TSP_VFIFO3D_FULL 0x0002 526 #define TSP_VFIFO3D_FULL_SHFT 1 527 #define TSP_VFIFO3D_LEVEL 0x000C 528 #define TSP_VFIFO3D_LEVEL_SHFT 2 529 #define TSP_VFIFO_EMPTY 0x0010 530 #define TSP_VFIFO_EMPTY_SHFT 4 531 #define TSP_VFIFO_FULL 0x0020 532 #define TSP_VFIFO_FULL_SHFT 5 533 #define TSP_VFIFO_LEVEL 0x00C0 534 #define TSP_VFIFO_LEVEL_SHFT 6 535 #define TSP_AFIFO_EMPTY 0x0100 536 #define TSP_AFIFO_EMPTY_SHFT 8 537 #define TSP_AFIFO_FULL 0x0200 538 #define TSP_AFIFO_FULL_SHFT 9 539 #define TSP_AFIFO_LEVEL 0x0C00 540 #define TSP_AFIFO_LEVEL_SHFT 10 541 #define TSP_AFIFOB_EMPTY 0x1000 542 #define TSP_AFIFOB_EMPTY_SHFT 12 543 #define TSP_AFIFOB_FULL 0x2000 544 #define TSP_AFIFOB_FULL_SHFT 13 545 #define TSP_AFIFOB_LEVEL 0xC000 546 #define TSP_AFIFOB_LEVEL_SHFT 14 547 548 REG32 SwInt_Stat; // 0xbf802ae0 0x38 549 #define TSP_SWINT_INFO_SEC_MASK 0x000000FF 550 #define TSP_SWINT_INFO_SEC_SHFT 0 551 #define TSP_SWINT_INFO_ENG_MASK 0x0000FF00 552 #define TSP_SWINT_INFO_ENG_SHFT 8 553 #define TSP_SWINT_STATUS_CMD_MASK 0x7FFF0000 554 #define TSP_SWINT_STATUS_CMD_SHFT 16 555 #define TSP_SWINT_STATUS_SEC_RDY 0x0001 556 #define TSP_SWINT_STATUS_REQ_RDY 0x0002 557 #define TSP_SWINT_STATUS_SEC_RDY_CRCERR 0x0003 558 #define TSP_SWINT_STATUS_BUF_OVFLOW 0x0006 559 #define TSP_SWINT_STATUS_SEC_CRCERR 0x0007 560 #define TSP_SWINT_STATUS_SEC_ERROR 0x0008 561 #define TSP_SWINT_STATUS_SYNC_LOST 0x0010 562 #define TSP_SWINT_STATUS_PKT_OVRUN 0x0020 563 #define TSP_SWINT_STATUS_DEBUG 0x0030 564 #define TSP_SWINT_CMD_DMA_PAUSE 0x0100 565 #define TSP_SWINT_CMD_DMA_RESUME 0x0200 566 #define TSP_SWINT_STATUS_SEC_GROUP 0x000F 567 #define TSP_SWINT_STATUS_GROUP 0x00FF 568 #define TSP_SWINT_CMD_GROUP 0x7F00 569 #define TSP_SWINT_CMD_STC_UPD 0x0400 570 #define TSP_SWINT_CTRL_FIRE 0x80000000 571 572 REG32 TsDma_Addr; // 0xbf802ae8 0x3a 573 574 REG32 TsDma_Size; // 0xbf802af0 0x3c 575 576 REG16 TsDma_Ctrl; // 0xbf802af8 0x3e 577 #define TSP_TSDMA_CTRL_START 0x0001 578 #define TSP_TSDMA_FILEIN_DONE 0x0002 579 #define TSP_TSDMA_INIT_TRUST 0x0004 580 #define TSP_TSDMA_STAT_ABORT 0x0080 581 582 REG16 TsDma_mdQ; // 0xbf802af8 0x3f 583 #define TSP_CMDQ_CNT_MASK 0x001F 584 #define TSP_CMDQ_CNT_SHFT 0 585 #define TSP_CMDQ_FULL 0x0040 586 #define TSP_CMDQ_EMPTY 0x0080 587 #define TSP_CMDQ_SIZE 16 588 #define TSP_CMDQ_WR_LEVEL_MASK 0x0300 589 #define TSP_CMDQ_WR_LEVEL_SHFT 8 590 591 REG32 MCU_Cmd; // 0xbf802b00 0x40 592 #define TSP_MCU_CMD_MASK 0x0000FFFF 593 #define TSP_MCU_CMD_NULL 0x00000000 594 #define TSP_MCU_CMD_READ 0x00000001 595 #define TSP_MCU_CMD_WRITE 0x00000002 596 #define TSP_MCU_CMD_ALIVE 0x00000100 597 #define TSP_MCU_CMD_DBG 0x00000200 598 #define TSP_MCU_CMD_BUFRST 0x00000400 599 #define TSP_MCU_CMD_SECRDYINT_DISABLE 0x00000800 600 #define TSP_MCU_CMD_SEC_CC_CHECK_DISABLE 0x00001000 601 #define TSP_MCU_CMD_INFO 0x00008000 602 #define INFO_FW_VERSION 0x0001 603 #define INFO_FW_DATE 0x0002 604 605 REG16 PktSize1; // 0xbf802b08 0x42 606 #define TSP_HW_CFG2_PACKET_CHK_SIZE1_MASK 0x00FF 607 #define TSP_HW_CFG2_PACKET_CHK_SIZE1_SHFT 0 608 #define TSP_HW_CFG2_PACKET_SYNCBYTE1_MASK 0xFF00 609 #define TSP_HW_CFG2_PACKET_SYNCBYTE1_SHFT 8 610 611 REG16 Hw_Config2; // 0xbf802b0C 0x43 612 #define TSP_HW_CFG2_PACKET_SIZE1_MASK 0x00FF 613 #define TSP_HW_CFG2_PACKET_SIZE1_SHFT 0 614 #define TSP_HW_CFG2_TSIF1_SERL 0x0000 615 #define TSP_HW_CFG2_TSIF1_PARL 0x0100 616 #define TSP_HW_CFG2_TSIF1_EXTSYNC 0x0200 617 #define TSP_HW_CFG2_TSIF1_TS_BYPASS 0x1000 618 619 REG16 Hw_PVRCfg; // 0xbf802b10 0x44 620 #define TSP_HW_CFG4_SECDMA_PRI_HIGH 0x0001 621 #define TSP_HW_CFG4_PVR_ENABLE 0x0002 622 #define TSP_HW_CFG4_PVR_ENDIAN_BIG 0x0004 // 1: record TS to MIU with big endian, 0: record TS to MIU with little endian 623 #define TSP_HW_CFG4_TSIF1_ENABLE 0x0008 // 1: enable ts interface 1 and vice versa 624 #define TSP_HW_CFG4_PVR_FLUSH 0x0010 // 1: str2mi_wadr <- str2mi_miu_head 625 #define TSP_HW_CFG4_PVRBUF_BYTEORDER_BIG 0x0020 // Byte order of 8-byte recoding buffer to MIU. 626 #define TSP_HW_CFG4_PVR_PAUSE 0x0040 627 #define TSP_HW_CFG4_MEMTSDATA_ENDIAN_BIG 0x0080 // 32-bit data byte order read from 8x64 FIFO when playing file. 628 #define TSP_HW_CFG4_TSIF0_ENABLE 0x0100 // 1: enable ts interface 0 and vice versa 629 #define TSP_SYNC_RISING_DETECT 0x0200 // Reset bit count when data valid signal of TS interface is low. 630 #define TSP_VALID_FALLING_DETECT 0x0400 // Reset bit count on the rising sync signal of TS interface. 631 #define TSP_HW_CFG4_TS_DATA0_SWAP 0x0800 // Set 1 to swap the bit order of TS0 DATA bus 632 #define TSP_HW_CFG4_TS_DATA1_SWAP 0x1000 // Set 1 to swap the bit order of TS1 DATA bus 633 #define TSP_HW_TSP2OUTAEON_INT_EN 0x4000 // Set 1 to force interrupt to outside AEON 634 #define TSP_HW_HK_INT_FORCE 0x8000 // Set 1 to force interrupt to HK_MCU 635 636 REG16 Hw_Config4; // 0xbf802b14 0x45 637 #define TSP_HW_CFG4_ALT_TS_SIZE 0x0001 // enable TS packets in 204 mode 638 #define TSP_HW_CFG4_PS_AUDC_EN 0x0002 // program stream audiodC enable 639 #define TSP_HW_CFG4_BYTE_ADDR_DMA 0x000D // prevent from byte enable bug, bit1~3 must enable togather 640 #define TSP_HW_DMA_MODE_MASK 0x0030 // Section filter DMA mode, 2'b00: Single.2'b01: Burst 2 bytes.2'b10: Burst 4 bytes.2'b11: Burst 8 bytes. 641 #define TSP_HW_DMA_MODE_SHIFT 4 642 #define TSP_HW_CFG4_WSTAT_CH_EN 0x0040 643 #define TSP_HW_CFG4_PS_VID_EN 0x0080 // program stream video enable 644 #define TSP_HW_CFG4_PS_AUD_EN 0x0100 // program stream audio enable 645 #define TSP_HW_CFG4_PS_AUDB_EN 0x0200 // program stream audioB enable 646 #define TSP_HW_CFG4_APES_ERR_RM_EN 0x0400 // Set 1 to enable removing APES error packet 647 #define TSP_HW_CFG4_VPES_ERR_RM_EN 0x0800 // Set 1 to enable removing VPES error packet 648 #define TSP_HW_CFG4_SEC_ERR_RM_EN 0x1000 // Set 1 to enable removing section error packet 649 #define TSP_HW_CFG4_PS_AUDD_EN 0x2000 // program stream audioD enable 650 #define TSP_HW_CFG4_DATA_CHK_2T 0x8000 // Set 1 to enable the patch of internal sync in "tsif" 651 652 REG32 NOEA_PC; // 0xbf802b18 0x46 653 654 REG16 Idr_Ctrl; // 0xbf802b20 0x48 655 #define TSP_IDR_START 0x0001 656 #define TSP_IDR_READ 0x0000 657 #define TSP_IDR_WRITE 0x0002 658 #define TSP_IDR_WR_ENDIAN_BIG 0x0004 659 #define TSP_IDR_WR_ADDR_AUTO_INC 0x0008 // Set 1 to enable address auto-increment after finishing read/write 660 #define TSP_IDR_WDAT0_TRIG_EN 0x0010 // WDAT0_TRIG_EN 661 #define TSP_IDR_MCUWAIT 0x0020 662 #define TSP_IDR_SOFT_RST 0x0080 // Set 1 to soft-reset the IND32 module 663 #define TSP_IDR_AUTO_INC_VAL_MASK 0x0F00 664 #define TSP_IDR_AUTO_INC_VAL_SHIFT 8 665 666 REG32 Idr_Addr; // 0xbf802b24 0x49 667 REG32 Idr_Write; // 0xbf802b2c 0x4b 668 REG32 Idr_Read; // 0xbf802b34 0x4d 669 670 REG16 Fifo_Status; // 0xbf802b3c 0x4f 671 #define TSP_V3D_FIFO_DISCON 0x0010 672 #define TSP_V3D_FIFO_OVERFLOW 0x0020 673 #define TSP_VD_FIFO_DISCON 0x0200 674 #define TSP_VD_FIFO_OVERFLOW 0x0800 675 #define TSP_AUB_FIFO_OVERFLOW 0x1000 676 #define TSP_AU_FIFO_OVERFLOW 0x2000 677 678 // only 25 bits supported in PVR address. 8 bytes address 679 #define TSP_STR2MI2_ADDR_MASK 0x0FFFFFFF 680 REG32 TsRec_Head; // 0xbf802b40 0x50 681 REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid address & write point 682 REG32 TsRec_Tail; // 0xbf802b50 0x54 683 REG32 _xbf802b58[2]; // 0xbf802b58 ~ 0xbf802b60 0x56~0x59 684 685 REG16 reg15b4; // 0xbf802b68 0x5a 686 #define TSP_VQ_DMAW_PROTECT_EN 0x0001 687 #define TSP_SEC_CB_PVR2_DAMW_PROTECT_EN 0x0002 688 #define TSP_PVR_PID_BYPASS 0x0008 // Set 1 to bypass PID in record 689 #define TSP_PVR_PID_BYPASS2 0x0010 // Set 1 to bypass PID in record2 690 #define TSP_BD_AUD_EN 0x0020 // Set 1 to enable the BD audio stream recognization ( core /extend audio stream) 691 #define TSP_BD2_AUD_EN 0x0200 // Set 1 to enable the BD audio stream recognization ( core /extend audio stream) 692 #define TSP_AVFIFO_RD_EN 0x0080 // 0: AFIFO and VFIFO read are connected to MVD and MAD, 1: AFIFO and VFIFO read are controlled by registers (0x15B5[2:0]) 693 #define TSP_AVFIFO_RD 0x0100 // If AVFIFO_RD_EN is 1, set to 1, then set to 0 would issue a read strobe to AFIFO or VFIFO 694 #define TSP_NMATCH_DISABLE 0x0800 695 #define TSP_PVR_INVERT 0x1000 // Set 1 to enable data payload invert for PVR record 696 #define TSP_PLY_FILE_INV_EN 0x2000 // Set 1 to enable data payload invert in pidflt0 file path 697 #define TSP_PLY_TS_INV_EN 0x4000 // Set 1 to enable data payload invert in pidflt0 TS path 698 #define TSP_FILEIN_BYTETIMER_ENABLE 0x8000 // Set 1 to enable byte timer in ts_if0 TS path 699 700 REG16 reg15b8; // 0xbf802b6C 0x5b 701 #define TSP_PVR1_PINGPONG 0x0001 // Set 1 to enable MIU addresses with pinpon mode 702 #define TSP_VQ_STATUS_SEL 0x0002 703 #define TSP_TEI_SKIPE_PKT_PID0 0x0004 // Set 1 to skip error packets in pidflt0 TS path 704 #define TSP_TEI_SKIPE_PKT_PID4 0x0008 // Set 1 to skip error packets in pidflt4 TS path 705 #define TSP_TEI_SKIPE_PKT_PID1 0x0010 // Set 1 to skip error packets in pidflt1 TS path 706 #define TSP_TEI_SKIPE_PKT_PID3 0x0020 // Set 1 to skip error packets in pidflt3 TS path 707 #define TSP_REMOVE_DUP_AV_PKT 0x0040 // Set 1 to remove duplicate A/V packet 708 #define TSP_64bit_PCR2_ld 0x0080 709 #define TSP_cnt_33b_ld 0x0100 710 #define TSP_FORCE_SYNCBYTE 0x0200 // Set 1 to force sync byte (8'h47) in ts_if0 and ts_if1 path. 711 #define TSP_SERIAL_EXT_SYNC_LT 0x0400 // Set 1 to detect serial-in sync without 8-cycle mode 712 #define TSP_BURST_LEN_MASK 0x1800 // 00,01: burst length = 4; 10,11: burst length = 1 713 #define TSP_BURST_LEN_SHIFT 11 714 #define TSP_MATCH_PID_SRC_MASK 0xE000 // Select the source of pid filter number with hit pid and match pid number with scramble information, 00 : from pkt_demux0, 01 : from pkt_demux_file, 10 : from pkt_demux1, 11 : from pkt_demux2 715 #define TSP_MATCH_PID_SRC_SHIFT 13 716 #define TSP_MATCH_PID_SRC_PKTDMX0 0 717 #define TSP_MATCH_PID_SRC_PKTDMX1 1 718 #define TSP_MATCH_PID_SRC_PKTDMX2 2 719 #define TSP_MATCH_PID_SRC_PKTDMX3 3 720 721 REG32 TSP_MATCH_PID_NUM; // 0xbf802b70 0x5c 722 723 REG32 TSP_IWB_WAIT; // 0xbf802b78 0x5e // Wait count settings for IWB when TSP CPU i-cache is enabled. 724 725 REG32 Cpu_Base; // 0xbf802b80 0x60 726 #define TSP_CPU_BASE_ADDR_MASK 0x0FFFFFFF 727 728 REG32 Qmem_Ibase; // 0xbf802b88 0x62 729 730 REG32 Qmem_Imask; // 0xbf802b90 0x64 731 732 REG32 Qmem_Dbase; // 0xbf802b98 0x66 733 734 REG32 Qmem_Dmask; // 0xbf802ba0 0x68 735 736 REG32 TSP_Debug; // 0xbf802ba8 0x6a 737 #define TSP_DEBUG_MASK 0x00FFFFFF 738 739 REG32 _xbf802bb0; // 0xbf802bb0 0x6c 740 741 REG32 TsFileIn_RPtr; // 0xbf802bb8 0x6e 742 #define TSP_FILE_RPTR_MASK 0x0FFFFFFF 743 REG32 TsFileIn_Timer; // 0xbf802bc0 0x70 744 #define TSP_FILE_TIMER_MASK 0x00FFFFFF 745 REG32 TsFileIn_Head; // 0xbf802bc8 0x72 746 #define TSP_FILE_ADDR_MASK 0x0FFFFFFF 747 REG32 TsFileIn_Mid; // 0xbf802bd0 0x74 748 749 REG32 TsFileIn_Tail; // 0xbf802bd8 0x76 750 751 REG16 Dnld_Ctrl_Addr; // 0xbf802be0 0x78 752 #define TSP_DNLD_ADDR_MASK 0xFFFF 753 #define TSP_DNLD_ADDR_SHFT 0 754 #define TSP_DNLD_ADDR_ALI_SHIFT 4 // Bit [11:4] of DMA_RADDR[19:0] 755 756 REG16 Dnld_Ctrl_Size; // 0xbf802be4 0x79 757 #define TSP_DNLD_NUM_MASK 0xFFFF 758 #define TSP_DNLD_NUM_SHFT 0 759 760 REG16 TSP_Ctrl; // 0xbf802be8 0x7a 761 #define TSP_CTRL_CPU_EN 0x0001 762 #define TSP_CTRL_SW_RST 0x0002 763 #define TSP_CTRL_DNLD_START 0x0004 764 #define TSP_CTRL_DNLD_DONE 0x0008 // See 0x78 for related information 765 #define TSP_CTRL_TSFILE_EN 0x0010 766 #define TSP_CTRL_R_PRIO 0x0020 767 #define TSP_CTRL_W_PRIO 0x0040 768 #define TSP_CTRL_ICACHE_EN 0x0100 769 #define TSP_CTRL_CPU2MI_R_PRIO 0x0400 770 #define TSP_CTRL_CPU2MI_W_PRIO 0x0800 771 #define TSP_CTRL_I_EL 0x0000 772 #define TSP_CTRL_I_BL 0x1000 773 #define TSP_CTRL_D_EL 0x0000 774 #define TSP_CTRL_D_BL 0x2000 775 #define TSP_CTRL_NOEA_QMEM_ACK_DIS 0x4000 776 #define TSP_CTRL_MEM_TS_WORDER 0x8000 777 778 REG16 TSP_SyncByte; // 0xbf802bec 0x7b 779 #define TSP_SYNC_BYTE_MASK 0x00FF 780 #define TSP_SYNC_BYTE_SHIFT 0 781 782 REG16 PKT_CNT; // 0xbf802bf0 0x7c 783 #define TSP_PKT_CNT_MASK 0x00FF 784 785 REG16 DBG_SEL; // 0xbf802bf4 0x7d 786 #define TSP_DBG_SEL_MASK 0xFFFF 787 #define TSP_DBG_SEL_SHIFT 0 788 789 REG16 HwInt_Stat; // 0xbf802bf8 0x7e 790 /* 791 7: audio/video packet error 792 6: DMA read done 793 5: HK_INT_FORCE. // it's trigure bit is at bank 15 44 bit[15] 794 4: TSP_FILE_RP meets TSP_FILE_TAIL. 795 3: TSP_FILE_RP meets TSP_FILE_MID. 796 2: HK_INT_FORCE. // it's trigure bit is at bank 15 39 bit[15] 797 1: STR2MI_WADR meets STR2MI_MID. 798 0: STR2MI_WADR meets STR2MI_TAIL." 799 */ 800 #define TSP_INT_EN_MASK 0x00FF // Tsp2hk_int enable bits. 801 #define TSP_INT_EN_SHIFT 0 802 #define TSP_HWINT_TSP_PVR_TAIL0_EN 0x0001 // currently not used in ISR 803 #define TSP_HWINT_TSP_PVR_MID0_EN 0x0002 // currently not used in ISR 804 #define TSP_HWINT_HW_PVR0_EN_MASK (TSP_HWINT_TSP_PVR_TAIL0_EN | TSP_HWINT_TSP_PVR_MID0_EN) 805 #define TSP_HWINT_TSP_HK_INT_FORCE_EN 0x0004 // currently not used in ISR 806 #define TSP_HWINT_TSP_FILEIN_MID_INT_EN 0x0008 // currently not used in ISR 807 #define TSP_HWINT_TSP_FILEIN_TAIL_INT_EN 0x0010 // currently not used in ISR 808 #define TSP_HWINT_TSP_SW_INT_EN 0x0020 809 #define TSP_HWINT_TSP_DMA_READ_DONE_EN 0x0040 // currently not used in ISR 810 #define TSP_HWINT_TSP_AV_PKT_ERR_EN 0x0080 // currently not used in ISR 811 #define TSP_HWINT_TSP_SUPPORT_ALL (TSP_HWINT_TSP_SW_INT_EN) 812 #define TSP_HWINT_ALL TSP_HWINT_TSP_SUPPORT_ALL 813 814 #define TSP_HWINT_STATUS_MASK 0xFF00 815 #define TSP_HWINT_STATUS_SHIFT 8 816 #define TSP_HWINT_TSP_PVR_TAIL0_STATUS 0x0100 817 #define TSP_HWINT_TSP_PVR_MID0_STATUS 0x0200 818 #define TSP_HWINT_HW_PVR0_STATUS_MASK (TSP_HWINT_TSP_PVR_TAIL0_STATUS | TSP_HWINT_TSP_PVR_MID0_STATUS) 819 #define TSP_HWINT_TSP_HK_INT_FORCE_STATUS 0x0400 820 #define TSP_HWINT_TSP_FILEIN_MID_INT_STATUS 0x0800 821 #define TSP_HWINT_TSP_FILEIN_TAIL_INT_STATUS 0x1000 822 #define TSP_HWINT_TSP_SW_INT_STATUS 0x2000 823 #define TSP_HWINT_TSP_DMA_READ_DONE 0x4000 824 #define TSP_HWINT_TSP_AV_PKT_ERR 0x8000 825 826 // following mask is merged with bank 15 7e(LOW BYTE) and bank 16 6c(HIGH BYTE) 827 #define TSP_HWINT_HW_PVR_ALL_MASK (TSP_HWINT_HW_PVR0_STATUS_MASK | TSP_HWINT_HW_PVR1_MASK) //@FIXME this is for all pvr interrupt but PVR 3 and 4 is not added 828 829 REG16 TSP_Ctrl1; // 0xbf802bfc 0x7f 830 // 0x7f: TSP_CTRL1: hidden in HwInt_Stat 831 #define TSP_CTRL1_FILEIN_TIMER_ENABLE 0x0001 832 #define TSP_CTRL1_TSP_FILE_NON_STOP 0x0002 //Set 1 to enable TSP file data read without timer check 833 #define TSP_CTRL1_FILEIN_PAUSE 0x0004 //Set 1 to pause file-in engine fetch data 834 #define TSP_CTRL1_FILE_CHECK_WP 0x0008 835 #define TSP_CTRL1_FILE_WP_SEL_MASK 0x0030 836 #define TSP_CTRL1_FILE_WP_FI 0x0010 837 #define TSP_CTRL1_FILE_WP_PVR 0x0020 838 #define TSP_CTRL1_STANDBY 0x0080 839 #define TSP_CTRL1_INT2NOEA 0x0100 840 #define TSP_CTRL1_INT2NOEA_FORCE 0x0200 841 #define TSP_CTRL1_FORCE_XIU_WRDY 0x0400 842 #define TSP_CTRL1_CMDQ_RESET 0x0800 843 #define TSP_CTRL1_DLEND_EN 0x1000 // Set 1 to enable little-endian mode in TSP CPU 844 #define TSP_CTRL1_PVR_CMD_QUEUE_ENABLE 0x2000 845 #define TSP_CTRL1_FILEIN_RADDR_READ 0x4000 846 #define TSP_CTRL1_DMA_RST 0x8000 847 848 //---------------------------------------------- 849 // 0xBF802C00 MIPS direct access 850 //---------------------------------------------- 851 REG32 MCU_Data0; // 0xbf802c00 0x00 852 #define TSP_MCU_DATA_ALIVE TSP_MCU_CMD_ALIVE 853 854 REG32 PVR1_LPcr1; // 0xbf802c08 0x02 855 856 REG32 LPcr2; // 0xbf802c10 0x04 857 858 REG16 reg160C; // 0xbf802c18 0x06 859 #define TSP_PVR1_LPCR1_WLD 0x0001 // Set 1 to load LPCR1 value (Default: 0) 860 #define TSP_PVR1_LPCR1_RLD 0x0002 // Set 1 to read LPCR1 value (Default: 1) 861 #define TSP_LPCR2_WLD 0x0004 // Set 1 to load LPCR2 value (Default: 0) 862 #define TSP_LPCR2_RLD 0x0008 // Set 1 to read LPCR2 value (Default: 1) 863 #define TSP_RECORD192_EN 0x0010 // 160C bit(5)enable TS packets with 192 bytes on record mode 864 #define TSP_FILEIN192_EN 0x0020 // 160C bit(5)enable TS packets with 192 bytes on file-in mode 865 #define TSP_ORZ_DMAW_PROT_EN 0x0080 // 160C bit(7) open RISC DMA write protection 866 #define TSP_CLR_PIDFLT_BYTE_CNT 0x0100 // Clear pidflt0_file byte counter 867 #define TSP_DOUBLE_BUF_DESC 0x4000 // 160d bit(6) remove buffer limitation, Force pinpong buffer to flush 868 #define TSP_TIMESTAMP_RESET 0x8000 // 160d bit(7) reset timestamp 869 870 REG16 reg160E; // 0xbf802c1C 0x07 871 #define TSP_VQTX0_BLOCK_DIS 0x0001 872 #define TSP_VQTX1_BLOCK_DIS 0x0002 873 #define TSP_VQTX2_BLOCK_DIS 0x0004 874 #define TSP_VQTX3_BLOCK_DIS 0x0008 875 #define TSP_DIS_MIU_RQ 0x0010 // Disable miu R/W request for reset TSP usage 876 #define TSP_RM_DMA_GLITCH 0x0080 // Fix sec_dma overflow glitch 877 #define TSP_RESET_VFIFO 0x0100 // Reset VFIFO -- ECO Done 878 #define TSP_RESET_AFIFO 0x0200 // Reset AFIFO -- ECO Done 879 #define TSP_RESET_AFIFO3 0x0400 // Reset AFIFOC -- ECO Done 880 #define TSP_CLR_ALL_FLT_MATCH 0x0800 // Set 1 to clean all flt_match in a packet 881 #define TSP_RESET_AFIFO2 0x1000 882 #define TSP_RESET_VFIFO3D 0x2000 883 #define TSP_PVR_WPRI_HIGH 0x4000 884 #define TSP_OPT_ORACESS_TIMING 0x8000 885 886 REG16 PktChkSizeFilein; // 0xbf802c20 0x08 887 #define TSP_PKT_SIZE_MASK 0x00ff 888 #define TSP_PKT192_BLK_DIS_FIN 0x0100 // Set 1 to disable file-in timestamp block scheme 889 #define TSP_AV_CLR 0x0200 // Clear AV FIFO overflow flag and in/out counter 890 #define TSP_HW_STANDBY_MODE 0x0400 // Set 1 to disable all SRAM in TSP for low power mode automatically 891 #define TSP_RESET_AFIFO4 0x4000 // Reset AFIFOC -- ECO Done 892 893 REG16 TSP_Cfg5; // 0xbf802c24 0x09 894 #define TSP_PREVENT_OVF_META 0x0001 895 #define TSP_OVF_META_SEL 0x0004 896 #define TSP_SYSTIME_MODE 0x0008 897 #define TSP_SEC_DMA_BURST_EN 0x0080 // Enable Section DMA burst 898 899 REG16 Dnld_AddrH; // 0xbf802c28 0x0a 900 #define TSP_DMA_RADDR_MSB_MASK 0x00FF 901 #define TSP_DMA_RADDR_MSB_SHIFT 0 902 903 REG16 TSP_Ctrl2; // 0xbf802c2c 0x0b 904 #define TSP_CMQ_WORD_EN 0x0040 // Set 1 to access CMDQ related registers in word. 905 #define TSP_AV_DIRECT_STOP 0x0080 //Set 1 to enable A/V fifo full pull back tsif0 file in 906 #define TSP_AV_DIRECT_STOP1 0x0100 //Set 1 to enable A/V fifo full pull back tsif1 file in 907 #define TSP_AV_DIRECT_STOP2 0x0200 //Set 1 to enable A/V fifo full pull back tsif2 file in 908 #define TSP_AV_DIRECT_STOP3 0x0400 //Set 1 to enable A/V fifo full pull back tsif3 file in 909 #define TSP_TS_OUT_EN 0x1000 // TS_CB out enable. for Serial input to parallel output 910 #define TSP_PS_VID_3D_EN 0x2000 //Set 1 to enable video 3D path in program stream mode 911 912 REG32 TsPidScmbStatTsin; // 0xbf802c30 0x0c 913 914 REG32 TsPidScmbStatFile; // 0xbf802c38 0x0e 915 916 REG32 PCR64_2_L; // 0xbf802c40 0x10 917 918 REG32 PCR64_2_H; // 0xbf802c48 0x12 919 920 #define TSP_DMAW_BND_MASK 0xFFFFFFFFUL 921 REG32 DMAW_LBND0; // 0xbf802c50 0x14 //sec1 protect 922 923 REG32 DMAW_UBND0; // 0xbf802c58 0x16 924 925 REG32 DMAW_LBND1; // 0xbf802c60 0x18 //sec2 protect 926 927 REG32 DMAW_UBND1; // 0xbf802c68 0x1A 928 929 REG32 HW2_CFG6; // 0xbf802c68 0x1C 930 931 REG32 HW2_CFG5; // 0xbf802c68 0x1E 932 933 REG32 VQ0_BASE; // 0xbf802c80 0x20 934 935 REG16 VQ0_SIZE; // 0xbf802c84 0x22 936 #define TSP_VQ0_SIZE_208PK_MASK 0xFFFF 937 #define TSP_VQ0_SIZE_208PK_SHIFT 0 938 939 REG16 VQ0_CTRL; // 0xbf802c88 0x23 940 #define TSP_VQ0_WR_THRESHOLD_MASK 0x000F 941 #define TSP_VQ0_WR_THRESHOLD_SHIFT 0 942 #define TSP_VQ0_PRIORTY_THRESHOLD_MASK 0x00F0 943 #define TSP_VQ0_PRIORTY_THRESHOL_SHIFT 4 944 #define TSP_VQ0_FORCE_FIRE_CNT_1K_MASK 0x0F00 945 #define TSP_VQ0_FORCE_FIRE_CNT_1K_SHIFT 8 946 #define TSP_VQ0_RESET 0x1000 947 #define TSP_VQ0_OVERFLOW_INT_EN 0x4000 // Enable the interrupt for overflow happened on Virtual Queue path 948 #define TSP_VQ0_CLR_OVERFLOW_INT 0x8000 // Clear the interrupt and the overflow flag 949 950 REG16 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 951 952 #define TSP_REQ_VQ_RX_THRESHOLD_MASKE 0x000E 953 #define TSP_REQ_VQ_RX_THRESHOLD_SHIFT 1 954 #define TSP_REQ_VQ_RX_THRESHOLD_LEN1 0x0000 955 #define TSP_REQ_VQ_RX_THRESHOLD_LEN2 0x0002 956 #define TSP_REQ_VQ_RX_THRESHOLD_LEN4 0x0004 957 #define TSP_REQ_VQ_RX_THRESHOLD_LEN8 0x0006 958 #define TSP_PIDFLT0_OVF_INT_EN 0x0040 959 #define TSP_PIDFLT0_CLR_OVF_INT 0x0080 960 #define TSP_PIDFLT1_OVF_INT_EN 0x0100 961 #define TSP_PIDFLT1_CLR_OVF_INT 0x0200 962 #define TSP_PIDFLT2_OVF_INT_EN 0x0400 963 #define TSP_PIDFLT2_CLR_OVF_INT 0x0800 964 965 REG16 _xbf202c94 ; // 0xbf802c94 0x25 966 967 REG16 MOBF_PVR1_Index[2]; // 0xbf3a2c98 0x26 968 #define TSP_MOBF_PVR1_INDEX_MASK 0x0000001F 969 #define TSP_MOBF_PVR1_INDEX_SHIFT 0 970 971 REG16 MOBF_PVR2_Index[2]; // 0xbf3a2cA0 0x28 972 #define TSP_MOBF_PVR2_INDEX_MASK 0x0000001F 973 #define TSP_MOBF_PVR2_INDEX_SHIFT 0 974 975 REG32 DMAW_LBND2; // 0xbf802ca8 0x2a //PVR protect 976 #define TSP_PVR_MASK 0x0FFFFFFFUL 977 978 REG32 DMAW_UBND2; // 0xbf802cb0 0x2c 979 980 REG32 DMAW_LBND3; // 0xbf802cb8 0x2e //PVR 2 protect 981 982 REG32 DMAW_UBND3; // 0xbf802cc0 0x30 983 984 REG32 DMAW_LBND4; // 0xbf802cc8 0x32 //PVR 3 protect 985 986 REG32 DMAW_UBND4; // 0xbf802cd0 0x34 987 988 REG32 ORZ_DMAW_LBND; // 0xbf802cd8 0x36 //CPU protect 989 #define TSP_ORZ_DMAW_LBND_MASK 0xffffffffUL //protect address is base on MIU unit (16byte aligment) 990 REG32 ORZ_DMAW_UBND; // 0xbf802ce0 0x38 991 #define TSP_ORZ_DMAW_UBND_MASK 0xffffffffUL 992 993 REG16 PIDFLT_PCR0; // 0xbf802ce8 0x3a 994 #define TSP_PIDFLT_PCR0_PID_MASK 0x1fff 995 #define TSP_PIDFLT_PCR0_EN 0x8000 996 997 998 REG16 PIDFLT_PCR1; // 0xbf802ce8 0x3b 999 #define TSP_PIDFLT_PCR1_PID_MASK 0x1fff 1000 #define TSP_PIDFLT_PCR1_EN 0x8000 1001 1002 REG32 HWPCR0_L; // 0xbf802cf0 0x3c 1003 REG32 HWPCR0_H; // 0xbf802cf8 0x3e 1004 1005 REG32 CA_CTRL; // 0xbf802d00 0x40 1006 #define TSP_CA_CTRL_MASK 0xffffffff 1007 #define TSP_CA0_INPUT_TSIF0_LIVEIN 0x00000001 1008 #define TSP_CA0_INPUT_TSIF0_FILEIN 0x00000002 1009 #define TSP_CA0_INPUT_TSIF1 0x00000004 1010 #define TSP_CA0_AVPAUSE 0x00000008 1011 #define TSP_CA0_OUTPUT_PKTDMX0_LIVE 0x00000010 1012 #define TSP_CA0_OUTPUT_PKTDMX0_FILE 0x00000020 1013 #define TSP_CA0_OUTPUT_PKTDMX1 0x00000040 //pkt_demux1 1014 #define TSP_CA0_INPUT_TSIF2 0x00001000 1015 #define TSP_CA0_OUTPUT_PKTDMX2 0x00002000 //pkt_demux2 1016 #define TSP_CA2_INPUT_TSIF2 0x00100000 1017 #define TSP_CA2_OUTPUT_REC2 0x00200000 //pkt_demux2 1018 #define TSP_CA2_INPUT_TSIF0_LIVEIN 0x01000000 1019 #define TSP_CA2_INPUT_TSIF0_FILEIN 0x02000000 1020 #define TSP_CA2_INPUT_TSIF1 0x04000000 1021 #define TSP_CA2_OUTPUT_PLAY_LIVE 0x10000000 1022 #define TSP_CA2_OUTPUT_PLAY_FILE 0x20000000 1023 #define TSP_CA2_OUTPUT_REC1 0x40000000 //pkt_demux1 1024 1025 REG16 OneWay; // 0xbf802d08 0x42 , 1026 #define TSP_ONEWAY_CAREC_DISABLE 0x0001 1027 #define TSP_ONEWAY_PVR 0x0002 1028 #define TSP_ONEWAY_PVR1 0x0004 1029 #define TSP_ONEWAY_FW 0x0008 1030 #define TSP_ONEWAY_QMEM 0x0010 1031 #define TSP_ONEWAY_PVR2 0x0020 1032 #define TSP_ONEWAY_FIQ 0x0040 1033 1034 REG16 _xbf202d0C; // 0xbf802d0C 0x43 1035 1036 REG32 HWPCR1_L; // 0xbf802d10 0x44 1037 REG32 HWPCR1_H; // 0xbf802d18 0x46 1038 1039 REG16 IND32_CMD; // 0xbf802d20 0x48 1040 1041 REG32 IND32_ADDR; // 0xbf802d24 0x49, Indirect address to TSP CPU 1042 1043 REG32 IND32_WDATA; // 0xbf802d2C 0x4B, Indirect write data to TSP CPUr 1044 1045 REG32 IND32_RDATA; // 0xbf802d34 0x4D, IND32_WDATA 1046 1047 REG16 _xbf202d3c; // 0xbf802d3C 0x4F 1048 1049 REG16 FIFO_Src; // 0xbf802d40 0x50 1050 #define TSP_AUD_SRC_MASK 0x0007 1051 #define TSP_AUD_SRC_SHIFT 0 1052 #define TSP_AUDB_SRC_MASK 0x0038 1053 #define TSP_AUDB_SRC_SHIFT 3 1054 #define TSP_VID_SRC_MASK 0x01C0 1055 #define TSP_VID_SRC_SHIFT 6 1056 #define TSP_VID3D_SRC_MASK 0x0E00 1057 #define TSP_VID3D_SRC_SHIFT 9 1058 #define TSP_PVR1_SRC_MASK 0x7000 1059 #define TSP_PVR1_SRC_SHIFT 12 1060 #define TSP_PVR2_SRC_MASK_L 0x8000 1061 #define TSP_PVR2_SRC_SHIFT_L 15 1062 1063 REG16 PCR_Cfg; // 0xbf802d44 0x51 1064 #define TSP_PVR2_SRC_MASK_H 0x0003 1065 #define TSP_PVR2_SRC_SHIFT_H 0 1066 #define TSP_AUDC_SRC_MASK 0x001C 1067 #define TSP_AUDC_SRC_SHIFT 2 1068 #define TSP_AUDD_SRC_MASK 0x00E0 1069 #define TSP_AUDD_SRC_SHIFT 5 1070 #define TSP_TEI_SKIP_PKT_PCR0 0x0100 1071 #define TSP_PCR0_RESET 0x0200 1072 #define TSP_PCR0_INT_CLR 0x0400 1073 #define TSP_PCR0_READ 0x0800 1074 #define TSP_TEI_SKIP_PKT_PCR1 0x1000 1075 #define TSP_PCR1_RESET 0x2000 1076 #define TSP_PCR1_INT_CLR 0x4000 1077 #define TSP_PCR1_READ 0x8000 1078 1079 REG32 STC_DIFF_BUF; // 0xbf802d48 0x52 1080 1081 REG32 STC_DIFF_BUF_H; // 0xbf802d50 0x54 1082 #define TSP_STC_DIFF_BUF_H_MASK 0x0000000F 1083 #define TSP_STC_DIFF_BUF_H_AHIFT 0 1084 1085 REG32 VQ1_Base; // 0xbf802d58 0x56 1086 1087 REG32 _xbf202d60_6C[2]; // 0xbf802d60 0x58~0x5B 1088 1089 REG16 VQ1_Size; // 0xbf802d70 0x5C 1090 #define TSP_VQ1_SIZE_208PK_MASK 0xffff 1091 #define TSP_VQ1_SIZE_208PK_SHIFT 0 1092 1093 REG16 VQ1_Config; // 0xbf802d74 0x5d 1094 #define TSP_VQ1_WR_THRESHOLD_MASK 0x000F 1095 #define TSP_VQ1_WR_THRESHOLD_SHIFT 0 1096 #define TSP_VQ1_PRI_THRESHOLD_MASK 0x00F0 1097 #define TSP_VQ1_PRI_THRESHOLD_SHIFT 4 1098 #define TSP_VQ1_FORCEFIRE_CNT_1K_MASK 0x0F00 1099 #define TSP_VQ1_FORCEFIRE_CNT_1K_SHIFT 8 1100 #define TSP_VQ1_RESET 0x1000 1101 #define TSP_VQ1_OVF_INT_EN 0x4000 1102 #define TSP_VQ1_CLR_OVF_INT 0x8000 1103 1104 REG32 VQ2_Base; // 0xbf802d78 0x5E 1105 1106 REG32 TS_WatchDog_Cnt; // 0xbf802d80 0x60 1107 #define TSP_TS_WATCH_DOG_MASK 0xFFFF0000 1108 #define TSP_TS_WATCH_DOG_SHIFT 16 1109 1110 REG32 Bist_Fail; // 0xbf802d88 0x62 1111 #define TSP_BIST_FAIL_STATUS_MASK 0x00FF0000 1112 #define TSP_BIST_FAIL_STATUS_SRAM1P192x8_MASK 0x00070000 1113 #define TSP_BIST_FAIL_STATUS_SRAM2P512x32w8 0x00080000 1114 #define TSP_BIST_FAIL_STATUS_SRAM2P16x128_MASK 0x00600000 1115 #define TSP_BIST_FAIL_STATUS_SRAM1P2048x32w8 0x00800000 1116 #define TSP_BIST_FAIL_STATUS_SRAM1P1024x32w8 0x01000000 1117 #define TSP_BIST_FAIL_STATUS_SRAM1P512x20 0x00200000 1118 1119 REG16 VQ2_Size; // 0xbf802d90 0x64 1120 #define TSP_VQ2_SIZE_208PK_MASK 0xffff 1121 #define TSP_VQ2_SIZE_208PK_SHIFT 0 1122 1123 REG16 VQ2_Config; // 0xbf802d90 0x65 1124 #define TSP_VQ2_WR_THRESHOLD_MASK 0x000F 1125 #define TSP_VQ2_WR_THRESHOLD_SHIFT 0 1126 #define TSP_VQ2_PRI_THRESHOLD_MASK 0x00F0 1127 #define TSP_VQ2_PRI_THRESHOLD_SHIFT 4 1128 #define TSP_VQ2_FORCEFIRE_CNT_1K_MASK 0x0F00 1129 #define TSP_VQ2_FORCEFIRE_CNT_1K_SHIFT 8 1130 #define TSP_VQ2_RESET 0x1000 1131 #define TSP_VQ2_OVF_INT_EN 0x4000 1132 #define TSP_VQ2_CLR_OVF_INT 0x8000 1133 1134 REG32 VQ_STATUS; // 0xbf802d98 0x66 1135 #define TSP_VQ_STATUS_MASK 0xFFFFFFFF 1136 #define TSP_VQ_STATUS_SHIFT 0 1137 #define TSP_VQ0_STATUS_READ_EVER_FULL 0x00001000 1138 #define TSP_VQ0_STATUS_READ_EVER_OVERFLOW 0x00002000 1139 #define TSP_VQ0_STATUS_EMPTY 0x00004000 1140 #define TSP_VQ0_STATUS_READ_BUSY 0x00008000 1141 #define TSP_VQ1_STATUS_READ_EVER_FULL 0x00010000 1142 #define TSP_VQ1_STATUS_READ_EVER_OVERFLOW 0x00020000 1143 #define TSP_VQ1_STATUS_EMPTY 0x00040000 1144 #define TSP_VQ1_STATUS_READ_BUSY 0x00080000 1145 #define TSP_VQ2_STATUS_READ_EVER_FULL 0x00100000 1146 #define TSP_VQ2_STATUS_READ_EVER_OVERFLOW 0x00200000 1147 #define TSP_VQ2_STATUS_EMPTY 0x00400000 1148 #define TSP_VQ2_STATUS_READ_BUSY 0x00800000 1149 #define TSP_VQ0_STATUS_TX_OVERFLOW 0x10000000 1150 #define TSP_VQ1_STATUS_TX_OVERFLOW 0x20000000 1151 #define TSP_VQ2_STATUS_TX_OVERFLOW 0x40000000 1152 1153 REG32 DM2MI_WAddr_Err; // 0xbf802da0 0x68 , DM2MI_WADDR_ERR0 1154 1155 REG32 ORZ_DMAW_WAddr_Err; // 0xbf802da8 0x6a , ORZ_WADDR_ERR0 1156 1157 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c 1158 /* 1159 [7] : PVR2 meet_tail or PVR2_meet_mid 1160 [6] : vq0, vq1, vq2, vq3 overflow interrupt 1161 [5] : all DMA write address not in the protect zone interrupt 1162 [4] : PVR_cb meet the mid or PVR_cb meet the tail 1163 [3] : pcr filter 0 update finish 1164 [2] : pcr filter 1 update finish 1165 [1] : OTV HW interrupt 1166 [0] : reserved 1167 */ 1168 #define TSP_HWINT2_EN_MASK 0x00FF 1169 #define TSP_HWINT2_EN_SHIFT 0 1170 #define TSP_HWINT2_OTV_EN 0x0002 1171 #define TSP_HWINT2_PCR1_UPDATE_END_EN 0x0004 1172 #define TSP_HWINT2_PCR0_UPDATE_END_EN 0x0008 1173 #define TSP_HWINT2_ALL_DMA_WADDR_NOT_IN_PROCT_Z_EN 0x0020 1174 #define TSP_HWINT2_VQ0_VQ1_VQ2_VQ3_OVERFLOW_EN 0x0040 1175 #define TSP_HWINT2_PVR2_MID_TAIL_STATUS_EN 0x0080 1176 #define TSP_HWINT_PVR (TSP_HWINT2_PVR2_MID_TAIL_STATUS_EN) //@FIXME check what is this doing 1177 #define TSP_HWINT2_SUPPORT_ALL (TSP_HWINT2_PCR0_UPDATE_END_EN|TSP_HWINT2_PCR1_UPDATE_END_EN|TSP_HWINT2_OTV_EN) 1178 #define TSP_HWINT2_ALL TSP_HWINT2_SUPPORT_ALL 1179 1180 #define TSP_HWINT2_STATUS_MASK 0xFF00 1181 #define TSP_HWINT2_STATUS_SHIFT 8 1182 #define TSP_HWINT2_OTV 0x0200 1183 #define TSP_HWINT2_PCR1_UPDATE_END 0x0400 1184 #define TSP_HWINT2_PCR0_UPDATE_END 0x0800 1185 #define TSP_HWINT2_ALL_DMA_WADDR_NOT_IN_PROCT_Z 0x2000 1186 #define TSP_HWINT2_VQ0_VQ1_VQ2_VQ3_OVERFLOW 0x4000 1187 #define TSP_HWINT2_PVR2_MID_TAIL_STATUS 0x8000 1188 1189 REG32 SwInt_Stat1_H; // 0xbf802dB4 0x6d 1190 1191 REG16 _xbf202dbc; // 0xbf802dBC 0x6f 1192 1193 REG32 TimeStamp_FileIn; // 0xbf802dC0 0x70 1194 1195 REG16 HW2_Config3; // 0xbf802dC8 0x72 1196 #define TSP_PVR_DMAW_PROTECT_EN 0x0001 1197 #define TSP_WADDR_ERR_SRC_SEL_MASK 0x0006 1198 #define TSP_WADDR_ERR_SRC_SEL_SHIFT 1 1199 #define TSP_WADDR_ERR_SRC_PVR 0x0000 1200 #define TSP_WADDR_ERR_SRC_VQ 0x0002 1201 #define TSP_WADDR_ERR_SRC_SEC_CB 0x0004 1202 #define TSP_RM_OVF_GLITCH 0x0008 1203 #define TSP_FILEIN_RADDR_READ 0x0010 1204 #define TSP_DUP_PKT_CNT_CLR 0x0040 1205 #define TSP_DMA_FLUSH_EN 0x0080 //PVR1, PVR2 dma flush 1206 #define TSP_REC_AT_SYNC_DIS 0x0100 1207 #define TSP_PVR1_ALIGN_EN 0x0200 1208 #define TSP_REC_FORCE_SYNC_EN 0x0400 1209 #define TSP_RM_PKT_DEMUX_PIPE 0x0800 1210 #define TSP_VQ_EN 0x4000 1211 #define TSP_VQ2PINGPONG_EN 0x8000 1212 1213 REG16 PVRConfig; // 0xbf802dCC 0x73 1214 #define TSP_PVR1_REC_ALL_EN 0x0001 1215 #define TSP_PVR2_REC_ALL_EN 0x0002 1216 #define TSP_REC_NULL 0x0004 1217 #define TSP_REC_ALL_OLD 0x0008 1218 #define TSP_MATCH_PID_SEL_MASK 0x0700 1219 #define TSP_MATCH_PID_SEL_SHIFT 8 1220 #define TSP_MATCH_PID_LD 0x8000 1221 1222 REG32 VQ3_Base; //0x74~75 1223 1224 REG16 VQ3_Size; // 0x76 1225 #define TSP_VQ3_SIZE_208PK_MASK 0xffff 1226 #define TSP_VQ3_SIZE_208PK_SHIFT 0 1227 1228 REG16 VQ3_Config; //0x77 1229 #define TSP_VQ3_WR_THRESHOLD_MASK 0x000F 1230 #define TSP_VQ3_WR_THRESHOLD_SHIFT 0 1231 #define TSP_VQ3_PRI_THRESHOLD_MASK 0x00F0 1232 #define TSP_VQ3_PRI_THRESHOLD_SHIFT 4 1233 #define TSP_VQ3_FORCEFIRE_CNT_1K_MASK 0x0F00 1234 #define TSP_VQ3_FORCEFIRE_CNT_1K_SHIFT 8 1235 #define TSP_VQ3_RESET 0x1000 1236 #define TSP_VQ3_OVF_INT_EN 0x4000 1237 #define TSP_VQ3_CLR_OVF_INT 0x8000 1238 1239 REG32 VQ_RX_Status; // 0xbf802de0 0x78 1240 #define VQ_RX_ARBITER_MODE_MASK 0x0000000F 1241 #define VQ_RX_ARBITER_MODE_SHIFT 0 1242 #define VQ_RX0_PRI_MASK 0x000000F0 1243 #define VQ_RX0_PRI_SHIFT 4 1244 #define VQ_RX1_PRI_MASK 0x00000F00 1245 #define VQ_RX1_PRI_SHIFT 8 1246 #define VQ_RX2_PRI_MASK 0x0000F000 1247 #define VQ_RX2_PRI_SHIFT 12 1248 1249 REG32 _xbf802de8; // 0xbf802dC0 0x7a 1250 1251 REG32 MCU_Data1; // 0xbf802dC0 0x7c 1252 } REG_Ctrl; 1253 1254 //TSP 3 1255 typedef struct _REG_Ctrl2 //TSP3 0x1702 1256 { 1257 REG16 CFG_00; // 0x00 1258 #define CFG_00_TSP_FILE_IN_TSIF1_EN 0x0001 //Set 1: Enable FILE_input 1259 #define CFG_00_MEM_TS_DATA_ENDIAN_TSIF1 0x0002 //Set 1 to swap the byte order of TSIF1 DMA DATA bus 1260 #define CFG_00_TSP_FILE_SEGMENT_TSIF1 0x0004 1261 #define CFG_00_FILEIN_RADDR_READ_TSIF1 0x0008 //Read file DMA read address 1262 #define CFG_00_MEM_TS_W_ORDER_TSIF1 0x0010 //Set 1 to swap the word order of TSIF1 MIU DATA bus 1263 #define CFG_00_DIS_MIU_RQ_TSIF1 0x0020 //Disable the MIU request 1264 #define CFG_00_RST_TS_FIN1 0x0040 //reset TSIF1 1265 #define CFG_00_RST_FILEIN_TSIF1 0x0080 //reset the TSIF1 file in path 1266 #define CFG_00_RST_CMDQ_FILEIN_TSIF1 0x0100 //reset the file in TSIF1 command queue 1267 #define CFG_00_WB_RST_FILEIN_TSIF1 0x0200 //reset DMA to TSIF FSM in TSP clock Domain 1268 #define CFG_00_RST_WB_DMA_FILEIN_TSIF1 0x0400 //reset TSIF1 DMA in TSP clock Domain 1269 #define CFG_00_FILE2MI_PRI_TSIF1 0x0800 //Set 1: Higher MIU ABT read priority 1270 #define CFG_00_RST_READ_DMA_1 0x1000 //reset TSIF1 DMA in MIU clock Domain 1271 #define CFG_00_LPCR2_LOAD_TSIF1 0x2000 //Load lpcr2 from TSIF1 90k counter 1272 #define CFG_00_LPCR2_LOAD_BUF1 0x4000 //Load lpcr2 from pdflt1_buffer 90k counter 1273 #define CFG_00_LPCR2_LOAD_BUF0 0x8000 //Load lpcr2 from pdflt0_buffer 90k counter 1274 REG16 CFG_01; // 0x01 1275 #define CFG_01_TSP_FILE_SEGMENT1 0x0001 1276 #define CFG_01_TIMER_EN1 0x0002 //1: enable byte delay timer for TSIF1 filein path 0: packet delay timer 1277 #define CFG_01_PKT192_EN1 0x0004 //Set 1 to enable TS packets with 192 bytes on file-in mode. (Blocking TS packets by timestamp) 1278 #define CFG_01_PKT192_BLK_DISABLE1 0x0008 //Set 1 to disable file-in timestamp block scheme 1279 #define CFG_01_LPCR2_WLD1 0x0010 //Set PCR to TSIF1 90k counter 1280 #define CFG_01_TS_DATA_PORT_SEL1 0x0020 //TSIF1 data port output select. 0: select live TS to be TSIF output 1: select data port to be TSIF output 1281 #define CFG_01_PDFLT2_FILE_SRC 0x00c0 //00:disable 01:tsif0 file in port 10:tsif1 file in port 11:disable 1282 #define CFG_01_PDFLT2_FILE_SRC_SHIFT 6 1283 1284 #define CFG_01_PCR0_SRC_MASK 0x0f00 1285 #define CFG_01_PCR0_SRC_SHIFT 8 1286 #define CFG_01_PCR0_SRC_TSIF0 0x0 1287 #define CFG_01_PCR0_SRC_TSIF1 0x1 1288 #define CFG_01_PCR0_SRC_TSIF2 0x2 1289 #define CFG_01_PCR0_SRC_TSIF3 0x3 1290 #define CFG_01_PCR0_SRC_TSIF4 0x4 1291 #define CFG_01_PCR0_SRC_TSIF5 0x5 1292 #define CFG_01_PCR0_SRC_PKT_MERGE0 0x8 1293 #define CFG_01_PCR0_SRC_PKT_MERGE1 0x9 1294 #define CFG_01_PCR0_SRC_MM_FILEIN0 0xa 1295 #define CFG_01_PCR0_SRC_MM_FILEIN1 0xb 1296 #define CFG_01_PCR0_SRC_FIQ0 0xc 1297 #define CFG_01_PCR0_SRC_FIQ1 0xd 1298 1299 #define CFG_01_PCR1_SRC_MASK 0xf000 1300 #define CFG_01_PCR1_SRC_SHIFT 12 1301 #define CFG_01_PCR1_SRC_TSIF0 0x0 1302 #define CFG_01_PCR1_SRC_TSIF1 0x1 1303 #define CFG_01_PCR1_SRC_TSIF2 0x2 1304 #define CFG_01_PCR1_SRC_TSIF3 0x3 1305 #define CFG_01_PCR1_SRC_TSIF4 0x4 1306 #define CFG_01_PCR1_SRC_TSIF5 0x5 1307 #define CFG_01_PCR1_SRC_PKT_MERGE0 0x8 1308 #define CFG_01_PCR1_SRC_PKT_MERGE1 0x9 1309 #define CFG_01_PCR1_SRC_MM_FILEIN0 0xa 1310 #define CFG_01_PCR1_SRC_MM_FILEIN1 0xb 1311 #define CFG_01_PCR1_SRC_FIQ0 0xc 1312 #define CFG_01_PCR1_SRC_FIQ1 0xd 1313 REG16 CFG_02; 1314 #define CFG_02_PKT_CHK_SIZE_FIN1 0x00ff //(Packet Size - 1) for sync detection in TSIF1 1315 #define CFG_02_PKT_DEMUX_SIZE_1 0xff00 //(Packet Size - 1) for sync detection in pkt_demux1 1316 #define CFG_02_PKT_DEMUX_SIZE_1_SHIFT 8 1317 REG16 CFG_03; 1318 #define CFG_03_TSP_FILE_TIMER1 0xffff //Bit [15:0] of timer threshold for TS file playback data fetch from MIU. 1319 REG16 CFG_04; 1320 #define CFG_04_TSP_FILEIN_ABORT_ECO_TSIF0 0x0001 1321 #define CFG_04_TSP_FILEIN_ABORT_ECO_TSIF1 0x0002 1322 #define CFG_04_TSP_FILEIN_ABORT_ECO_TSIF2 0x0004 1323 #define CFG_04_TSP_FILEIN_ABORT_ECO_TSIF3 0x0008 1324 REG16 CFG_05; 1325 #define CFG_05_TSP_FILEIN_TSIF2 0x0001 //Set 1 to swap the word order of TSIF2 MIU DATA bus 1326 #define CFG_05_MEM_TS_DATA_EDIAN_TSIF2 0x0002 //Set 1 to swap the byte order of TSIF2 DMA DATA bus 1327 #define CFG_05_TSP_FILE_SEGMENT_TSIF2 0x0004 //set 0 to enable file in alignment mdoe 1328 #define CFG_05_FILEIN_RDDR_READ_TSIF2 0x0008 //Read file DMA read address 1329 #define CFG_05_MEM_TS_W_ORDER_TSIF2 0x0010 //Set 1: Enable FILE_input 1330 #define CFG_05_DIS_MIU_RQ_TSIF2 0x0020 //Disable the MIU request 1331 #define CFG_05_RST_TS_FIN2 0x0040 //reset TSIF2 1332 #define CFG_05_RST_FILEIN_TSIF2 0x0080 //reset the TSIF2 file in path 1333 #define CFG_05_RST_CMDQ_FILEIN_TSIF2 0x0100 //reset the file in TSIF2 command queue 1334 #define CFG_05_WB_RST_FILEIN_TSIF2 0x0200 //reset DMA to TSIF FSM in TSP clock Domain 1335 #define CFG_05_RST_WB_DMA_FILEIN_TSIF2 0x0400 //reset TSIF2 DMA in TSP clock Domain 1336 #define CFG_05_FILE2MI_PRI_TSIF2 0x0800 //Set 1: Higher MIU ABT read priority 1337 #define CFG_05_RST_READ_DMA_2 0x1000 //reset TSIF1 DMA in MIU clock Domain 1338 #define CFG_05_LPCR2_LOAD_TSIF2 0x2000 //Load lpcr2 from TSIF2 90k counter 1339 #define CFG_05_LPCR2_LOAD_BUF2 0x4000 //Load lpcr2 from pdflt2_buffer 90k counter 1340 REG16 CFG_06; 1341 #define CFG_06_TSP_FILE_SEGMENT2 0x0001 //set 0 to enable file in alignment mdoe 1342 #define CFG_06_TSP_TIMER_EN2 0x0002 //1: enable byte delay timer for TSIF2 filein path 0: packet delay timer 1343 #define CFG_06_TSP_PKT192_EN2 0x0004 //Set 1 to enable TS packets with 192 bytes on file-in mode. (Blocking TS packets by timestamp) 1344 #define CFG_06_TSP_PKT192_BLK_DISABLE2 0x0008 //Set 1 to disable file-in timestamp block scheme 1345 #define CFG_06_LPCR2_WLD2 0x0010 //Set PCR to TSIF2 90k counter 1346 #define CFG_06_TS_DATA_PORT_SEL2 0x0020 //TSIF2 data port output select. 0: select live TS to be TSIF output 1: select data port to be TSIF output 1347 #define CFG_06_PIDFLT5_FILE_SRC 0x00C0 //pdflt5 file in source 00:disable 01:tsif2 file in port 10:tsif3 file in port 11:disable 1348 #define CFG_06_PIDFLT5_FILE_SRC_SHIFT 6 1349 #define CFG_06_PCR0_ID_SEL 0x0700 //pkt merge multi-stream id select 0: stream 0 1: stream 1 2: stream 2 3: stream 3 1350 #define CFG_06_PCR0_ID_SEL_SHFIT 8 1351 #define CFG_06_PCR1_ID_SEL 0x3800 //pkt merge multi-stream id select 0: stream 0 1: stream 1 2: stream 2 3: stream 3 1352 #define CFG_06_PCR1_ID_SEL_SHFIT 11 1353 REG16 CFG_07; 1354 #define CFG_07_PKT_CHK_SIZE_FILEIN2 0x00ff //(Packet Size �V 1) for sync detection in TSIF2 1355 #define CFG_07_PKTDMX_SIZE2 0xff00 //(Packet Size �V 1) for sync detection in pkt_demux2 1356 #define CFG_07_PKTDMX_SIZE2_SHIFT 8 1357 REG16 CFG_08; 1358 #define CFG_08_TSP_FILE_TIMER2 0x00ff 1359 REG16 CFG_09; // reserved 1360 REG16 CFG_0A; 1361 #define CFG_0A_TSP_FILE_IN_TSIF3 0x0001 //Set 1: Enable FILE_input 1362 #define CFG_0A_MEM_TS_DATA_EDIAN_TSIF3 0x0002 //Set 1 to swap the byte order of TSIF3 DMA DATA bus 1363 #define CFG_0A_TSP_FILE_SEGMENT_TSIF3 0x0004 //set 0 to enable file in alignment mdoe 1364 #define CFG_0A_FILEIN_RADDR_READ_TSIF3 0x0008 //Read file DMA read address 1365 #define CFG_0A_MEM_TS_W_ORDER_TSIF3 0x0010 //Set 1: Enable FILE_input 1366 #define CFG_0A_DIS_MIU_RQ_TSIF3 0x0020 //Set 1 to swap the byte order of TSIF3 DMA DATA bus 1367 #define CFG_0A_RST_TS_FIN3 0x0040 //set 0 to enable file in alignment mdoe 1368 #define CFG_0A_RST_FILEIN_TSIF3 0x0080 //Read file DMA read address 1369 #define CFG_0A_RST_CMDQ_FILEIN_TSIF3 0x0100 //reset the file in TSIF3 command queue 1370 #define CFG_0A_WB_RST_FILEIN_TSIF3 0x0200 //reset DMA to TSIF FSM in TSP clock Domain 1371 #define CFG_0A_RST_WB_DMA_FILEIN_TSIF3 0x0400 //reset TSIF3 DMA in TSP clock Domain 1372 #define CFG_0A_FILE2MI_PRI_TSIF3 0x0800 //Set 1: Higher MIU ABT read priority 1373 #define CFG_0A_RST_READ_DMA_3 0x1000 //reset TSIF3 DMA in MIU clock Domain 1374 #define CFG_0A_LPCR2_LOAD_TSIF3 0x2000 //Load lpcr2 from TSIF3 90k counter 1375 #define CFG_0A_LPCR2_LOAD_BUF3 0x4000 //Load lpcr2 from pdflt3_buffer 90k counter 1376 REG16 CFG_0B; 1377 #define CFG_0B_TSP_FILE_SEGMENT3 0x0001 //set 0 to enable file in alignment mdoe 1378 #define CFG_0B_TIMER_EN3 0x0002 //1: enable byte delay timer for TSIF3 filein path 0: packet delay timer 1379 #define CFG_0B_PKT192_EN3 0x0004 //Set 1 to enable TS packets with 192 bytes on file-in mode. (Blocking TS packets by timestamp) 1380 #define CFG_0B_PKT192_BLK_DISABLE3 0x0008 //Set 1 to disable file-in timestamp block scheme 1381 #define CFG_0B_LPCR2_WLD3 0x0010 //Set PCR to TSIF3 90k counter 1382 #define CFG_0B_TS_DATA_PORT_SEL3 0x0020 //TSIF3 data port output select. 0: select live TS to be TSIF output 1: select data port to be TSIF output 1383 #define CFG_0B_P_SEL3 0x0040 //select parallel TS interface for TSIF3 1384 #define CFG_0B_EXT_SYNC_SEL3 0x0080 //select exteranl sync for ts_if3 1385 #define CFG_0B_TS_IF3_EN 0x0100 //set 1 tsif3 live in enable 1386 #define CFG_0B_TS_DATA3_SWAP 0x0200 //tsif3 live in bit order swap 1387 REG16 CFG_0C; 1388 #define CFG_0C_PKT_CHK_SIZE_FILEIN3 0x00ff //(Packet Size �V 1) for sync detection in TSIF3 1389 #define CFG_0C_PKT_DMX_SIZE3 0xff00 //(Packet Size �V 1) for sync detection in pkt_demux3 1390 #define CFG_0C_PKT_DMX_SIZE3_SHIFT 8 1391 1392 REG16 CFG_0D; 1393 #define CFG_0D_TSP_FILE_TIMER3 0xffff //Bit [15:0] of timer threshold for TS file playback data fetch from MIU. 1394 1395 REG16 CFG_0E; 1396 #define CFG_0E_PKT_DEMUX_SIZE_0 0x00ff //(Packet Size - 1) for sync detection in pkt_demux0 1397 #define CFG_0E_PKT_SIZE3 0xff00 //(Packet Size �V 1) for sync detection in pkt_flt3 1398 #define CFG_0E_PKT_SIZE3_SHIFT 8 1399 1400 REG16 CFG_0F; 1401 #define CFG_0F_PKT_CHK_SIZE3 0x00ff //(Packet Size �V 1) for sync detection in TSIF3. 1402 #define CFG_0F_SYNC_BYTE3 0xff00 //Sync byte for TSIF3 1403 #define CFG_0F_SYNC_BYTE3_SHIFT 8 1404 1405 REG16 CFG_10; 1406 #define CFG_10_RESET_PDFLT0 0x0001 //reset Pdflt0 1407 #define CFG_10_RESET_PDFLT1 0x0002 //reset Pdflt1 1408 #define CFG_10_RESET_PDFLT2 0x0004 //reset Pdflt2 1409 #define CFG_10_RESET_PDFLT3 0x0008 //reset Pdflt3 1410 REG16 CFG_11; 1411 #define CFG_11_RECEIVE_BUF0_SRC 0x0003 //Receive BUF0 input Stream source selection 00: pkt_merge0 01: pkt_merge1 10: Dscrmb 1412 #define CFG_11_RECEIVE_BUF0_SRC_SHIFT 0 1413 #define CFG_11_RECEIVE_BUF1_SRC 0x000c //Receive BUF1 input Stream source selection 00: pkt_merge0 01: pkt_merge1 10: Dscrmb 1414 #define CFG_11_RECEIVE_BUF1_SRC_SHIFT 2 1415 #define CFG_11_RECEIVE_BUF2_SRC 0x0030 //Receive BUF2 input Stream source selection 00: pkt_merge0 01: pkt_merge1 10: Dscrmb 1416 #define CFG_11_RECEIVE_BUF2_SRC_SHIFT 4 1417 #define CFG_11_RECEIVE_BUF3_SRC 0x00c0 //Receive BUF3 input Stream source selection 00: pkt_merge0 01: pkt_merge1 10: Dscrmb 1418 #define CFG_11_RECEIVE_BUF3_SRC_SHIFT 6 1419 REG16 CFG_12; 1420 #define CFG_12_TIMESTAMP_SEL_PVR1 0x0001 //PVR1 timestamp sel 0:local timestamp 1:stream timestamp 1421 #define CFG_12_TIMESTAMP_SEL_PVR2 0x0002 //PVR2 timestamp sel 0:local timestamp 1:stream timestamp 1422 #define CFG_12_TIMESTAMP_SEL_PVR3 0x0004 //PVR3 timestamp sel 0:local timestamp 1:stream timestamp 1423 #define CFG_12_TIMESTAMP_SEL_PVR4 0x0008 //PVR4 timestamp sel 0:local timestamp 1:stream timestamp 1424 1425 #define CFG_12_REG_REST_RBF0 0x0010 //reset Receive buffer0 1426 #define CFG_12_REG_REST_RBF1 0x0020 //reset Receive buffer1 1427 #define CFG_12_REG_REST_RBF2 0x0040 //reset Receive buffer2 1428 #define CFG_12_REG_REST_RBF3 0x0080 //reset Receive buffer2 1429 1430 #define CFG_12_REG_REST_PDBF0 0x0400 //reset Pdflt_buf0 1431 #define CFG_12_REG_REST_PDBF1 0x0800 //reset Pdflt_buf1 1432 #define CFG_12_REG_REST_PDBF2 0x1000 //reset Pdflt_buf2 1433 #define CFG_12_REG_REST_PDBF3 0x2000 //reset Pdflt_buf3 1434 REG16 CFG_13; 1435 #define CFG_13_LPCR_WLD0 0x0001 //Set PCR to pdflt_buf0 90k counter 1436 #define CFG_13_LPCR_EN0 0x0002 //Enable Pdflt_buf0 90k counter 1437 #define CFG_13_LPCR_WLD1 0x0004 //Set PCR to pdflt_buf1 90k counter 1438 #define CFG_13_LPCR_EN1 0x0008 //Enable Pdflt_buf1 90k counter 1439 #define CFG_13_LPCR_WLD2 0x0010 //Set PCR to pdflt_bu 1440 #define CFG_13_LPCR_EN2 0x0020 //Enable Pdflt_buf1 90k counter 1441 #define CFG_13_LPCR_WLD3 0x0040 //Set PCR to pdflt_bu 1442 #define CFG_13_LPCR_EN3 0x0080 //Enable Pdflt_buf1 90k counter 1443 #define CFG_13_REG_RESET_ABT0 0x4000 //reset pkt_merge0 1444 #define CFG_13_REG_RESET_ABT1 0x8000 //reset pkt_merge1 1445 REG16 CFG_14; 1446 #define CFG_14_ABT_PORT0_SRC 0x0007 //pkt_merge0 input Stream source selection 0: tsif0 stream 1: tsif1 stream 2: tsif2 stream 3: tsif3 stream 4: tsif4 stream 5: tsif5 stream 1447 #define CFG_14_ABT_PORT0_SRC_SHIFT 0 1448 #define CFG_14_ABT_PORT1_SRC 0x0038 //pkt_merge0 input Stream source selection 1: tsif0 stream 1: tsif1 stream 2: tsif2 stream 3: tsif3 stream 4: tsif4 stream 5: tsif5 stream 1449 #define CFG_14_ABT_PORT1_SRC_SHIFT 3 1450 #define CFG_14_ABT_PORT2_SRC 0x01c0 //pkt_merge0 input Stream source selection 2: tsif0 stream 1: tsif1 stream 2: tsif2 stream 3: tsif3 stream 4: tsif4 stream 5: tsif5 stream 1451 #define CFG_14_ABT_PORT2_SRC_SHIFT 6 1452 #define CFG_14_ABT_PORT3_SRC 0x1E00 //pkt_merge0 input Stream source selection 2: tsif0 stream 1: tsif1 stream 2: tsif2 stream 3: tsif3 stream 4: tsif4 stream 5: tsif5 stream 1453 #define CFG_14_ABT_PORT3_SRC_SHIFT 9 1454 REG16 CFG_15; 1455 #define CFG_15_RBUF_FULL_LEVEL 0x0038 1456 #define CFG_15_PVR3_SRC 0x0e00 //PVR3 input path sel 000: pkt_demux0 001: pkt_demux1 010: pkt_demux2 011: pkt_demux3 100: pkt_demux4 101: pkt_demux5 1457 #define CFG_15_PVR3_SRC_SHIFT 9 1458 #define CFG_15_PVR4_SRC 0x7000 //PVR4input path sel 000: pkt_demux0 001: pkt_demux1 010: pkt_demux2 011: pkt_demux3 100: pkt_demux4 101: pkt_demux5 1459 #define CFG_15_PVR4_SRC_SHIFT 12 1460 1461 REG16 CFG_16; 1462 #define CFG_16_PVR3_REG_PINGPONG_EN 0x0001 //set 1 to enable the pingpong buffer of PVR3 1463 #define CFG_16_PVR3_STR2MI_EN 0x0002 //set 1 to enable PVR3 1464 #define CFG_16_PVR3_STR2MI_RST_WADR 0x0004 //set 1 to reset the PVR3 write pointer to the head address 1465 #define CFG_16_PVR3_STR2MI_PAUSE 0x0008 //set 1 to pause PVR3 1466 #define CFG_16_PVR3_PKT192_EN 0x0010 //set 1 to enable 192 mode of PVR3 1467 #define CFG_16_PVR3_BURST_LEN_MASK 0x0060 //the PVR3 dma burst length 00 : burst 8 01 : burst 4 10/11 : burst 1 1468 #define CFG_16_PVR3_BURST_LEN_SHIFT 5 1469 #define CFG_16_PVR3_LPCR1_WLD 0x0080 //set 1 to write the value of lpcr1 from the register to the lpcr1_buf for PVR3 1470 #define CFG_16_PVR3_PVR_ALIGN_EN 0x0100 //set 1 to enable the function of alignment of PVR3 1471 #define CFG_16_PVR3_STR2MI_DSWAP 0x0200 //set 1 to swap the bit order of stream2miu data bus of PVR3 1472 #define CFG_16_PVR3_STR2MI_BT_ORDER 0x0400 //Byte order of 16-byte recoding buffer to MIU of PVR3 0: Little endian. 1: Big endian 1473 #define CFG_16_REC_DATA3_INV_EN 0x0800 //Set 1 to enable data payload invert for PVR record 1474 #define CFG_16_PVR3_BLOCK_DIS 0x1000 //set 1 to disable the PVR3 fifo blocking mechanism 1475 #define CFG_16_PID_BYPASS3_REC 0x2000 //0: record PES 1: record 188/192 1476 #define CFG_16_REC_ALL3 0x4000 //set 1 to record all 1477 #define CFG_16_PVR3_LPCR1_RLD 0x8000 //set 1 to read the value of lpcr1 from the register to the lpcr1_buf for PVR3 1478 REG32 CFG_17_18; 1479 #define CFG_17_18_PVR3_STR2MI_HEAD 0xffffffff //[31:27] : reserved [26:0] : MIU start address1 of TS recoding buffer for PVR3 1480 REG32 CFG_19_1A; 1481 #define CFG_19_1A_PVR3_STR2MI_MID 0xffffffff //[31:27] : reserved [26:0] : MIU middle address1 of TS recoding buffer for PVR3. 1482 REG32 CFG_1B_1C; 1483 #define CFG_1B_1C_PVR3_STR2MI_TAIL 0xffffffff //[31:27] : reserved [26:0] : MIU tail address1 of TS recoding buffer for PVR3. 1484 REG32 CFG_1D_1E; 1485 #define CFG_1D_1E_PVR3_STR2MI_HEAD2 0xffffffff //[31:27] : reserved [26:0] : MIU start address2 of TS recoding buffer for PVR3 1486 REG32 CFG_1F_20; 1487 #define CFG_1F_20_PVR3_STR2MI_MID2 0xffffffff //[31:27] : reserved [26:0] : MIU middle address2 of TS recoding buffer for PVR3. 1488 REG32 CFG_21_22; 1489 #define CFG_21_22_PVR3_STR2MI_TAIL2 0xffffffff //[31:27] : reserved [26:0] : MIU tail address2 of TS recoding buffer for PVR3. 1490 1491 REG16 CFG_23; 1492 #define CFG_23_PVR4_REG_PINGPONG_EN 0x0001 //set 1 to enable the pingpong buffer of PVR4 1493 #define CFG_23_PVR4_STR2MI_EN 0x0002 //set 1 to enable PVR4 1494 #define CFG_23_PVR4_STR2MI_RST_WADR 0x0004 //set 1 to reset the PVR4 write pointer to the head address 1495 #define CFG_23_PVR4_STR2MI_PAUSE 0x0008 //set 1 to pause PVR4 1496 #define CFG_23_PVR4_PKT192_EN 0x0010 //set 1 to enable 192 mode of PVR4 1497 #define CFG_23_PVR4_BURST_LEN_MASK 0x0060 //the PVR4 dma burst length 00 : burst 8 01 : burst 4 10/11 : burst 1 1498 #define CFG_23_PVR4_BURST_LEN_SHIFT 5 1499 #define CFG_23_PVR4_LPCR1_WLD 0x0080 //set 1 to write the value of lpcr1 from the register to the lpcr1_buf for PVR4 1500 #define CFG_23_PVR4_PVR_ALIGN_EN 0x0100 //set 1 to enable the function of alignment of PVR4 1501 #define CFG_23_PVR4_STR2MI_DSWAP 0x0200 //set 1 to swap the bit order of stream2miu data bus of PVR4 1502 #define CFG_23_PVR4_STR2MI_BT_ORDER 0x0400 //Byte order of 16-byte recoding buffer to MIU of PVR4 0: Little endian. 1: Big endian 1503 #define CFG_23_REC_DATA4_INV_EN 0x0800 //Set 1 to enable data payload invert for PVR record 1504 #define CFG_23_PVR4_BLOCK_DIS 0x1000 //set 1 to disable the PVR4 fifo blocking mechanism 1505 #define CFG_23_PID_BYPASS4_REC 0x2000 //0: record PES 1: record 188/192 1506 #define CFG_23_REC_ALL4 0x4000 //set 1 to record all 1507 #define CFG_23_PVR4_LPCR1_RLD 0x8000 //set 1 to read the value of lpcr1 from the register to the lpcr1_buf for PVR4 1508 1509 REG32 CFG_24_25; 1510 #define CFG_24_25_PVR4_STR2MI_HEAD 0xffffffff //[31:27] : reserved [26:0] : MIU start address1 of TS recoding buffer for PVR4 1511 REG32 CFG_26_27; 1512 #define CFG_26_27_PVR4_STR2MI_MID 0xffffffff //[31:27] : reserved [26:0] : MIU middle address1 of TS recoding buffer for PVR4 1513 REG32 CFG_28_29; 1514 #define CFG_28_29_PVR4_STR2MI_TAIL 0xffffffff //[31:27] : reserved [26:0] : MIU tail address1 of TS recoding buffer for PVR4 1515 REG32 CFG_2A_2B; 1516 #define CFG_2A_2B_PVR4_STR2MI_HEAD2 0xffffffff //[31:27] : reserved [26:0] : MIU start address2 of TS recoding buffer for PVR4 1517 REG32 CFG_2C_2D; 1518 #define CFG_2C_2D_PVR4_STR2MI_MID2 0xffffffff //[31:27] : reserved [26:0] : MIU middle address2 of TS recoding buffer for PVR4 1519 REG32 CFG_2E_2F; 1520 #define CFG_2E_2F_PVR4_STR2MI_TAIL2 0xffffffff //[31:27] : reserved [26:0] : MIU tail address2 of TS recoding buffer for PVR4 1521 1522 REG32 CFG_30_31; 1523 #define CFG_30_31_REG_TSP_FILEIN_RADDR_TSIF1 0xffffffff //Read start address [23:0] (byte unit) in tsif1 and command queue mode 1524 REG32 CFG_32_33; 1525 #define CFG_32_33_REG_TSP_FILEIN_RNUM_TSIF1 0xffffffff //Read number [23:0] (byte unit) in tsif1 and command queue mode 1526 REG16 CFG_34; 1527 #define CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_START 0x0001 //bit[0] Set 1 to start tsif1 in command 1528 #define CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_DONE 0x0002 //bit[1] 1 : FileIn done 1529 #define CFG_34_REG_TSP_FILEIN_INIT_TRUST_TSIF1 0x0004 //bit[2] filein_init_trust for tsif1 1530 #define CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_ABORT 0x0010 //bit[4] Set 1 to abort tsif1 in command queue mode 1531 REG32 CFG_35_36; 1532 #define CFG_35_36_TSP_FILEIN_RADDR_TSIF2 0xffffffff //[31:24] : reserved [23:0] : Read start address [15:0] [23:16](byte unit) in tsif2 and command queue mode 1533 REG32 CFG_37_38; 1534 #define CFG_37_38_TSP_FILEIN_RNUM_TSIF2 0xffffffff //[31:24] : reserved [23:0] : Read number [15:0] [23:16] (byte unit) in tsif2 and command queue mode 1535 REG16 CFG_39; 1536 #define CFG_39_FILEIN_CTRL_TSIF2_START 0x0001 //bit[0] Set 1 to start tsif2 in command 1537 #define CFG_39_FILEIN_CTRL_TSIF2_DONE 0x0002 //bit[1] 1: FileIn done 1538 #define CFG_39_FILEIN_INIT_TRUST_TSIF2 0x0004 //bit[2] filein_init_trust for tsif2 1539 #define CFG_39_FILEIN_CTRL_TSIF2_ABORT 0x0010 //bit[4] Set 1 to abort tsif2 in command queue mode 1540 REG32 CFG_3A_3B; 1541 #define CFG_3A_3B_TSP_FILEIN_RADDR_TSIF3 0xffffffff //[31:24] : reserved [23:0] : Read start address [15:0] [23:16](byte unit) in tsif2 and command queue mode 1542 REG32 CFG_3C_3D; 1543 #define CFG_3C_3D_TSP_FILEIN_RNUM_TSIF3 0xffffffff //[31:24] : reserved [23:0] : Read number [15:0] [23:16] (byte unit) in tsif2 and command queue mode 1544 REG16 CFG_3E; 1545 #define CFG_3E_FILEIN_CTRL_TSIF3_START 0x0001 //bit[0] Set 1 to start tsif2 in command 1546 #define CFG_3E_FILEIN_CTRL_TSIF3_DONE 0x0002 //bit[1] 1: FileIn done 1547 #define CFG_3E_FILEIN_INIT_TRUST_TSIF3 0x0004 //bit[2] filein_init_trust for tsif3 1548 #define CFG_3E_FILEIN_CTRL_TSIF3_ABORT 0x0010 //bit[4] Set 1 to abort tsif2 in command queue mode 1549 REG16 CFG_3F; 1550 #define CFG_3F_REG_TSIF1_CMD_QUEUE_WR_CNT 0x001f 1551 #define CFG_3F_REG_TSIF1_CMD_QUEUE_FIFO_FULL 0x0040 1552 #define CFG_3F_REG_TSIF1_CMD_QUEUE_FIFO_EMPTY 0x0080 1553 #define CFG_3F_REG_TSIF1_CMD_QUEUE_WR_LEVEL 0x0300 1554 #define CFG_3F_REG_TSIF1_CMD_QUEUE_LEVEL_SHIFT 8 1555 #define CFG_3F_REG_TSIF1_CMD_QUEUE_SIZE 16 1556 REG16 CFG_40; 1557 #define CFG_40_REG_TSIF2_CMD_QUEUE_WR_CNT 0x001f 1558 #define CFG_40_REG_TSIF2_CMD_QUEUE_FIFO_FULL 0x0040 1559 #define CFG_40_REG_TSIF2_CMD_QUEUE_FIFO_EMPTY 0x0080 1560 #define CFG_40_REG_TSIF2_CMD_QUEUE_WR_LEVEL 0x0300 1561 #define CFG_40_REG_TSIF2_CMD_QUEUE_LEVEL_SHIFT 8 1562 #define CFG_40_REG_TSIF2_CMD_QUEUE_SIZE 16 1563 REG16 CFG_41; 1564 #define CFG_41_REG_TSIF3_CMD_QUEUE_WR_CNT 0x001f 1565 #define CFG_41_REG_TSIF3_CMD_QUEUE_FIFO_FULL 0x0040 1566 #define CFG_41_REG_TSIF3_CMD_QUEUE_FIFO_EMPTY 0x0080 1567 #define CFG_41_REG_TSIF3_CMD_QUEUE_WR_LEVEL 0x0300 1568 #define CFG_41_REG_TSIF3_CMD_QUEUE_LEVEL_SHIFT 8 1569 #define CFG_41_REG_TSIF3_CMD_QUEUE_SIZE 16 1570 REG32 CFG_42_43; 1571 #define CFG_42_43_REG_TIMESTAMP_TSP_FILEIN_TSIF1 0xffffffff //tsif1 pkt timestamp 1572 REG32 CFG_44_45; 1573 #define CFG_44_45_REG_TIMESTAMP_TSP_FILEIN_TSIF2 0xffffffff //tsif2 pkt timestamp 1574 REG32 CFG_46_47; 1575 #define CFG_46_47_REG_TIMESTAMP_TSP_FILEIN_TSIF3 0xffffffff //tsif3 pkt timestamp 1576 REG16 CFG_48; 1577 #define CFG_48_REG_INT0 0xffff 1578 REG16 CFG_49; 1579 REG16 CFG_4A_4F[6]; 1580 REG32 CFG_50_51; 1581 #define CFG_50_51_LPCR2_TSIF1_RD 0xffffffff //tsif1 90k counter value 1582 REG32 CFG_52_53; 1583 #define CFG_52_53_LPCR2_TSIF2_RD 0xffffffff //tsif2 90k counter value 1584 REG32 CFG_54_55; 1585 #define CFG_54_55_LPCR2_TSIF3_RD 0xffffffff //tsif3 90k counter value 1586 REG32 CFG_56_57; 1587 #define CFG_56_57_LPCR2_BUF0_RD 0xffffffff // pdflt_buf0 90k counter value 1588 REG32 CFG_58_59; 1589 #define CFG_58_59_LPCR2_BUF1_RD 0xffffffff // pdflt_buf1 90k counter value 1590 REG32 CFG_5A_5B; 1591 #define CFG_5A_5B_LPCR2_BUF2_RD 0xffffffff // pdflt_buf2 90k counter value 1592 REG32 CFG_5C_5D; 1593 #define CFG_5C_5D_LPCR2_BUF3_RD 0xffffffff // pdflt_buf3 90k counter value 1594 REG32 CFG_5E_5F; 1595 #define CFG_5E_5F_LPCR2_BUF4_RD 0xffffffff // pdflt_buf4 90k counter value 1596 REG32 CFG_60_61; 1597 #define CFG_60_61_LPCR2_BUF5_RD 0xffffffff // pdflt_buf5 90k counter value 1598 REG32 CFG_62_63; 1599 #define CFG_62_63_LPCR2_PVR3_RD 0xffffffff // PVR3 90k counter value 1600 REG32 CFG_64_65; // Reserved 1601 #define CFG_64_65_LPCR2_PVR4_RD 0xffffffff // PVR4 90k counter value 1602 REG32 CFG_66_67; 1603 #define CFG_66_67_PVR3_STR2MI_WADR_R 0xffffffff // PVR3 write point 1604 REG32 CFG_68_69; 1605 #define CFG_68_69_PVR4_STR2MI_WADR_R 0xffffffff // PVR4 write point 1606 REG32 CFG_6A_6B; 1607 #define CFG_6A_6B_TSP2MI_RADDR_S_TSIF1 0x0fffffff // tsif1 DMA read point 1608 REG32 CFG_6C_6D; 1609 #define CFG_6C_6D_TSP2MI_RADDR_S_TSIF2 0x0fffffff // tsif2 DMA read point 1610 REG32 CFG_6E_6F; 1611 #define CFG_6E_6F_TSP2MI_RADDR_S_TSIF3 0x0fffffff // tsif3 DMA read point 1612 REG16 CFG_70; 1613 #define CFG_70_MATCHECED_VPID_3D_MASK 0x1fff 1614 #define CFG_70_CHANGE_VPID_3D 0x4000 1615 REG16 CFG_71; 1616 #define CFG_71_MATCHECED_APID_B_MASK 0x1fff 1617 #define CFG_71_CHANGE_APID_B 0x4000 1618 REG16 CFG_72; 1619 #define CFG_72_MERGE_FIFO_STATUS 0x1fff 1620 REG16 CFG_73; 1621 #define CFG_73_PVR_STATUS_PVR3_FIFO_MASK 0x000f 1622 #define CFG_73_PVR_STATUS_PVR3_FIFO_SHIFT 0 1623 #define CFG_73_PVR_STATUS_PVR3_EVER_OVERFLOW_MASK 0x0001 1624 #define CFG_73_PVR_STATUS_PVR3_EVER_OVERFLOW_SHIFT 4 1625 #define CFG_73_PVR_STATUS_PVR3_STR2MI_INT_MASK 0x0006 1626 #define CFG_73_PVR_STATUS_PVR3_STR2MI_INT_SHIFT 5 1627 #define CFG_73_PVR_STATUS_PVR4_FIFO_MASK 0x000f 1628 #define CFG_73_PVR_STATUS_PVR4_FIFO_SHIFT 8 1629 #define CFG_73_PVR_STATUS_PVR4_EVER_OVERFLOW_MASK 0x0001 1630 #define CFG_73_PVR_STATUS_PVR4_EVER_OVERFLOW_SHIFT 12 1631 #define CFG_73_PVR_STATUS_PVR4_STR2MI_INT_MASK 0x0006 1632 #define CFG_73_PVR_STATUS_PVR4_STR2MI_INT_SHIFT 13 1633 REG16 CFG_74; 1634 #define CFG_74_MATCHECED_APID_C_MASK 0x1fff 1635 #define CFG_74_CHANGE_APID_C 0x4000 1636 REG16 CFG_75; 1637 #define CFG_75_FI_MOBF_INDEC_TSIF1_MASK 0x0000001F 1638 REG16 CFG_76; 1639 #define CFG_76_FI_MOBF_INDEC_TSIF2_MASK 0x0000001F 1640 REG16 CFG_77; 1641 #define CFG_77_FI_MOBF_INDEC_TSIF3_MASK 0x0000001F 1642 REG16 CFG_78_7B[4]; 1643 #define CFG_78_PVR3_INDEX 0x0000001F 1644 REG16 CFG_7C; 1645 #define CFG_7C_MATCHECED_APID_D_MASK 0x1fff 1646 #define CFG_7C_CHANGE_APID_D 0x4000 1647 } REG_Ctrl2; 1648 1649 //TSP 4 1650 typedef struct _REG_Ctrl3 1651 { 1652 REG16 CFG3_00_09[10]; // 0x00 ~ 0x09 1653 REG16 CFG3_0A; // 0x0A 1654 #define CFG3_0A_REG_PDFLT_BF0_CAVID 0x001F 1655 #define CFG3_0A_REG_PDFLT_BF1_CAVID 0x03E0 1656 #define CFG3_0A_REG_PDFLT_BF2_CAVID 0x7C00 1657 REG16 CFG3_0B; // 0x0B 1658 REG16 CFG3_0C; // 0x0C 1659 #define CFG3_0C_RBF0_PASS_MODE 0x0001 1660 #define CFG3_0C_RBF1_PASS_MODE 0x0002 1661 #define CFG3_0C_RBF2_PASS_MODE 0x0004 1662 #define CFG3_0C_RBF3_PASS_MODE 0x0008 1663 1664 #define CFG3_0C_PKTDMX_CC_DROP_MSAK 0x03C0 1665 #define CFG3_0C_PKTDMX_CC_DROP_SHIFT 0x0006 1666 #define CFG3_0C_PIDFLT0_DUP_CC_SKIP 0x0040 1667 #define CFG3_0C_PIDFLT1_DUP_CC_SKIP 0x0080 1668 #define CFG3_0C_PIDFLT2_DUP_CC_SKIP 0x0100 1669 #define CFG3_0C_PIDFLT3_DUP_CC_SKIP 0x0200 1670 1671 REG16 CFG3_0D; // 0x0D 1672 #define CFG3_0D_PIDFLT0_ADP_DUP_CC_SKIP 0x0001 1673 #define CFG3_0D_PIDFLT1_ADP_DUP_CC_SKIP 0x0002 1674 #define CFG3_0D_PIDFLT2_ADP_DUP_CC_SKIP 0x0004 1675 #define CFG3_0D_PIDFLT3_ADP_DUP_CC_SKIP 0x0008 1676 REG16 CFG3_0E; // 0x0E 1677 #define CFG3_0E_PDFBUF_FULL_SEL 0x0007 1678 #define CFG3_0E_PKT_MERGE_TIMESTAMP_SRC_SEL 0x01F8 //reg_pkt_merge_timestamp_src_sel=> 1679 #define CFG3_0E_PIDBUF0_TIMESTAMP_27M 0x0008 //pdflt buffer 0 timestamp sel 1: 27m 0: 90k 1680 #define CFG3_0E_PIDBUF1_TIMESTAMP_27M 0x0010 //pdflt buffer 1 timestamp sel 1: 27m 0: 90k 1681 #define CFG3_0E_PIDBUF2_TIMESTAMP_27M 0x0020 //pdflt buffer 2 timestamp sel 1: 27m 0: 90k 1682 #define CFG3_0E_PIDBUF3_TIMESTAMP_27M 0x0040 //pdflt buffer 3 timestamp sel 1: 27m 0: 90k 1683 #define CFG3_0E_STREAM2MIU1_C27M 0x0200 //reg_stream2miu1_c90k_sel=>Stream2miu1 timestamp sel 1: 27m 0: 90k 1684 #define CFG3_0E_STREAM2MIU2_C27M 0x0400 //reg_stream2miu2_c90k_sel=>Stream2miu2 timestamp sel 1: 27m 0: 90k 1685 #define CFG3_0E_STREAM2MIU3_C27M 0x0800 //reg_stream2miu3_c90k_sel=>Stream2miu3 timestamp sel 1: 27m 0: 90k 1686 #define CFG3_0E_STREAM2MIU4_C27M 0x1000 //reg_stream2miu4_c90k_sel=>Stream2miu4 timestamp sel 1: 27m 0: 90k 1687 REG16 CFG3_0F; // 0x0F 1688 #define CFG3_0F_TSIF0_C27M 0x0001 //reg_tsif0_c90k_sel=>Tsif0 timestamp sel 1: 27m 0: 90k 1689 #define CFG3_0F_TSIF1_C27M 0x0002 //reg_tsif1_c90k_sel=>Tsif1 timestamp sel 1: 27m 0: 90k 1690 #define CFG3_0F_TSIF2_C27M 0x0004 //reg_tsif2_c90k_sel=>Tsif2 timestamp sel 1: 27m 0: 90k 1691 #define CFG3_0F_TSIF3_C27M 0x0008 //reg_tsif3_c90k_sel=>Tsif3 timestamp sel 1: 27m 0: 90k 1692 REG16 CFG3_10; // 0x10 1693 #define CFG3_10_TSO0_SRC 0x0007 //reg_tso0_src 1694 #define CFG3_10_TSO0_SRC_SHIFT 0 1695 #define CFG3_10_TSO0_SRC_PKTDMX0 0x0001 1696 #define CFG3_10_TSO0_SRC_PKTDMX1 0x0002 1697 #define CFG3_10_TSO0_SRC_PKTDMX2 0x0004 1698 #define CFG3_10_TSO1_SRC 0x0038 //reg_tso1_src 1699 #define CFG3_10_TSO1_SRC_SHIFT 3 1700 #define CFG3_10_TSO1_SRC_PKTDMX0 0x0001 1701 #define CFG3_10_TSO1_SRC_PKTDMX1 0x0002 1702 #define CFG3_10_TSO1_SRC_PKTDMX2 0x0004 1703 #define CFG3_10_TSO0_BLOCK_DIS 0x1000 //reg_tso0_block_dis 1704 #define CFG3_10_TSO1_BLOCK_DIS 0x2000 //reg_tso1_block_dis 1705 #define CFG3_10_PS_MODE_SRC_MASK 0x01C0 1706 #define CFG3_10_PS_MODE_SRC_SHIFT 6 1707 1708 REG16 CFG3_11; // 0x11 1709 REG32 CFG3_12_13; // reg_dmaw_lbnd4 1710 REG32 CFG3_14_15; //reg_dmaw_ubnd4 1711 REG16 CFG3_16; // 0x16 1712 #define CFG3_16_FIXED_DMA_RSTART_OTP_ONEWAY_LOAD_FW 0x8000 1713 REG16 CFG3_17; // 0x17 1714 #define CFG3_17_INIT_TIMESTAMP_TSIF_0 0x0040 1715 #define CFG3_17_INIT_TIMESTAMP_TSIF_1 0x0080 1716 #define CFG3_17_INIT_TIMESTAMP_TSIF_2 0x0100 1717 #define CFG3_17_INIT_TIMESTAMP_TSIF_3 0x0200 1718 REG16 CFG3_18_1D[6]; // 0x18 ~ 0x1D 1719 REG16 CFG3_1E; // 0X1E 1720 #define CFG3_1E_TSIF0_SPD_RESET 0x0001 //Tsif0 SPD rest 1721 #define CFG3_1E_TSIF1_SPD_RESET 0x0002 //Tsif1 SPD rest 1722 #define CFG3_1E_TSIF2_SPD_RESET 0x0004 //Tsif2 SPD rest 1723 #define CFG3_1E_TSIF3_SPD_RESET 0x0008 //Tsif3 SPD rest 1724 REG16 CFG3_1F; // 0x1F 1725 REG16 CFG3_20; // 0x20 1726 #define CFG3_20_PIDFLT0_CLR_REPLACE_EN_MASK 0x000F //reg_pdflt0_clear_replace_en=>clear pdflt 0 cc replace function flag 1727 #define CFG3_20_PIDFLT1_CLR_REPLACE_EN_MASK 0x00F0 //reg_pdflt1_clear_replace_en=>clear pdflt 0 cc replace function flag 1728 #define CFG3_20_PIDFLT2_CLR_REPLACE_EN_MASK 0x0F00 //reg_pdflt2_clear_replace_en=>clear pdflt 0 cc replace function flag 1729 #define CFG3_20_PIDFLT3_CLR_REPLACE_EN_MASK 0xF000 //reg_pdflt3_clear_replace_en=>clear pdflt 0 cc replace function flag 1730 REG16 CFG3_21; // 0x21 1731 #define CFG3_21_TSIF0_FILE_PAUSE 0x0100 // Set 1 to inform TSIF(file-in engine) back-end pipe is full 1732 #define CFG3_21_TSIF1_FILE_PAUSE 0x0200 // and don't transmit data 1733 #define CFG3_21_TSIF2_FILE_PAUSE 0x0400 1734 #define CFG3_21_TSIF3_FILE_PAUSE 0x0800 1735 REG16 CFG3_22; 1736 #define CFG3_22_PVR1_PKT_MEET_SIZE_L_MASK 0xFFFF //PVR1 callback PKT Meet Size 1737 REG16 CFG3_23; 1738 #define CFG3_23_PVR1_PKT_MEET_SIZE_H_MASK 0x00FF 1739 #define CFG3_23_PVR1_STR2MI_CNT_CLR 0x0100 1740 #define CFG3_23_PVR1_STR2MI_CNT_INTMODE 0x0200 1741 #define CFG3_23_PVR1_STR2MI_SYNC_INTMODE 0x0400 1742 REG16 CFG3_24; 1743 #define CFG3_24_PVR2_PKT_MEET_SIZE_L_MASK 0xFFFF //PVR2 callback PKT Meet Size 1744 REG16 CFG3_25; 1745 #define CFG3_25_PVR2_PKT_MEET_SIZE_H_MASK 0x00FF 1746 #define CFG3_25_PVR2_STR2MI_CNT_CLR 0x0100 1747 #define CFG3_25_PVR2_STR2MI_CNT_INTMODE 0x0200 1748 #define CFG3_25_PVR2_STR2MI_SYNC_INTMODE 0x0400 1749 REG16 CFG3_26; 1750 #define CFG3_26_PVR3_PKT_MEET_SIZE_L_MASK 0xFFFF //PVR3 callback PKT Meet Size 1751 REG16 CFG3_27; 1752 #define CFG3_27_PVR3_PKT_MEET_SIZE_H_MASK 0x00FF 1753 #define CFG3_27_PVR3_STR2MI_CNT_CLR 0x0100 1754 #define CFG3_27_PVR3_STR2MI_CNT_INTMODE 0x0200 1755 #define CFG3_27_PVR3_STR2MI_SYNC_INTMODE 0x0400 1756 REG16 CFG3_28_29[2]; // 0x28 ~ 0x29 1757 REG16 CFG3_2A; 1758 #define CFG3_2A_PKTDMX0_TRACE_MARK_V_EN 0x0001 1759 #define CFG3_2A_PKTDMX0_TRACE_MARK_V3D_EN 0x0002 1760 #define CFG3_2A_PKTDMX0_TRACE_MARK_A_EN 0x0004 1761 #define CFG3_2A_PKTDMX0_TRACE_MARK_AB_EN 0x0008 1762 #define CFG3_2A_PKTDMX1_TRACE_MARK_V_EN 0x0020 1763 #define CFG3_2A_PKTDMX1_TRACE_MARK_V3D_EN 0x0040 1764 #define CFG3_2A_PKTDMX1_TRACE_MARK_A_EN 0x0080 1765 #define CFG3_2A_PKTDMX1_TRACE_MARK_AB_EN 0x0100 1766 #define CFG3_2A_PKTDMX2_TRACE_MARK_V_EN 0x0400 1767 #define CFG3_2A_PKTDMX2_TRACE_MARK_V3D_EN 0x0800 1768 #define CFG3_2A_PKTDMX2_TRACE_MARK_A_EN 0x1000 1769 #define CFG3_2A_PKTDMX2_TRACE_MARK_AB_EN 0x2000 1770 REG16 CFG3_2B; 1771 #define CFG3_2B_PKTDMX3_TRACE_MARK_V_EN 0x0001 1772 #define CFG3_2B_PKTDMX3_TRACE_MARK_V3D_EN 0x0002 1773 #define CFG3_2B_PKTDMX3_TRACE_MARK_A_EN 0x0004 1774 #define CFG3_2B_PKTDMX3_TRACE_MARK_AB_EN 0x0008 1775 #define CFG3_2B_PKTDMX4_TRACE_MARK_V_EN 0x0020 1776 #define CFG3_2B_PKTDMX4_TRACE_MARK_V3D_EN 0x0040 1777 #define CFG3_2B_PKTDMX4_TRACE_MARK_A_EN 0x0080 1778 #define CFG3_2B_PKTDMX4_TRACE_MARK_AB_EN 0x0100 1779 REG16 CFG3_2C; 1780 #define CFG3_2C_PDFLT0_NDS_TEST_MODE 0x0001 1781 #define CFG3_2C_PDFLT1_NDS_TEST_MODE 0x0002 1782 #define CFG3_2C_PDFLT2_NDS_TEST_MODE 0x0004 1783 #define CFG3_2C_PDFLT3_NDS_TEST_MODE 0x0008 1784 #define CFG3_2C_AVFIFO_READ_SEL_MASK 0x01C0 1785 #define CFG3_2C_AVFIFO_READ_SEL_SHIFT 6 1786 #define CFG3_2C_AVFIFO_READ_SEL_V 0 1787 #define CFG3_2C_AVFIFO_READ_SEL_A 1 1788 #define CFG3_2C_AVFIFO_READ_SEL_AB 2 1789 #define CFG3_2C_AVFIFO_READ_SEL_V3D 3 1790 #define CFG3_2C_AVFIFO_READ_SEL_AC 4 1791 #define CFG3_2C_AVFIFO_READ_SEL_AD 5 1792 #define CFG3_2C_DEBUG_WR_SRC_SEL_MASK 0x0E00 1793 REG16 CFG3_2D; 1794 #define CFG3_2D_FIXED_RM_PINPONG_SYCN_IN_ECO 0x0001 // fixed_rm_pinpong_sycn_in_eco 1795 #define CFG3_2D_VPID_3D_BYPASS 0x0002 // reg_vpid_3d_bypass 1796 #define CFG3_2D_APID_B_BYPASS 0x0004 // reg_apid_b_bypass 1797 #define CFG3_2D_APID_C_BYPASS 0x0008 // reg_apid_b_bypass 1798 #define CFG3_2D_APID_D_BYPASS 0x0010 // reg_apid_b_bypass 1799 #define CFG3_2D_PKT_DEMUX0_TRACE_MARK_AD 0x0020 // reg_pkt_demux0_trace_mark_ad_en=>set 1 enable trace mark function in pktdemux0 audio d path 1800 #define CFG3_2D_PKT_DEMUX1_TRACE_MARK_AD 0x0040 // reg_pkt_demux1_trace_mark_ad_en=>set 1 enable trace mark function in pktdemux0 audio d path 1801 #define CFG3_2D_PKT_DEMUX2_TRACE_MARK_AD 0x0080 // reg_pkt_demux2_trace_mark_ad_en=>set 1 enable trace mark function in pktdemux0 audio d path 1802 #define CFG3_2D_PKT_DEMUX3_TRACE_MARK_AD 0x0100 // reg_pkt_demux3_trace_mark_ad_en=>set 1 enable trace mark function in pktdemux0 audio d path 1803 #define CFG3_2D_FILTER_NULL_PKT 0x0800 1804 REG16 CFG3_2E_30[3]; //reserved 1805 REG16 CFG3_31; // 0x31 1806 #define CFG3_31_PVR1_MEET_SIZE_CNT_R_MASK 0x00FF 1807 #define CFG3_31_PVR2_MEET_SIZE_CNT_R_MASK 0xFF00 1808 REG16 CFG3_32; // 0x32 1809 #define CFG3_31_PVR3_MEET_SIZE_CNT_R_MASK 0x00FF 1810 REG16 CFG3_33; 1811 #define TSP_AFIFOC_EMPTY 0x0002 1812 #define TSP_AFIFOC_EMPTY_SHFT 1 1813 #define TSP_AFIFOC_FULL 0x0004 1814 #define TSP_AFIFOC_FULL_SHFT 2 1815 #define TSP_AFIFOC_LEVEL 0x0018 1816 #define TSP_AFIFOC_LEVEL_SHFT 3 1817 #define TSP_AFIFOD_EMPTY 0x1000 1818 #define TSP_AFIFOD_EMPTY_SHFT 12 1819 #define TSP_AFIFOD_FULL 0x4000 1820 #define TSP_AFIFOD_FULL_SHFT 13 1821 #define TSP_AFIFOD_LEVEL 0xC000 1822 #define TSP_AFIFOD_LEVEL_SHFT 14 1823 REG16 CFG3_34; // 0x34 1824 #define CFG3_34_DUP_PKT_SKIP_V 0x0001 //reg_dup_pkt_skip_v 1825 #define CFG3_34_DUP_PKT_SKIP_V3D 0x0002 //reg_dup_pkt_skip_v3d 1826 #define CFG3_34_DUP_PKT_SKIP_A 0x0004 //reg_dup_pkt_skip_a 1827 #define CFG3_34_DUP_PKT_SKIP_AB 0x0008 //reg_dup_pkt_skip_ab 1828 #define CFG3_34_DUP_PKT_SKIP_AC 0x0010 //reg_dup_pkt_skip_ac 1829 #define CFG3_34_DUP_PKT_SKIP_AD 0x0020 //reg_dup_pkt_skip_ad 1830 #define CFG3_34_MASK_SRC_V_EN 0x0100 //mask_scr_vid_en 1831 #define CFG3_34_MASK_SRC_V3D_EN 0x0200 //mask_scr_v3d_en 1832 #define CFG3_34_MASK_SRC_A_EN 0x0400 //mask_scr_aud_en 1833 #define CFG3_34_MASK_SRC_AB_EN 0x0800 //mask_scr_aud_b_en 1834 #define CFG3_34_MASK_SRC_AC_EN 0x1000 //mask_scr_aud_c_en 1835 #define CFG3_34_MASK_SRC_AD_EN 0x2000 //mask_scr_aud_d_en 1836 #define CFG3_34_FIX_192_TIMER_0_EN 0x4000 //reg_fix_192_timer_0_en 1837 #define CFG3_34_TSP2MI_REQ_MCM_DISABLE 0x8000 //reg_tsp2mi_req_mcm_disable 1838 REG16 CFG3_35; // 0x35 1839 #define HW4_CFG35_BLK_AD_SCMBTIS_TSP 0x0001 1840 #define HW4_CFG35_PUSI_3BYTE_MODE 0x0002 1841 #define HW4_CFG35_PKT_MERGE_AUTO_RST 0x0004 1842 #define HW4_CFG35_AES_OUT_BT_ORDER 0x0008 1843 #define HW4_CFG35_AES_IN_BT_ORDER 0x0010 1844 #define HW4_CFG35_PREVENT_PID_TABLE_SRAM_COLLISION 0x0020 1845 #define HW4_CFG35_RW_CONDITION_0 0x0040 1846 #define HW4_CFG35_RW_CONDITION_1 0x0080 1847 #define HW4_CFG35_PUSI_UPDATE_SCMB_BIT 0x0100 1848 #define HW4_CFG35_BYPASS_TIMESTAMP_SEL1 0x0200 1849 #define HW4_CFG35_BYPASS_TIMESTAMP_SEL2 0x0400 1850 #define HW4_CFG35_BYPASS_TIMESTAMP_SEL3 0x0800 1851 #define HW4_CFG35_BYPASS_TIMESTAMP_SEL4 0x1000 1852 #define HW4_CFG35_CLR_SRAM_COLLISION 0x2000 1853 #define HW4_CFG35_PREVENT_SRAM_COLLISION 0x4000 1854 #define HW4_CFG35_BYPASS_FILEIN_TO_FIQ 0x8000 1855 REG16 CFG3_36; 1856 #define HW4_CFG36_PKT130_PSI_EN0 0x0001 //rvu setting 1857 #define HW4_CFG36_PKT130_TEI_EN0 0x0002 1858 #define HW4_CFG36_PKT130_ERR_CLR0 0x0004 1859 #define HW4_CFG36_PKT130_EN0 0x0008 1860 #define HW4_CFG36_PKT130_TIMESTAMP_EN0 0x0010 1861 #define HW4_CFG36_PKT130_PID_12_TIE_0_EN0 0x0020 1862 #define HW4_CFG36_PAYLOAD_128_MODE_EN0 0x0040 1863 #define HW4_CFG36_PKT130_PSI_EN1 0x0100 1864 #define HW4_CFG36_PKT130_TEI_EN1 0x0200 1865 #define HW4_CFG36_PKT130_ERR_CLR1 0x0400 1866 #define HW4_CFG36_PKT130_EN1 0x0800 1867 #define HW4_CFG36_PKT130_TIMESTAMP_EN1 0x1000 1868 #define HW4_CFG36_PKT130_PID_12_TIE_0_EN1 0x2000 1869 #define HW4_CFG36_PAYLOAD_128_MODE_EN1 0x4000 1870 REG16 CFG3_37; 1871 #define HW4_CFG37_3WIRE_SERIAL_MODE_TS0 0x0001 1872 #define HW4_CFG37_3WIRE_SERIAL_MODE_TS1 0x0002 1873 #define HW4_CFG37_3WIRE_SERIAL_MODE_TS2 0x0004 1874 #define HW4_CFG37_3WIRE_SERIAL_MODE_TS3 0x0008 1875 #define HW4_CFG37_NON_188_CNT_MODE 0x0100 1876 #define HW4_CFG37_MASK_SCR_PVR1_EN 0x0200 1877 #define HW4_CFG37_MASK_SCR_PVR2_EN 0x0400 1878 #define HW4_CFG37_MASK_SCR_PVR3_EN 0x0800 1879 #define HW4_CFG37_MASK_SCR_PVR4_EN 0x1000 1880 #define HW4_CFG37_RST_CC_MODE 0x2000 1881 #define HW4_CFG37_DIS_CNTR_INC_BY_PL 0x4000 // 1=without payload 0=with payload ??? 1882 REG16 CFG3_38; 1883 #define HW4_CFG38_LOAD_SPS_KEY1 0x0001 1884 #define HW4_CFG38_LOAD_SPS_KEY2 0x0002 1885 #define HW4_CFG38_LOAD_SPS_KEY3 0x0004 1886 #define HW4_CFG38_LOAD_SPS_KEY4 0x0008 1887 #define HW4_CFG38_PKT192_SPS_EN1 0x0010 1888 #define HW4_CFG38_PKT192_SPS_EN2 0x0020 1889 #define HW4_CFG38_PKT192_SPS_EN3 0x0040 1890 #define HW4_CFG38_PKT192_SPS_EN4 0x0080 1891 #define HW4_CFG38_CA_PVR1_SEL_MASK 0x0300 1892 #define HW4_CFG38_CA_PVR1_SEL_SHIFT 8 1893 #define HW4_CFG38_CA_PVR2_SEL_MASK 0x0C00 1894 #define HW4_CFG38_CA_PVR2_SEL_SHIFT 10 1895 #define HW4_CFG38_CA_PVR3_SEL_MASK 0x3000 1896 #define HW4_CFG38_CA_PVR3_SEL_SHIFT 12 1897 #define HW4_CFG38_CA_PVR4_SEL_MASK 0xC000 1898 #define HW4_CFG38_CA_PVR4_SEL_SHIFT 14 1899 REG16 CFG3_39; 1900 #define HW4_CFG39_FLUSH_PVR_DATA 0x0001 1901 #define HW4_CFG39_FLUSH_PVR1_DATA 0x0002 1902 #define HW4_CFG39_FLUSH_PVR2_DATA 0x0004 1903 #define HW4_CFG39_FLUSH_PVR3_DATA 0x0008 1904 REG16 CFG3_3A; 1905 #define HW4_CFG3A_LOAD_SPD_KEY0 0x0001 1906 #define HW4_CFG3A_LOAD_SPD_KEY1 0x0002 1907 #define HW4_CFG3A_LOAD_SPD_KEY2 0x0004 1908 #define HW4_CFG3A_LOAD_SPD_KEY3 0x0008 1909 #define HW4_CFG3A_LOAD_SPD_KEY4 0x0010 1910 #define HW4_CFG3A_LOAD_SPD_KEY5 0x0020 1911 REG16 CFG3_3B_3F[5]; 1912 REG16 CFG3_40; 1913 #define HW4_CFG40_HW_SEMAPHORE0_MASK 0xFFFF 1914 REG16 CFG3_41; 1915 #define HW4_CFG41_HW_SEMAPHORE1_MASK 0xFFFF 1916 REG16 CFG3_42; 1917 #define HW4_CFG42_HW_SEMAPHORE2_MASK 0xFFFF 1918 REG16 CFG3_43; 1919 #define HW4_CFG43_SRC_AES_PVR_KEY_MASK 0x0007 1920 #define HW4_CFG43_SRC_AES_PVR1_KEY 0x0000 1921 #define HW4_CFG43_SRC_AES_PVR2_KEY 0x0001 1922 #define HW4_CFG43_SRC_AES_PVR3_KEY 0x0002 1923 #define HW4_CFG43_SRC_AES_PVR4_KEY 0x0003 1924 #define HW4_CFG43_SRC_AES_FI_KEY_MASK 0x0038 1925 #define HW4_CFG43_SRC_AES_FI_KEY_SHIFT 3 1926 #define HW4_CFG43_SRC_AES_FI0_KEY 0x0000 1927 #define HW4_CFG43_SRC_AES_FI1_KEY 0x0001 1928 #define HW4_CFG43_SRC_AES_FI2_KEY 0x0002 1929 #define HW4_CFG43_SRC_AES_FI3_KEY 0x0003 1930 REG32 CFG3_44_45; //pause time0 for PVR1+ FIQ application 1931 REG32 CFG3_46_47; //pause time1 for PVR2+ FIQ application 1932 REG32 CFG3_48_49; //pause time2 for PVR3+ FIQ application 1933 REG32 CFG3_4A_4B; //pause time3 for PVR4+ FIQ application 1934 REG16 CFG3_4C_4F[4]; 1935 REG32 CFG3_50_51; 1936 REG16 CFG3_52; 1937 #define CFG3_52_SPD_TSIF0_BYPASS 0x0001 1938 #define CFG3_52_SPD_TSIF1_BYPASS 0x0002 1939 #define CFG3_52_SPD_TSIF2_BYPASS 0x0004 1940 #define CFG3_52_SPD_TSIF3_BYPASS 0x0008 1941 REG16 CFG3_53; 1942 #define CFG3_53_WB_FSM_REST 0x0001 1943 REG16 CFG3_54_57[4]; 1944 REG16 CFG3_58_5F[8]; 1945 REG16 CFG3_60_67[8]; //AES KEY PVR 1946 REG16 CFG3_68_6F[8]; //AES KEY FILEIN 1947 REG16 CFG3_70_71[2]; //BIST fail status 1948 REG16 CFG3_72; 1949 #define CFG3_72_PIDFLT_PCR_SCR_ID_MASK 0x00ff 1950 #define CFG3_72_PIDFLT_PCR0_SCR_ID_SHIFT 0 1951 #define CFG3_72_PIDFLT_PCR1_SCR_ID_SHIFT 8 1952 REG16 CFG3_73; 1953 #define CFG3_73_PVR1_DMAW_PROTECT_EN 0x0001 1954 #define CFG3_73_PVR2_DMAW_PROTECT_EN 0x0002 1955 #define CFG3_73_PVR3_DMAW_PROTECT_EN 0x0004 1956 #define CFG3_73_PVR4_DMAW_PROTECT_EN 0x0008 1957 #define CFG3_73_FILEIN0_DMAR_PROTECT_EN 0x0010 1958 #define CFG3_73_FILEIN1_DMAR_PROTECT_EN 0x0020 1959 #define CFG3_73_FILEIN2_DMAR_PROTECT_EN 0x0040 1960 #define CFG3_73_FILEIN3_DMAR_PROTECT_EN 0x0080 1961 #define CFG3_73_MMFI0_DMAR_PROTECT_EN 0x0400 1962 #define CFG3_73_MMFI1_DMAR_PROTECT_EN 0x0800 1963 #define CFG3_73_FILEIN0_ILLEGAL_ADDR_0 0x1000 1964 #define CFG3_73_FILEIN1_ILLEGAL_ADDR_0 0x2000 1965 #define CFG3_73_FILEIN2_ILLEGAL_ADDR_0 0x4000 1966 #define CFG3_73_FILEIN3_ILLEGAL_ADDR_0 0x8000 1967 REG16 CFG3_74; 1968 #define CFG3_74_MMFI0_ILLEGAL_ADDR_0 0x0004 1969 #define CFG3_74_MMFI1_ILLEGAL_ADDR_0 0x0008 1970 #define CFG3_74_FILEIN0_ILLEGAL_MIU_NS_EN 0x0010 1971 #define CFG3_74_FILEIN1_ILLEGAL_MIU_NS_EN 0x0020 1972 #define CFG3_74_FILEIN2_ILLEGAL_MIU_NS_EN 0x0040 1973 #define CFG3_74_FILEIN3_ILLEGAL_MIU_NS_EN 0x0080 1974 #define CFG3_74_MMFI0_ILLEGAL_MIU_NS_EN 0x0400 1975 #define CFG3_74_MMFI1_ILLEGAL_MIU_NS_EN 0x0800 1976 #define CFG3_74_DIS_FILEIN0_ADDR_LEN_BY_TEE 0x1000 1977 #define CFG3_74_DIS_FILEIN1_ADDR_LEN_BY_TEE 0x2000 1978 #define CFG3_74_DIS_FILEIN2_ADDR_LEN_BY_TEE 0x4000 1979 #define CFG3_74_DIS_FILEIN3_ADDR_LEN_BY_TEE 0x8000 1980 REG16 CFG3_75; 1981 #define CFG3_75_DIS_MMFI0_ADDR_LEN_BY_TEE 0x0004 1982 #define CFG3_75_DIS_MMFI1_ADDR_LEN_BY_TEE 0x0008 1983 } REG_Ctrl3; 1984 1985 //@TODO There is FIQ Bank in TSP6 bank 1986 //TSP 6 1987 typedef struct _REG_Ctrl4 1988 { 1989 REG16 CFG4_00_53[84]; 1990 REG16 CFG4_54; 1991 #define CFG4_54_RVU_PSI_EN2 0x0001 1992 #define CFG4_54_RVU_TEI_EN2 0x0002 1993 #define CFG4_54_RVU_ERR_CLR2 0x0004 1994 #define CFG4_54_RVU_EN2 0x0008 1995 #define CFG4_54_RVU_TIMESTAMP_EN2 0x0010 1996 #define CFG4_54_RVU_PID_12_TIE_0_EN2 0x0020 1997 #define CFG4_54_PAYLOAD_128_MODE_EN2 0x0040 1998 1999 #define CFG4_54_RVU_PSI_EN3 0x0100 2000 #define CFG4_54_RVU_TEI_EN3 0x0200 2001 #define CFG4_54_RVU_ERR_CLR3 0x0400 2002 #define CFG4_54_RVU_EN3 0x0800 2003 #define CFG4_54_RVU_TIMESTAMP_EN3 0x1000 2004 #define CFG4_54_RVU_PID_12_TIE_0_EN3 0x2000 2005 #define CFG4_54_PAYLOAD_128_MODE_EN3 0x4000 2006 REG16 CFG4_55; 2007 #define CFG4_55_RVU_PSI_EN4 0x0001 2008 #define CFG4_55_RVU_TEI_EN4 0x0002 2009 #define CFG4_55_RVU_ERR_CLR4 0x0004 2010 #define CFG4_55_RVU_EN4 0x0008 2011 #define CFG4_55_RVU_TIMESTAMP_EN4 0x0010 2012 #define CFG4_55_RVU_PID_12_TIE_0_EN4 0x0020 2013 #define CFG4_55_PAYLOAD_128_MODE_EN4 0x0040 2014 }REG_Ctrl4; 2015 2016 //TSP 7 2017 typedef struct _REG_Ctrl5 2018 { 2019 REG16 CFG5_00; 2020 REG16 CFG5_01; 2021 REG16 CFG5_02; 2022 REG16 CFG5_03; 2023 REG16 CFG5_04; 2024 REG16 Drop_Dis_PKT_Cnt_0; 2025 REG16 Drop_Dis_PKT_Cnt_1; 2026 REG16 Drop_Dis_PKT_Cnt_2; 2027 REG16 Drop_Dis_PKT_Cnt_3; 2028 REG16 CFG5_09; 2029 REG16 CFG5_0A; 2030 REG16 CFG5_0B; 2031 REG16 CFG5_0C; 2032 REG16 Locked_PKT_Cnt; //0x0D : reg_locked_pkt_cnt 2033 REG16 Av_PKT_Cnt; //0x0E : aud_pkt /vid_pkt 2034 REG16 CFG5_0F_16[8]; 2035 REG16 Av_PKT_Cnt1; //0x17 : aud_b_pkt /vid_3d_pkt 2036 REG16 CFG5_18; 2037 REG16 Err_PKT_Cnt; //0x19 : reg_err_pkt_cnt 2038 REG16 CFG5_1A_1C[3]; 2039 REG16 Input_PKT_Cnt; //0x1D : reg_input_pkt_cnt 2040 REG16 CFG5_1E_6F[82]; 2041 REG16 CFG5_70; 2042 #define CFG5_70_ERR_PKT_SRC_SEL_SHIFT 0 2043 #define CFG5_70_ERR_PKT_SRC_SEL_MASK 0x0007 2044 #define CFG5_70_INPUT_PKT_SRC_SEL_SHIT 3 2045 #define CFG5_70_INPUT_PKT_SRC_SEL_MASK 0x0038 2046 REG16 CFG5_71; 2047 #define CFG5_71_ERR_PKT_CNT_0_LOAD 0x0001 2048 #define CFG5_71_ERR_PKT_CNT_1_LOAD 0x0002 2049 #define CFG5_71_ERR_PKT_CNT_2_LOAD 0x0004 2050 #define CFG5_71_ERR_PKT_CNT_3_LOAD 0x0008 2051 #define CFG5_71_INPUT_PKT_CNT_0_LOAD 0x0100 2052 #define CFG5_71_INPUT_PKT_CNT_1_LOAD 0x0200 2053 #define CFG5_71_INPUT_PKT_CNT_2_LOAD 0x0400 2054 #define CFG5_71_INPUT_PKT_CNT_3_LOAD 0x0800 2055 REG16 CFG5_72; 2056 #define CFG5_72_ERR_PKT_CNT_0_CLR 0x0001 2057 #define CFG5_72_ERR_PKT_CNT_1_CLR 0x0002 2058 #define CFG5_72_ERR_PKT_CNT_2_CLR 0x0004 2059 #define CFG5_72_ERR_PKT_CNT_3_CLR 0x0008 2060 #define CFG5_72_INPUT_PKT_CNT_0_CLR 0x0100 2061 #define CFG5_72_INPUT_PKT_CNT_1_CLR 0x0200 2062 #define CFG5_72_INPUT_PKT_CNT_2_CLR 0x0400 2063 #define CFG5_72_INPUT_PKT_CNT_3_CLR 0x0800 2064 REG16 CFG5_73; 2065 REG16 CFG5_74; 2066 REG16 CFG5_75; 2067 REG16 CFG5_76; 2068 REG16 CFG5_77; 2069 #define CFG5_77_PIDFLT_SRC_SEL2_SHIFT 0 //pkt dmx 2 2070 #define CFG5_77_PIDFLT_SRC_SEL2_MASK 0x0007 2071 #define CFG5_77_PIDFLT_SRC_SEL3_SHIFT 3 //pkt dmx 3 2072 #define CFG5_77_PIDFLT_SRC_SEL3_MASK 0x0038 2073 REG16 CFG5_78; 2074 #define CFG5_78_AUDC_SRC_MASK 0x0007 2075 #define CFG5_78_AUDC_SRC_SHIFT 0 2076 #define CFG5_78_AUDD_SRC_MASK 0x0038 2077 #define CFG5_78_AUDD_SRC_SHIFT 3 2078 2079 #define CFG5_78_PIDFLT_SRC_SEL_MMFI0_SHIFT 6 // MMFI0 2080 #define CFG5_78_PIDFLT_SRC_SEL_MMFI0_MASK 0x01C0 2081 #define CFG5_78_PIDFLT_SRC_SEL_MMFI1_SHIFT 9 // MMFI1 2082 #define CFG5_78_PIDFLT_SRC_SEL_MMFI1_MASK 0x0E00 2083 REG16 CFG5_79; 2084 REG16 CFG5_7A; 2085 #define CFG5_7A_LOCKED_PKT_CNT_0_LOAD 0x0001 2086 #define CFG5_7A_LOCKED_PKT_CNT_1_LOAD 0x0002 2087 #define CFG5_7A_LOCKED_PKT_CNT_2_LOAD 0x0004 2088 #define CFG5_7A_LOCKED_PKT_CNT_3_LOAD 0x0008 2089 #define CFG5_7A_A_PKT_CNT_LOAD 0x0100 2090 #define CFG5_7A_V_PKT_CNT_LOAD 0x0200 2091 #define CFG5_7A_AD_PKT_CNT_LOAD 0x0400 2092 #define CFG5_7A_V3D_PKT_CNT_LOAD 0x0800 2093 #define CFG5_7A_ADC_PKT_CNT_LOAD 0x1000 2094 #define CFG5_7A_ADD_PKT_CNT_LOAD 0x2000 2095 REG16 CFG5_7B; 2096 #define CFG5_7B_DROP_PKT_CNT_V_LOAD 0x0001 2097 #define CFG5_7B_DROP_PKT_CNT_V3D_LOAD 0x0002 2098 #define CFG5_7B_DROP_PKT_CNT_A_LOAD 0x0004 2099 #define CFG5_7B_DROP_PKT_CNT_AD_LOAD 0x0008 2100 #define CFG5_7B_DROP_PKT_CNT_ADC_LOAD 0x0010 2101 #define CFG5_7B_DROP_PKT_CNT_ADD_LOAD 0x0020 2102 #define CFG5_7B_DIS_PKT_CNT_V_LOAD 0x0100 2103 #define CFG5_7B_DIS_PKT_CNT_V3D_LOAD 0x0200 2104 #define CFG5_7B_DIS_PKT_CNT_A_LOAD 0x0400 2105 #define CFG5_7B_DIS_PKT_CNT_AD_LOAD 0x0800 2106 #define CFG5_7B_DIS_PKT_CNT_ADC_LOAD 0x1000 2107 #define CFG5_7B_DIS_PKT_CNT_ADD_LOAD 0x2000 2108 REG16 CFG5_7C; 2109 #define CFG5_7C_LOCKED_PKT_CNT_0_CLR 0x0001 2110 #define CFG5_7C_LOCKED_PKT_CNT_1_CLR 0x0002 2111 #define CFG5_7C_LOCKED_PKT_CNT_2_CLR 0x0004 2112 #define CFG5_7C_LOCKED_PKT_CNT_3_CLR 0x0008 2113 #define CFG5_7C_A_PKT_CNT_CLR 0x0100 2114 #define CFG5_7C_V_PKT_CNT_CLR 0x0200 2115 #define CFG5_7C_AD_PKT_CNT_CLR 0x0400 2116 #define CFG5_7C_V3D_PKT_CNT_CLR 0x0800 2117 #define CFG5_7C_ADC_PKT_CNT_CLR 0x1000 2118 #define CFG5_7C_ADD_PKT_CNT_CLR 0x2000 2119 REG16 CFG5_7D; 2120 #define CFG5_7D_DROP_PKT_CNT_V_CLR 0x0001 2121 #define CFG5_7D_DROP_PKT_CNT_V3D_CLR 0x0002 2122 #define CFG5_7D_DROP_PKT_CNT_A_CLR 0x0004 2123 #define CFG5_7D_DROP_PKT_CNT_AD_CLR 0x0008 2124 #define CFG5_7D_DROP_PKT_CNT_ADC_CLR 0x0010 2125 #define CFG5_7D_DROP_PKT_CNT_ADD_CLR 0x0020 2126 #define CFG5_7D_DIS_PKT_CNT_V_CLR 0x0100 2127 #define CFG5_7D_DIS_PKT_CNT_V3D_CLR 0x0200 2128 #define CFG5_7D_DIS_PKT_CNT_A_CLR 0x0400 2129 #define CFG5_7D_DIS_PKT_CNT_AD_CLR 0x0800 2130 #define CFG5_7D_DIS_PKT_CNT_ADC_CLR 0x1000 2131 #define CFG5_7D_DIS_PKT_CNT_ADD_CLR 0x2000 2132 REG16 CFG5_7E; 2133 #define CFG5_7E_AUDA_SRC_MASK 0x0007 2134 #define CFG5_7E_AUDA_SRC_SHIFT 0 2135 #define CFG5_7E_VID_SRC_MASK 0x0038 2136 #define CFG5_7E_VID_SRC_SHIFT 3 2137 #define CFG5_7E_AUDB_SRC_MASK 0x01C0 2138 #define CFG5_7E_AUDB_SRC_SHIFT 6 2139 #define CFG5_7E_VID_3D_SRC_MASK 0x1E00 2140 #define CFG5_7E_VID_3D_SRC_SHIFT 9 2141 #define AV_PKT_SRC_PKTDMX0 0x0000 2142 #define AV_PKT_SRC_PKTDMX1 0x0001 2143 #define AV_PKT_SRC_PKTDMX2 0x0002 2144 #define AV_PKT_SRC_PKTDMX3 0x0003 2145 #define AV_PKT_SRC_PKTDMX4 0x0004 2146 #define AV_PKT_SRC_PKTDMX5 0x0005 2147 #define AV_PKT_SRC_MMFI0 0x0006 2148 #define AV_PKT_SRC_MMFI1 0x0007 2149 2150 REG16 CFG5_7F; 2151 #define CFG5_7F_DROP_PKT_MODE 0x0002 //choose the source of the reg_pkt_cnt 0: dis_cont_pkt 1: drop_pkt_cnt 2152 #define CFG5_7F_PIDFLT_SRC_SEL_SHIFT 2 //pkt dmx 0 2153 #define CFG5_7F_PIDFLT_SRC_SEL_MASK 0x001C 2154 #define CFG5_7F_TSIF_SRC_SEL_SHIFT 5 2155 #define CFG5_7F_TSIF_SRC_SEL_MASK 0x00E0 2156 #define TSIF_SRC_SEL_TSIF0 0x000 2157 #define TSIF_SRC_SEL_TSIF1 0x001 2158 #define TSIF_SRC_SEL_TSIF2 0x002 2159 #define TSIF_SRC_SEL_TSIF3 0x003 2160 2161 #define CFG5_7F_AV_PKT_SRC_SEL 0x0100 //choose the source of the Av_PKT_Cnt 0 : vid_pkt_cnt/vid_3d_pkt_cnt 1 : aud_pkt_cnt/aud_b_pkt_cnt 2162 #define CFG5_7F_CLR_SRC_SHIFT 9 2163 #define CFG5_7F_CLR_SRC_MASK 0x0E00 2164 #define CFG5_7F_CLR_SRC_PKTDMX0 0x0000 2165 #define CFG5_7F_CLR_SRC_PKTDMX1 0x0001 2166 #define CFG5_7F_CLR_SRC_PKTDMX2 0x0002 2167 #define CFG5_7F_CLR_SRC_PKTDMX3 0x0003 2168 #define CFG5_7F_CLR_SRC_PKTDMX4 0x0004 2169 #define CFG5_7F_CLR_SRC_PKTDMX5 0x0005 2170 #define CFG5_7F_CLR_SRC_MMFI0 0x0006 2171 #define CFG5_7F_CLR_SRC_MMFI1 0x0007 2172 2173 #define CFG5_7F_PIDFLT_SRC_SEL1_SHIFT 13 //pkt dmx 1 2174 #define CFG5_7F_PIDFLT_SRC_SEL1_MASK 0xE000 2175 #define DIS_DROP_CNT_V 0 2176 #define DIS_DROP_CNT_V3D 1 2177 #define DIS_DROP_CNT_A 2 2178 #define DIS_DROP_CNT_AD 3 2179 #define DIS_DROP_CNT_ADC 4 2180 #define DIS_DROP_CNT_ADD 5 2181 2182 } REG_Ctrl5; 2183 2184 //TSP 8 2185 typedef struct _REG_Ctrl6 2186 { 2187 REG16 SyncByte_tsif0[4]; //0x00~0x03 2188 #define TSP_SYNC_BYTE_MAASK0 0x00FF //byte 0 2189 #define TSP_SYNC_BYTE_MAASK1 0xFF00 //byte 1 2190 #define TSP_SYNC_BYTE_SHIFT0 0 2191 #define TSP_SYNC_BYTE_SHIFT1 8 2192 REG16 SourceId_tsif0[2]; //0x04~0x05 2193 #define TSP_SRCID_MASK0 0x000F //soruce 0 2194 #define TSP_SRCID_MASK1 0x00F0 //soruce 1 2195 #define TSP_SRCID_MASK2 0x0F00 //soruce 2 2196 #define TSP_SRCID_MASK3 0xF000 //soruce 3 2197 #define TSP_SRCID_SHIFT0 0 2198 #define TSP_SRCID_SHIFT1 4 2199 #define TSP_SRCID_SHIFT2 8 2200 #define TSP_SRCID_SHIFT3 12 2201 REG16 SyncByte_tsif1[4]; //0x06~0x09 2202 REG16 SourceId_tsif1[2]; //0x0a~0x0b 2203 REG16 SyncByte_tsif2[4]; //0x0c~0x0f 2204 REG16 SourceId_tsif2[2]; //0x10~0x11 2205 REG16 SyncByte_tsif3[4]; //0x12~0x15 2206 REG16 SourceId_tsif3[2]; //0x16~0x17 2207 REG16 CFG6_18_23[12]; //0x18~0x23 2208 REG16 pkt_converter[4]; //0x24~0x27 2209 #define TSP_PKT_CONVERTER_MODE_MASK 0x0007 2210 #define TSP_PKT_188Mode 0 2211 #define TSP_PKT_CIMode 1 2212 #define TSP_PKT_OpenCableMode 2 2213 #define TSP_PKT_ATSMode 3 2214 #define TSP_PKT_MxLMode 4 2215 #define TSP_PKT_FORCE_SYNC_47 0x0008 2216 #define TSP_BYPASS_PKT_CONVERTER 0x0010 2217 #define TSP_BYPASS_SRC_ID_PARSER 0x0020 2218 #define TSP_SRC_ID_FLT_EN 0x0040 2219 #define TSP_MXL_PKT_HEADER_MASK 0x0F80 //add pkt num 2220 #define TSP_MXL_PKT_HEADER_SHIFT 7 2221 REG16 CFG6_28_29[2]; 2222 REG16 CFG6_2A; 2223 #define CLR_PKT_CONVERTER_OVERFLOW 0x0001 2224 #define TSP_TSIF0_TSO_BLK_EN 0x0002 2225 #define TSP_TSIF0_TS1_BLK_EN 0x0004 2226 #define TSP_TSIF0_TS2_BLK_EN 0x0008 2227 #define TSP_TSIF0_TS3_BLK_EN 0x0010 2228 #define FIXED_TIMESTAMP_RING_BACK_EN 0x0080 2229 #define FIXED_LPCR_RING_BACK_EN 0x0400 2230 #define FIXED_VQ_MIU_REG_FLUSH 0x2000 2231 REG16 CFG6_2B; 2232 #define TSP_RESET_WB_DMA_FSM_TSIF1 0x0001 2233 #define TSP_RESET_WB_DMA_FSM_TSIF2 0x0002 2234 #define TSP_RESET_WB_DMA_FSM_TSIF3 0x0004 2235 #define TSP_RESET_WB_DMA_FSM_TSIF4 0x0008 2236 REG16 CFG6_2C_2F[4]; 2237 REG32 CFG6_30_31; // filein0 lower DMA read bound 2238 REG32 CFG6_32_33; // filein0 upper DMA read bound 2239 REG32 CFG6_34_35; // filein1 lower DMA read bound 2240 REG32 CFG6_36_37; // filein1 upper DMA read bound 2241 REG32 CFG6_38_39; // filein2 lower DMA read bound 2242 REG32 CFG6_3A_3B; // filein2 upper DMA read bound 2243 REG32 CFG6_3C_3D; // filein3 lower DMA read bound 2244 REG32 CFG6_3E_3F; // filein3 upper DMA read bound 2245 #define TSP_FILEIN_DMAR_BND_MASK 0x0FFFFFFFUL 2246 REG16 CFG6_40_47[8]; // @Not used 2247 REG32 CFG6_48_49; // mmfi0 lower DMA read bound 2248 REG32 CFG6_4A_4B; // mmfi0 upper DMA read bound 2249 REG32 CFG6_4C_4D; // mmfi1 lower DMA read bound 2250 REG32 CFG6_4E_4F; // mmfi1 upper DMA read bound 2251 #define TSP_MMFI_DMAR_BND_MASK 0x0FFFFFFFUL 2252 REG32 CFG6_50_51; // initial packet timestamp value (tsif0) 2253 REG32 CFG6_52_53; // initial packet timestamp value (tsif1) 2254 REG32 CFG6_54_55; // initial packet timestamp value (tsif2) 2255 REG32 CFG6_56_57; // initial packet timestamp value (tsif3) 2256 REG16 CFG6_58_5B[4]; // @Not used 2257 REG32 CFG6_5C_5D; // initial packet timestamp value (mmfi0) 2258 REG32 CFG6_5E_5F; // initial packet timestamp value (mmfi1) 2259 } REG_Ctrl6; 2260 2261 //TSP9 2262 typedef struct _REG_Ctrl7 2263 { 2264 REG16 CFG7_00_03[4]; //SPD CTR mode counter IV 2265 REG16 CFG7_04; //SPD CTR mode IV MAX (FILEIN) 2266 #define CFG7_04_CTR_IV_SPD_MAX_1K 0x0001 2267 #define CFG7_04_CTR_IV_SPD_MAX_2K 0x0002 2268 #define CFG7_04_CTR_IV_SPD_MAX_4K 0x0004 2269 #define CFG7_04_CTR_IV_SPD_MAX_8K 0x0008 2270 #define CFG7_04_CTR_IV_SPD_MAX_16K 0x0010 2271 #define CFG7_04_CTR_IV_SPD_MAX_32K 0x0020 2272 #define CFG7_04_CTR_IV_SPD_MAX_64K 0x0040 2273 #define CFG7_04_CTR_IV_SPD_MAX_128K 0x0080 2274 REG16 CFG7_05; //SPD CTR mode control (FILEIN) 2275 #define CFG7_05_CTR_MODE_SPD_FILEIN 0x0001 2276 #define CFG7_05_UPDATE_CTR_MODE_CNT_IV_SPD_FILEIN 0x0002 2277 #define CFG7_05_LOAD_INIT_CNT_SPD 0x0004 2278 #define CFG7_05_SPD_ONEWAY 0x8000 2279 REG16 CFG7_06_0F[10]; 2280 } REG_Ctrl7; 2281 2282 //TSP10 2283 typedef struct _REG_Ctrl8 2284 { 2285 REG16 CFG8_00_03[4]; //SPS CTR mode counter IV 2286 REG16 CFG8_04; //SPS CTR mode IV MAX (PVR 1) 2287 #define CFG8_04_CTR_IV_SPS_MAX_1K 0x0001 2288 #define CFG8_04_CTR_IV_SPS_MAX_2K 0x0002 2289 #define CFG8_04_CTR_IV_SPS_MAX_4K 0x0004 2290 #define CFG8_04_CTR_IV_SPS_MAX_8K 0x0008 2291 #define CFG8_04_CTR_IV_SPS_MAX_16K 0x0010 2292 #define CFG8_04_CTR_IV_SPS_MAX_32K 0x0020 2293 #define CFG8_04_CTR_IV_SPS_MAX_64K 0x0040 2294 #define CFG8_04_CTR_IV_SPS_MAX_128K 0x0080 2295 REG16 CFG8_05; //SPS CTR mode control (PVR 1) 2296 #define CFG8_05_CTR_MODE_SPS_PVR1 0x0001 2297 #define CFG8_05_UPDATE_CTR_MODE_CNT_IV_SPS_PVR1 0x0002 2298 #define CFG8_05_LOAD_INIT_CNT_SPS1 0x0004 2299 #define CFG8_05_SPS_ONEWAY1 0x8000 2300 REG16 CFG8_06_0F[10]; 2301 } REG_Ctrl8; 2302 2303 2304 #endif 2305