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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regTSP.h 98 // Description: Transport Stream Processor (TSP) Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _TSP_REG_H_ 103 #define _TSP_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 #define TS_PACKET_SIZE 188 137 138 139 //-------------------------------------------------------------------------------------------------- 140 // Compliation Option 141 //-------------------------------------------------------------------------------------------------- 142 143 //[CMODEL][FWTSP] 144 // When enable, interrupt will not lost, CModel will block next packet 145 // and FwTSP will block until interrupt status is clear by MIPS. 146 // (For firmware and cmodel only) 147 #define TSP_DBG_SAFE_MODE_ENABLE 0 148 149 //------------------------------------------------------------------------------------------------- 150 // Harware Capability 151 //------------------------------------------------------------------------------------------------- 152 #define TSP_PIDFLT_NUM 64 153 #define TSP_PIDFLT_EXT_NUM 8 154 155 #define TSP_PVR_IF_NUM 2 156 #define TSP_MMFI0_FILTER_NUM 4 157 #define TSP_MMFI1_FILTER_NUM 4 158 #define TSP_IF_NUM 3 159 #define TSP_DEMOD_NUM 2 160 #define TSP_VFIFO_NUM 2 161 #define TSP_AFIFO_NUM 2 162 #define TSP_TS_PAD_NUM 3 // 3p 163 #define TSP_VQ_NUM 3 // VQ0, VQ_file, VQ1 164 #define TSP_VQ_PITCH 208 165 #define TSP_CA_ENGINE_NUM 2 166 #define TSP_CA_KEY_NUM 8 167 #define TSP_CA0_FLT_NUM 72 168 #define TSP_CA_FLT_NUM 72 169 #define TSP_MERGESTR_MUM 8 170 #define TSP_ENGINE_NUM 1 171 #define TSP_SECFLT_NUM 64 172 #define TSP_PCRFLT_NUM 1 173 #define TSP_STC_NUM 1 174 175 #ifdef HWPCR_ENABLE 176 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM+TSP_PIDFLT_EXT_NUM+TSP_PCRFLT_NUM) 177 #else 178 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM+TSP_PIDFLT_EXT_NUM) 179 #endif 180 181 #define TSP_SECBUF_NUM TSP_SECFLT_NUM 182 #define TSP_FILTER_DEPTH 16 183 184 #define TSP_WP_SET_NUM 4 185 186 #define DSCMB_FLT_START_ID 16 187 #define DSCMB_FLT_END_ID 31 188 #define DSCMB_FLT_NUM 16 189 190 #define DSCMB1_FLT_START_ID 32 191 #define DSCMB1_FLT_END_ID 47 192 #define DSCMB1_FLT_NUM 16 193 194 195 #define DSCMB_FLT_SHAREKEY_START_ID 48 196 #define DSCMB_FLT_SHAREKEY_END_ID 64 197 #define DSCMB_FLT_SHAREKEY_NUM 16 198 199 #define DSCMB_FLT_SHAREKEY1_START_ID 48 200 #define DSCMB_FLT_SHAREKEY1_END_ID 64 201 #define DSCMB_FLT_SHAREKEY1_NUM 16 202 203 204 #define TSP_NMATCH_FLTID 17 205 206 //PAD MUX definition 207 #define TSP_MUX_TS0 0 208 #define TSP_MUX_TS1 1 209 #define TSP_MUX_TS2 2 210 #define TSP_MUX_TSO 6 211 #define TSP_MUX_INDEMOD 7 212 #define TSP_MUX_TSCB 0xFF //not support 213 #define TSP_MUX_NONE 0xFF 214 215 //Clk source definition 216 #define TSP_CLK_DISABLE 0x01 217 #define TSP_CLK_INVERSE 0x02 218 #define TSP_CLK_TS0 0x00 219 #define TSP_CLK_TS1 0x04 220 #define TSP_CLK_TS2 0x08 221 #define TSP_CLK_TSOOUT 0x18 222 #define TSP_CLK_INDEMOD 0x1C 223 #define CLKGEN0_TSP_CLK_MASK 0x1C 224 #define TSP_CLK_TSCB 0xFF //not support 225 226 //PIDFLT1,2 source definition 227 #define TSP_PIDFLT1_USE_TSIF1 0 228 #define TSP_PIDFLT2_USE_TSIF2 1 229 #define TSP_PIDFLT1_USE_TSIF_MMFI0 2 230 #define TSP_PIDFLT2_USE_TSIF_MMFI1 3 231 232 233 #define TSP_FW_DEVICE_ID 0x67 234 235 #define STC_SYNTH_DEFAULT 0x28000000 236 237 #define DRAM_SIZE (0x20000000) 238 #define TSP_FW_BUF_SIZE (0x4000UL) 239 #define TSP_FW_BUF_LOW_BUD 0 240 #define TSP_FW_BUF_UP_BUD DRAM_SIZE 241 242 #define TSP_VQ_BUF_LOW_BUD 0 243 #define TSP_VQ_BUF_UP_BUD DRAM_SIZE 244 245 #define TSP_SEC_BUF_LOW_BUD 0 246 #define TSP_SEC_BUF_UP_BUD DRAM_SIZE 247 #define TSP_SEC_FLT_DEPTH 32 248 #define TSP_FIQ_NUM 0 249 250 //QMEM definition 251 #define _TSP_QMEM_I_MASK 0xffff8000 //total: 0x4000 252 #define _TSP_QMEM_I_ADDR_HIT 0x00000000 253 #define _TSP_QMEM_I_ADDR_MISS 0xffffffff 254 #define _TSP_QMEM_D_MASK 0xffff8000 255 #define _TSP_QMEM_D_ADDR_HIT 0x00000000 256 #define _TSP_QMEM_D_ADDR_MISS 0xffffffff 257 #define _TSP_QMEM_SIZE 0x1000 // 16K bytes, 32bit aligment //0x4000 258 259 //------------------------------------------------------------------------------------------------- 260 // Type and Structure 261 //------------------------------------------------------------------------------------------------- 262 263 // Software 264 #define REG_PIDFLT_L_BASE (0x00210000 << 1) // Fit the size of REG32, 0~63 265 #define REG_PIDFLT_H_BASE (0x00210800 << 1) // Fit the size of REG32, 0~63 266 267 #define REG_SECFLT_BASE1 (0x00211000 << 1) // Fix the size of REG32 268 269 #define REG_CTRL_BASE (0x2A00) // 0xBF800000+(1500/2)*4 270 #define REG_CTRL_MMFIBASE (0x39C0) // 0xBF800000+(3800/2)*4 (TSP2: debug table), from 0x70 271 #define REG_CTRL_TSP3 (0xC1440) 272 #define REG_CTRL_TSP4 (0xC2E00) 273 #define REG_CTRL_TSP5 (0xC7600) 274 #define REG_CTRL_TS_SAMPLE (0x21600) 275 276 typedef struct _REG32 277 { 278 volatile MS_U16 L; 279 volatile MS_U16 empty_L; 280 volatile MS_U16 H; 281 volatile MS_U16 empty_H; 282 } REG32; 283 284 typedef struct _REG32_L 285 { 286 volatile MS_U32 data; 287 volatile MS_U32 _resv; 288 } REG32_L; 289 290 typedef struct _REG16 291 { 292 volatile MS_U16 u16data; 293 volatile MS_U16 _null; 294 } REG16; 295 296 typedef REG32 REG_PidFlt; 297 298 //******************** PIDFLT DEFINE START ********************// 299 // PID 300 #define TSP_PIDFLT_PID_MASK 0x00001FFF 301 #define TSP_PIDFLT_PID_SHFT 0 302 303 // PIDFLT SRC 304 #define TSP_PIDFLT_IN_MASK 0x0000E000 305 #define TSP_PIDFLT_IN_NONE 0x00000000 306 #define TSP_PIDFLT_IN_PIDFLT0 0x00002000 307 #define TSP_PIDFLT_IN_PIDFLT_FILE 0x00004000 308 #define TSP_PIDFLT_IN_PIDFLT1 0x00006000 309 #define TSP_PIDFLT_IN_PIDFLT2 0x00008000 310 #define TSP_PIDFLT_IN_PIDFLT_CB 0 //not support 311 #define TSP_PIDFLT_IN_SHIFT 13 312 313 // Section filter Id (0~64) 314 #define TSP_PIDFLT_SECFLT_MASK 0x000007f0 // [36:42] secflt id 315 #define TSP_PIDFLT_SECFLT_SHFT 4 316 317 // Stream source ID 318 #define TSP_PIDFLT_IN_SRC_MASK 0x0000000F // [35:32] stream source id 319 #define TSP_PIDFLT_IN_SRC_SHFT 0 320 321 // AF/Sec/Video/V3D/Audio/Audio-second/PVR1/PVR2 322 #define TSP_PIDFLT_OUT_MASK 0xFFE00000 323 #define TSP_PIDFLT_OUT_NONE 0x00000000 324 #define TSP_PIDFLT_OUT_AFIFO4 0x00200000 325 #define TSP_PIDFLT_OUT_AFIFO3 0x00400000 326 #define TSP_PIDFLT_OUT_SECFLT_AF 0x01000000 327 #define TSP_PIDFLT_OUT_SECFLT 0x02000000 328 #define TSP_PIDFLT_OUT_VFIFO 0x04000000 329 #define TSP_PIDFLT_OUT_VFIFO3D 0x08000000 330 #define TSP_PIDFLT_OUT_AFIFO 0x10000000 331 #define TSP_PIDFLT_OUT_AFIFO2 0x20000000 332 #define TSP_PIDFLT_OUT_PVR1 0x80000000 333 #define TSP_PIDFLT_OUT_PVR2 0x40000000 334 335 #define TSP_PIDFLT_SECFLT_NULL 0x3F // software usage clean selected section filter 336 //******************** PIDFLT DEFINE END ********************// 337 338 typedef struct _REG_SecFlt 339 { 340 REG32 Ctrl; 341 // SW flag 342 #define TSP_SECFLT_TYPE_MASK 0x01000007 343 #define TSP_SECFLT_TYPE_SHFT 0 344 #define TSP_SECFLT_TYPE_SEC 0x00000000 345 #define TSP_SECFLT_TYPE_PES 0x00000001 346 #define TSP_SECFLT_TYPE_PKT 0x00000002 347 #define TSP_SECFLT_TYPE_PCR 0x00000003 348 #define TSP_SECFLT_TYPE_TTX 0x00000004 349 #define TSP_SECFLT_TYPE_VER 0x00000005 350 #ifdef SEC_ADF_TYPE_SUPPORT 351 #define TSP_SECFLT_TYPE_ADF 0x00000006 //for af_descriptor 352 #endif 353 //#define TSP_SECFLT_TYPE_EMM 0x00000006 354 //#define TSP_SECFLT_TYPE_ECM 0x00000007 355 #define TSP_SECFLT_TYPE_SEC_NO_PUSI 0x01000000 356 357 358 #define TSP_SECFLT_PCRRST 0x00000010 // for TSP_SECFLT_TYPE_PCR 359 360 #define TSP_SECFLT_MODE_MASK 0x00000030 // software implementation 361 #define TSP_SECFLT_MODE_SHFT 4 362 #define TSP_SECFLT_MODE_CONTI 0x0 363 #define TSP_SECFLT_MODE_ONESHOT 0x1 364 #define TSP_SECFLT_MODE_CRCCHK 0x2 365 #define TSP_SECFLT_MODE_PESSCMCHK 0x3 //Only for PES type checking SCMB status 366 367 #define TSP_SECFLT_STATE_MASK 0x000000C0 // software implementation 368 #define TSP_SECFLT_STATE_SHFT 6 369 #define TSP_SECFLT_STATE_OVERFLOW 0x1 370 #define TSP_SECFLT_STATE_DISABLE 0x2 371 372 REG32 Match[TSP_FILTER_DEPTH/sizeof(MS_U32)]; 373 374 REG32 Mask[TSP_FILTER_DEPTH/sizeof(MS_U32)]; 375 376 REG32 BufStart; 377 #define TSP_SECFLT_BUFSTART_MASK 0xFFFFFFFF 378 379 REG32 BufEnd; 380 381 REG32 BufRead; 382 383 REG32 BufWrite; 384 385 REG32 BufCur; 386 387 REG32 RmnReqCnt; 388 #define TSP_SECFLT_OWNER_MASK 0x80000000 389 #define TSP_SECFLT_OWNER_SHFT 31 390 #define TSP_SECFLT_REQCNT_MASK 0x7FFF0000 391 #define TSP_SECFLT_REQCNT_SHFT 16 392 #define TSP_SECFLT_RMNCNT_MASK 0x0000FFFF 393 #define TSP_SECFLT_RMNCNT_SHFT 0 394 395 REG32 CRC32; 396 397 REG32 _x50[16]; // (0x210080-0x210050)/4 398 } REG_SecFlt; 399 400 401 typedef struct _REG_Stc 402 { 403 REG32 ML; 404 REG32_L H32; 405 } REG_Stc; 406 407 typedef struct _REG_Pid 408 { // Index(word) CPU(byte) Default 409 REG_PidFlt Flt[TSP_PIDFLT_NUM_ALL]; 410 } REG_Pid; 411 412 typedef struct _REG_Sec 413 { // Index(word) CPU(byte) Default 414 REG_SecFlt Flt[TSP_SECFLT_NUM]; 415 } REG_Sec; 416 417 typedef struct _REG_Ctrl 418 { 419 //---------------------------------------------- 420 // 0xBF802A00 MIPS direct access 421 //---------------------------------------------- 422 // Type Name Index(word) CPU(byte) MIPS(0x1500/2+index)*4 423 REG32 TsRec_Head20; // 0xbf802a00 0x00 424 #define TSP_HW_PVR_BUF_HEAD20_MASK 0xFFFF0000 425 #define TSP_HW_PVR_BUF_HEAD20_SHFT 16 426 427 REG32 TsRec_Head21_Mid20_Wptr; // 0xbf802a08 0x02 ,wptr & mid share same register 428 #define TSP_HW_PVR_BUF_HEAD21_MASK 0x000007FF 429 #define TSP_HW_PVR_BUF_HEAD21_SHFT 0 430 #define TSP_HW_PVR_BUF_MID20_MASK 0xFFFF0000 431 #define TSP_HW_PVR_BUF_MID20_SHFT 16 432 433 REG32 TsRec_Mid21_Tail20; // 0xbf802a10 0x04 434 #define TSP_HW_PVR_BUF_MID21_MASK 0x000007FF 435 #define TSP_HW_PVR_BUF_MID21_SHFT 0 436 #define TSP_HW_PVR_BUF_TAIL20_MASK 0xFFFF0000 437 #define TSP_HW_PVR_BUF_TAIL20_SHFT 16 438 439 REG32 TsRec_Tail2_Pcr1; // 0xbf802a18 0x06 440 #define TSP_HW_PVR_BUF_TAIL21_MASK 0x000007FF 441 #define TSP_HW_PVR_BUF_TAIL21_SHFT 0 // PCR64 L16 442 #define TSP_PCR64_L16_MASK 0xFFFF0000 443 #define TSP_PCR64_L16_SHFT 16 444 445 REG32 Pcr1; // 0xbf802a20 0x08 446 #define TSP_PCR64_MID32_MASK 0xFFFFFFFF // PCR64 Middle 64 447 #define TSP_PCR64_MID32_SHFT 0 448 449 REG32 Pcr64_H; // 0xbf802a28 0x0a 450 #define TSP_PCR64_H16_MASK 0x0000FFFF 451 #define TSP_PCR64_H16_SHFT 0 452 #define TSP_MOBF_FILE_INDEX_MASK 0x001F0000 // MOBF file index 453 #define TSP_MOBF_FILE_INDEX_SHIFT 16 454 455 REG16 _xbf202a30; // 0xbf802a30 0x0c 456 REG16 sw_mail_box0; // 0xbf802a34 0x0d 457 458 REG32 PVR2_Config; // 0xbf802a38 0x0e 459 #define TSP_PVR2_LPCR1_WLD 0x00000001 460 #define TSP_PVR2_LPCR1_RLD 0x00000002 461 #define TSP_PVR2_STR2MIU_DSWAP 0x00000004 462 #define TSP_PVR2_STR2MIU_EN 0x00000008 463 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010 464 #define TSP_PVR2_STR2MIU_BT_ORDER 0x00000020 465 #define TSP_PVR2_STR2MIU_PAUSE 0x00000040 466 #define TSP_PVR2_REG_PINGPONG_EN 0x00000080 467 #define TSP_PVR2_PVR_ALIGN_EN 0x00000100 468 #define TSP_PVR2_DMA_FLUSH_EN 0x00000200 469 #define TSP_PVR2_PKT192_EN 0x00000400 470 #define TSP_PVR2_BURST_LEN_MASK 0x00001800 471 #define TSP_PVR2_BURST_LEN_4 0x00000800 472 #define TSP_REC_DATA2_INV 0x00002000 473 #define TSP_V_BLOCK_DIS 0x00004000 474 #define TSP_V3D_BLOCK_DIS 0x00008000 475 #define TSP_AUD_BLOCK_DIS 0x00010000 476 #define TSP_AUDB_BLOCK_DIS 0x00020000 477 #define TSP_PVR1_BLOCK_DIS 0x00040000 478 #define TSP_PVR2_BLOCK_DIS 0x00080000 479 #define TSP_TSIF2_ENABLE 0x00100000 480 #define TSP_TSIF2_DATASWAP 0x00200000 481 #define TSP_TSIF2_SERL 0x00000000 482 #define TSP_TSIF2_PARL 0x00400000 483 #define TSP_TSIF2_EXTSYNC 0x00800000 484 #define TSP_TSIF2_BYPASS 0x01000000 485 #define TSP_TEI_SKIP_PKT2 0x02000000 486 #define TSP_CLR_LOCKED_PKT_CNT 0x20000000 487 #define TSP_CLR_AV_PKT_CNT 0x40000000 488 #define TSP_CLR_PVR_OVERFLOW 0x80000000 489 490 REG32 PVR2_LPCR1; // 0xbf802a40 0x10 491 492 #define TSP_STR2MI2_ADDR_MASK 0x07FFFFFF 493 REG32 Str2mi_head1_pvr2; // 0xbf802a48 0x12 494 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14 495 REG32 Str2mi_tail1_pvr2; // 0xbf802a58 0x16 496 REG32 Str2mi_head2_pvr2; // 0xbf802a60 0x18 497 REG32 Str2mi_mid2_pvr2; // 0xbf802a68 0x1a, PVR2 mid address & write point 498 REG32 Str2mi_tail2_pvr2; // 0xbf802a70 0x1c 499 REG32 _xbf802a70; // 0xbf802a78 0x1e 500 REG32 Pkt_CacheW0; // 0xbf802a80 0x20 501 502 REG32 Pkt_CacheW1; // 0xbf802a88 0x22 503 504 REG32 Pkt_CacheW2; // 0xbf802a90 0x24 505 506 REG32 Pkt_CacheW3; // 0xbf802a98 0x26 507 508 REG32_L Pkt_CacheIdx; // 0xbf802aa0 0x28 509 510 REG32 Pkt_DMA; // 0xbf802aa8 0x2a 511 #define TSP_SEC_DMAFIL_NUM_MASK 0x000000FF 512 #define TSP_SEC_DMAFIL_NUM_SHIFT 0 513 #define TSP_SEC_DMASRC_OFFSET_MASK 0x0000FF00 514 #define TSP_SEC_DMASRC_OFFSET_SHIFT 8 515 #define TSP_SEC_DMASRC_OFFSET_MASK 0x0000FF00 516 #define TSP_SEC_DMADES_LEN_MASK 0x00FF0000 517 #define TSP_SEC_DMADES_LEN_SHIFT 16 518 519 REG32 Hw_Config0; // 0xbf802ab0 0x2c 520 #define TSP_HW_CFG0_DATA_PORT_EN 0x00000001 521 #define TSP_HW_CFG0_TSIFO_SERL 0x00000000 522 #define TSP_HW_CFG0_TSIF0_PARL 0x00000002 523 #define TSP_HW_CFG0_TSIF0_EXTSYNC 0x00000004 524 #define TSP_HW_CFG0_TSIF0_TS_BYPASS 0x00000008 525 #define TSP_HW_CFG0_TSIF0_VPID_BYPASS 0x00000010 526 #define TSP_HW_CFG0_TSIF0_APID_BYPASS 0x00000020 527 #define TSP_HW_CFG0_WB_DMA_RESET 0x00000040 528 #define TSP_HW_CFG0_TSIF0_APID_B_BYPASS 0x00000080 529 #define TSP_HW_CFG0_PACKET_BUF_SIZE_MASK 0x0000FF00 530 #define TSP_HW_CFG0_PACKET_BUF_SIZE_SHIFT 8 531 #define TSP_HW_CFG0_PACKET_PIDFLT0_SIZE_MASK 0x00FF0000 532 #define TSP_HW_CFG0_PACKET_PIDFLT0_SIZE_SHIFT 16 533 #define TSP_HW_CFG0_PACKET_CHK_SIZE_MASK 0xFF000000 534 #define TSP_HW_CFG0_PACKET_CHK_SIZE_SHFT 24 535 536 REG32 TSP_DBG_PORT; // 0xbf802ab8 0x2e 537 #define TSP_DBG_FILTER_MATCH0_MASK 0x000000FF 538 #define TSP_DBG_FILTER_MATCH0_SHIFT 0 539 #define TSP_DBG_FILTER_MATCH1_MASK 0x0000FF00 540 #define TSP_DBG_FILTER_MATCH1_SHIFT 8 541 #define TSP_DNG_DATA_PORT_MASK 0x00FF0000 542 #define TSP_DNG_DATA_PORT_SHIFT 16 543 544 REG_Stc Pcr; // 0xbf802ac0 0x30 & 0x32 545 546 REG32 Pkt_Info; // 0xbf802ad0 0x34 547 #define TSP_APID_L_MASK 0x000000FF 548 #define TSP_APID_L_SHIFT 0 549 #define TSP_APID_H_MASK 0x00001F00 550 #define TSP_APID_H_SHIFT 8 551 #define TSP_PKT_PID_8_12_CP_MASK 0x001F0000 552 #define TSP_PKT_PID_8_12_CP_SHIFT 16 553 #define TSP_PKT_PRI_MASK 0x00200000 554 #define TSP_PKT_PRI_SHIFT 21 555 #define TSP_PKT_PLST_MASK 0x00400000 556 #define TSP_PKT_PLST_SHIFT 22 557 #define TSP_PKT_ERR 0x00800000 558 #define TSP_PKT_ERR_SHIFT 23 559 #define TSP_DMAW_NO_HIT_INT 0x0F000000 560 #define TSP_DMAW_NO_HIT_INT_SHIFT 24 561 562 REG32 Pkt_Info2; // 0xbf802ad8 0x36 563 #define TSP_PKT_INFO_CC_MASK 0x0000000F 564 #define TSP_PKT_INFO_CC_SHFT 0 565 #define TSP_PKT_INFO_ADPCNTL_MASK 0x00000030 566 #define TSP_PKT_INFO_ADPCNTL_SHFT 4 567 #define TSP_PKT_INFO_SCMB 0x000000C0 568 #define TSP_PKT_INFO_SCMB_SHFT 6 569 #define TSP_PKT_PID_0_7_CP_MASK 0x0000FF00 570 #define TSP_PKT_PID_0_7_CP_SHIFT 8 571 #define TSP_VFIFO3D_STATUS 0x000F0000 572 #define TSP_VFIFO3D_STATUS_SHFT 16 573 #define TSP_VFIFO_STATUS 0x00F00000 574 #define TSP_VFIFO_STATUS_SHFT 20 575 #define TSP_AFIFO_STATUS 0x0F000000 576 #define TSP_AFIFO_STATUS_SHFT 24 577 #define TSP_AFIFOB_STATUS 0xF0000000 578 #define TSP_AFIFOB_STATUS_SHFT 28 579 580 REG32 SwInt_Stat; // 0xbf802ae0 0x38 581 #define TSP_SWINT_INFO_SEC_MASK 0x000000FF 582 #define TSP_SWINT_INFO_SEC_SHFT 0 583 #define TSP_SWINT_INFO_ENG_MASK 0x0000FF00 584 #define TSP_SWINT_INFO_ENG_SHFT 8 585 #define TSP_SWINT_STATUS_CMD_MASK 0x7FFF0000 586 #define TSP_SWINT_STATUS_CMD_SHFT 16 587 #define TSP_SWINT_STATUS_SEC_RDY 0x0001 588 #define TSP_SWINT_STATUS_REQ_RDY 0x0002 589 #define TSP_SWINT_STATUS_BUF_OVFLOW 0x0006 590 #define TSP_SWINT_STATUS_SEC_CRCERR 0x0007 591 #define TSP_SWINT_STATUS_SEC_ERROR 0x0008 592 #define TSP_SWINT_STATUS_SYNC_LOST 0x0010 593 #define TSP_SWINT_STATUS_PKT_OVRUN 0x0020 594 #define TSP_SWINT_STATUS_DEBUG 0x0030 595 #define TSP_SWINT_CMD_DMA_PAUSE 0x0100 596 #define TSP_SWINT_CMD_DMA_RESUME 0x0200 597 #define TSP_SWINT_STATUS_SEC_GROUP 0x000F 598 #define TSP_SWINT_STATUS_GROUP 0x00FF 599 #define TSP_SWINT_CMD_GROUP 0x7F00 600 #define TSP_SWINT_CMD_STC_UPD 0x0400 601 #define TSP_SWINT_CTRL_FIRE 0x80000000 602 603 REG32 TsDma_Addr; // 0xbf802ae8 0x3a 604 605 REG32 TsDma_Size; // 0xbf802af0 0x3c 606 607 REG32 TsDma_Ctrl_CmdQ; // 0xbf802af8 0x3e 608 609 #define TSP_TSDMA_CTRL_VPES0 0x00000004 610 #define TSP_TSDMA_CTRL_APES0 0x00000008 611 #define TSP_TSDMA_CTRL_A2PES0 0x00000010 612 #define TSP_TSDMA_CTRL_V3DPES0 0x00000020 //not used 613 #define TSP_TSDMA_CTRL_A3PES0 0x00000040 //not used 614 #define TSP_TSDMA_CTRL_A4PES0 0x00000080 //not used 615 616 #define TSP_TSDMA_CTRL_START 0x00000001 617 #define TSP_TSDMA_CTRL_DONE 0x00000002 618 #define TSP_TSDMA_CTRL_INIT_TRUST 0x00000004 619 #define TSP_TSDMA_STAT_ABORT 0x00000080 620 #define TSP_CMDQ_CNT_MASK 0x001F0000 621 #define TSP_CMDQ_CNT_SHFT 16 622 #define TSP_CMDQ_FULL 0x00400000 623 #define TSP_CMDQ_EMPTY 0x00800000 624 #define TSP_CMDQ_SIZE 16 625 #define TSP_CMDQ_WR_LEVEL_MASK 0x03000000 626 #define TSP_CMDQ_WR_LEVEL_SHFT 24 627 628 REG32 MCU_Cmd; // 0xbf802b00 0x40 629 #define TSP_MCU_CMD_MASK 0xFF000000 630 #define TSP_MCU_CMD_NULL 0x00000000 631 #define TSP_MCU_CMD_ALIVE 0x01000000 632 #define TSP_MCU_CMD_NMATCH 0x02000000 633 #define TSP_MCU_CMD_NMATCH_FLT_MASK 0x000000FF 634 #define TSP_MCU_CMD_NMATCH_FLT_SHFT 0x00000000 635 #define TSP_MCU_CMD_PCR_GET 0x03000000 636 #define TSP_MCU_CMD_VER_RESET 0x04000000 637 #define TSP_MCU_CMD_VER_RESET_FLT_MASK 0x000000FF 638 #define TSP_MCU_CMD_VER_RESET_FLT_SHFT 0x00000000 639 #define TSP_MCU_CMD_MEM_HIGH_ADDR 0x05000000 640 #define TSP_MCU_CMD_MEM_LOW_ADDR 0x06000000 641 #define TSP_MCU_CMD_MEM_ADDR_SHFT 0x00000000 642 #define TSP_MCU_CMD_MEM_ADDR_MASK 0x0000FFFF 643 #define TSP_MCU_CMD_VERSION_GET 0x07000000 644 #define TSP_MCU_CMD_DBG_MEM 0x08000000 645 #define TSP_MCU_CMD_DBG_WORD 0x09000000 646 #define TSP_MCU_CMD_HWPCR_REG_SET 0x0A000000 647 #define TSP_MCU_CMD_SCMSTS_GET 0x0B000000 648 #define TSP_MCU_CMD_CTRL_STC_UPDATE 0x0C000000 649 #define TSP_MCU_CMD_CTRL_STC1_UPDATE 0x0D000000 650 #define TSP_MCU_CMD_CTRL_STC_UPDATE_OPTION_MASK 0x00FF0000 651 #define TSP_MCU_CMD_CTRL_STC_UPDATE_ONCE 0x00010000 652 #define TSP_MCU_CMD_TEI_COUNT_GET 0x0E000000 653 #define TSP_MCU_CMD_TEI_COUNT_SRC_MASK 0x0000FFFF 654 #define TSP_MCU_CMD_TEI_COUNT_SRC_LIVE 0x00000000 655 #define TSP_MCU_CMD_TEI_COUNT_SRC_FILE 0x00000001 656 #define TSP_MCU_CMD_TEI_COUNT_OPTION_MASK 0x00FF0000 657 #define TSP_MCU_CMD_TEI_COUNT_OPTION_RESET 0x00800000 658 #define TSP_MCU_CMD_DISCONT_COUNT_GET 0x0F000000 659 #define TSP_MCU_CMD_DISCONT_COUNT_FLT_MASK 0x0000FFFF 660 #define TSP_MCU_CMD_DISCONT_COUNT_OPTION_MASK 0x00FF0000 661 #define TSP_MCU_CMD_DISCONT_COUNT_OPTION_RESET 0x00800000 662 #define TSP_MCU_CMD_SET_STC_OFFSET 0x10000000 663 #define TSP_MCU_CMD_SET_STC_OFFSET_OPTION_MASK 0x00FF0000 664 #define TSP_MCU_CMD_SET_STC_OFFSET_OPTION_SHIFT 16 665 #define TSP_MCU_CMD_SEL_STC_ENG 0x20000000 666 #define TSP_MCU_SEL_STC_ENG_ID_MASK 0x000000FF 667 #define TSP_MCU_SEL_STC_ENG_ID_SHIFT 0 668 #define TSP_MCU_CMD_SEL_STC_ENG_FLTSRC_MASK 0x0000FF00 669 #define TSP_MCU_CMD_SEL_STC_ENG_FLTSRC_SHIFT 8 670 671 REG32 Hw_Config2; // 0xbf802b08 0x42 672 #define TSP_HW_CFG2_PACKET_CHK_SIZE1_MASK 0x000000FF 673 #define TSP_HW_CFG2_PACKET_CHK_SIZE1_SHFT 0 674 #define TSP_HW_CFG2_PACKET_SYNCBYTE1_MASK 0x0000FF00 675 #define TSP_HW_CFG2_PACKET_SYNCBYTE1_SHFT 8 676 #define TSP_HW_CFG2_PACKET_SIZE1_MASK 0x00FF0000 677 #define TSP_HW_CFG2_PACKET_SIZE1_SHFT 16 678 #define TSP_HW_CFG2_TSIF1_SERL 0x00000000 679 #define TSP_HW_CFG2_TSIF1_PARL 0x01000000 680 #define TSP_HW_CFG2_TSIF1_EXTSYNC 0x02000000 681 #define TSP_HW_CFG2_TS_DATAPORT_EN1 0x04000000 682 #define TSP_HW_CFG2_PIDFLT1_SOURCE_TSIF_MMFI0 0x20000000 // Switch source of PIDFLT1 to MMFI0 683 #define TSP_HW_CFG2_PIDFLT2_SOURCE_TSIF_MMFI1 0x40000000 // Switch source of PIDFLT2 to MMFI1 684 685 REG32 Hw_Config4; // 0xbf802b10 0x44 686 #define TSP_HW_CFG4_PVR_ENABLE 0x00000002 687 #define TSP_HW_CFG4_PVR_ENDIAN_BIG 0x00000004 // 1: record TS to MIU with big endian, 0: record TS to MIU with little endian 688 #define TSP_HW_CFG4_TSIF1_ENABLE 0x00000008 // 1: enable ts interface 1 and vice versa 689 #define TSP_HW_CFG4_PVR_FLUSH 0x00000010 // 1: str2mi_wadr <- str2mi_miu_head 690 #define TSP_HW_CFG4_PVRBUF_BYTEORDER_BIG 0x00000020 // Byte order of 8-byte recoding buffer to MIU. 691 #define TSP_HW_CFG4_PVR_PAUSE 0x00000040 692 #define TSP_HW_CFG4_MEMTSDATA_ENDIAN_BIG 0x00000080 // 32-bit data byte order read from 8x64 FIFO when playing file. 693 #define TSP_HW_CFG4_TSIF0_ENABLE 0x00000100 // 1: enable ts interface 0 and vice versa 694 #define TSP_VALID_FALLING_DETECT 0x00000200 // Reset bit count when data valid signal of TS interface is low. 695 #define TSP_SYNC_RISING_DETECT 0x00000400 // Reset bit count on the rising sync signal of TS interface. 696 #define TSP_HW_CFG4_TS_DATA0_SWAP 0x00000800 // Set 1 to swap the bit order of TS0 DATA bus 697 #define TSP_HW_CFG4_TS_DATA1_SWAP 0x00001000 // Set 1 to swap the bit order of TS1 DATA bus 698 #define TSP_HW_TSP2OUTAEON_INT_EN 0x00004000 // Set 1 to force interrupt to outside AEON 699 #define TSP_HW_HK_INT_FORCE 0x00008000 // Set 1 to force interrupt to HK_MCU 700 #define TSP_HW_CFG4_BYTE_ADDR_DMA 0x000F0000 // prevent from byte enable bug, bit1~3 must enable togather 701 #define TSP_HW_CFG4_ALT_TS_SIZE 0x00010000 // enable TS packets in 204 mode 702 #define TSP_HW_DMA_MODE_MASK 0x00300000 // Section filter DMA mode, 2'b00: Single.2'b01: Burst 2 bytes.2'b10: Burst 4 bytes.2'b11: Burst 8 bytes. 703 #define TSP_HW_DMA_MODE_SHIFT 20 704 #define TSP_HW_CFG4_WSTAT_CH_EN 0x00400000 705 #define TSP_HW_CFG4_PS_VID_EN 0x00800000 // program stream video enable 706 #define TSP_HW_CFG4_PS_AUD_EN 0x01000000 // program stream audio enable 707 #define TSP_HW_CFG4_PS_AUD2_EN 0x02000000 // program stream audioB enable 708 #define TSP_HW_CFG4_APES_ERR_RM_EN 0x04000000 // Set 1 to enable removing APES error packet 709 #define TSP_HW_CFG4_VPES_ERR_RM_EN 0x08000000 // Set 1 to enable removing VPES error packet 710 #define TSP_HW_CFG4_SEC_ERR_RM_EN 0x10000000 // Set 1 to enable removing section error packet 711 #define TSP_HW_CFG4_VID_ERR 0x20000000 // Set 1 to mask the error packet interrupt 712 #define TSP_HW_CFG4_AUD_ERR 0x40000000 // Set 1 to mask the error packet interrupt 713 #define TSP_HW_CFG4_ISYNC_PATCH_EN 0x80000000 // Set 1 to enable the patch of internal sync in "tsif" 714 715 REG32 NOEA_PC; // 0xbf802b18 0x46 716 717 REG32 Idr_Ctrl_Addr0; // 0xbf802b20 0x48 718 #define TSP_IDR_START 0x00000001 719 #define TSP_IDR_READ 0x00000000 720 #define TSP_IDR_WRITE 0x00000002 721 #define TSP_IDR_WR_ENDIAN_BIG 0x00000004 722 #define TSP_IDR_WR_ADDR_AUTO_INC 0x00000008 // Set 1 to enable address auto-increment after finishing read/write 723 #define TSP_IDR_WDAT0_TRIG_EN 0x00000010 // WDAT0_TRIG_EN 724 #define TSP_IDR_MCUWAIT 0x00000020 725 #define TSP_IDR_SOFT_RST 0x00000080 // Set 1 to soft-reset the IND32 module 726 #define TSP_IDR_AUTO_INC_VAL_MASK 0x00000F00 727 #define TSP_IDR_AUTO_INC_VAL_SHIFT 8 728 #define TSP_IDR_ADDR_MASK0 0xFFFF0000 729 #define TSP_IDR_ADDR_SHFT0 16 730 731 REG32 Idr_Addr1_Write0; // 0xbf802b28 0x4a 732 #define TSP_IDR_ADDR_MASK1 0x0000FFFF 733 #define TSP_IDR_ADDR_SHFT1 0 734 #define TSP_IDR_WRITE_MASK0 0xFFFF0000 735 #define TSP_IDR_WRITE_SHFT0 16 736 737 REG32 Idr_Write1_Read0; // 0xbf802b30 0x4c 738 #define TSP_IDR_WRITE_MASK1 0x0000FFFF 739 #define TSP_IDR_WRITE_SHFT1 0 740 #define TSP_IDR_READ_MASK0 0xFFFF0000 741 #define TSP_IDR_READ_SHFT0 16 742 743 REG32 Idr_Read1; // 0xbf802b38 0x4e 744 #define TSP_IDR_READ_MASK1 0x0000FFFF 745 #define TSP_IDR_READ_SHFT1 0 746 #define TSP_V3D_FIFO_DISCON 0x00100000 747 #define TSP_V3D_FIFO_OVERFLOW 0x00200000 748 #define TSP_VD_FIFO_DISCON 0x02000000 749 #define TSP_VD_FIFO_OVERFLOW 0x08000000 750 #define TSP_AUB_FIFO_OVERFLOW 0x10000000 751 #define TSP_AU_FIFO_OVERFLOW 0x20000000 752 753 // only 25 bits supported in PVR address. 8 bytes address 754 #define TSP_STR2MI2_ADDR_MASK 0x07FFFFFF 755 REG32 TsRec_Head; // 0xbf802b40 0x50 756 REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid address & write point 757 REG32 TsRec_Tail; // 0xbf802b50 0x54 758 759 REG16 sw_mail_b0x1; // 0xbf802b58 0x56 760 REG16 sw_mail_b0x2; // 0xbf802b5c 0x57 761 REG32 _xbf802b58; // 0xbf802b60 ~ 0xbf802b64 0x58~0x59 762 763 REG32 reg15b4; // 0xbf802b68 0x5a 764 #define TSP_SEC_CB_PVR2_DAMW_PROTECT_EN 0x00000002 765 #define TSP_PVR_PID_BYPASS 0x00000008 // Set 1 to bypass PID in record 766 #define TSP_PVR_PID_BYPASS2 0x00000010 // Set 1 to bypass PID in record2 767 #define TSP_BD_AUD_EN 0x00000020 // Set 1 to enable the BD audio stream recognization ( core /extend audio stream) 768 #define TSP_AVFIFO_RD_EN 0x00000080 // 0: AFIFO and VFIFO read are connected to MVD and MAD, 1: AFIFO and VFIFO read are controlled by registers (0x15B5[2:0]) 769 #define TSP_AVFIFO_RD 0x00000100 // If AVFIFO_RD_EN is 1, set to 1, then set to 0 would issue a read strobe to AFIFO or VFIFO 770 #define TSP_AVFIFO_SEL_VIDEO 0x00000000 771 #define TSP_AVFIFO_SEL_AUDIO 0x00000200 772 #define TSP_PVR_INVERT 0x00001000 // Set 1 to enable data payload invert for PVR record 773 #define TSP_PLY_FILE_INV_EN 0x00002000 // Set 1 to enable data payload invert in pidflt0 file path 774 #define TSP_PLY_TS_INV_EN 0x00004000 // Set 1 to enable data payload invert in pidflt0 TS path 775 #define TSP_FILEIN_BYTETIMER_ENABLE 0x00008000 // Set 1 to enable byte timer in ts_if0 TS path 776 #define TSP_PVR1_PINGPONG 0x00010000 // Set 1 to enable MIU addresses with pinpon mode 777 #define TSP_TEI_SKIPE_PKT_PID0 0x00040000 // Set 1 to skip error packets in pidflt0 TS path 778 #define TSP_TEI_SKIPE_PKT_FILE 0x00080000 // Set 1 to skip error packets in pidflt0 file path 779 #define TSP_TEI_SKIPE_PKT_PID1 0x00100000 // Set 1 to skip error packets in pidflt1 TS path 780 #define TSP_64bit_PCR2_ld 0x00800000 // Set 1 to load CNT_64B_2 (the second STC) 781 #define TSP_cnt_33b_ld 0x01000000 // Set 1 to load cnt_33b 782 #define TSP_FORCE_SYNCBYTE 0x02000000 // Set 1 to force sync byte (8'h47) in ts_if0 and ts_if1 path. 783 #define TSP_SERIAL_EXT_SYNC_LT 0x04000000 // Set 1 to detect serial-in sync without 8-cycle mode 784 #define TSP_BURST_LEN_MASK 0x18000000 // 00,01: burst length = 4; 10,11: burst length = 1 785 #define TSP_BURST_LEN_4 0x08000000 786 #define TSP_BURST_LEN_SHIFT 27 787 #define TSP_MATCH_PID_SRC_MASK 0x60000000 // Select the source of pid filter number with hit pid and match pid number with scramble information, 00 : from pkt_demux0, 01 : from pkt_demux_file, 10 : from pkt_demux1, 11 : from pkt_demux2 788 #define TSP_MATCH_PID_SRC_SHIFT 29 789 #define TSP_MATCH_PID_SRC_PKTDMX0 0 790 #define TSP_MATCH_PID_SRC_PKTDMXFL 1 791 #define TSP_MATCH_PID_SRC_PKTDMX1 2 792 #define TSP_MATCH_PID_LD 0x80000000 // Set 1 to load match pid number with scramble information from FILE PIDFLT 793 794 REG32 TSP_MATCH_PID_NUM; // 0xbf802b70 0x5c 795 796 REG32 TSP_IWB_WAIT; // 0xbf802b78 0x5e // Wait count settings for IWB when TSP CPU i-cache is enabled. 797 798 REG32 Cpu_Base; // 0xbf802b80 0x60 799 #define TSP_CPU_BASE_ADDR_MASK 0x01FFFFFF 800 801 REG32 Qmem_Ibase; // 0xbf802b88 0x62 802 803 REG32 Qmem_Imask; // 0xbf802b90 0x64 804 805 REG32 Qmem_Dbase; // 0xbf802b98 0x66 806 807 REG32 Qmem_Dmask; // 0xbf802ba0 0x68 808 809 REG32 TSP_Debug; // 0xbf802ba8 0x6a 810 #define TSP_DEBUG_MASK 0x00FFFFFF 811 812 REG32 _xbf802bb0; // 0xbf802bb0 0x6c 813 814 REG32 TsFileIn_RPtr; // 0xbf802bb8 0x6e 815 816 REG32 TsFileIn_Timer; // 0xbf802bc0 0x70 817 #define TSP_FILE_TIMER_MASK 0x00FFFFFF 818 REG32 TsFileIn_Head; // 0xbf802bc8 0x72 819 #define TSP_FILE_ADDR_MASK 0x07FFFFFF 820 REG32 TsFileIn_Mid; // 0xbf802bd0 0x74 821 822 REG32 TsFileIn_Tail; // 0xbf802bd8 0x76 823 824 REG32 Dnld_Ctrl; // 0xbf802be0 0x78 825 #define TSP_DNLD_ADDR_MASK 0x0000FFFF 826 #define TSP_DNLD_ADDR_SHFT 0 827 #define TSP_DNLD_ADDR_ALI_SHIFT 4 // Bit [11:4] of DMA_RADDR[19:0] 828 #define TSP_DNLD_NUM_MASK 0xFFFF0000 829 #define TSP_DNLD_NUM_SHFT 16 830 831 REG32 TSP_Ctrl; // 0xbf802be8 0x7a 832 #define TSP_CTRL_CPU_EN 0x00000001 833 #define TSP_CTRL_SW_RST 0x00000002 834 #define TSP_CTRL_DNLD_START 0x00000004 835 #define TSP_CTRL_DNLD_DONE 0x00000008 // See 0x78 for related information 836 #define TSP_CTRL_TSFILE_EN 0x00000010 837 #define TSP_CTRL_R_PRIO 0x00000020 838 #define TSP_CTRL_W_PRIO 0x00000040 839 #define TSP_CTRL_ICACHE_EN 0x00000100 840 #define TSP_CTRL_CPU2MI_R_PRIO 0x00000400 841 #define TSP_CTRL_CPU2MI_W_PRIO 0x00000800 842 #define TSP_CTRL_I_EL 0x00000000 843 #define TSP_CTRL_I_BL 0x00001000 844 #define TSP_CTRL_D_EL 0x00000000 845 #define TSP_CTRL_D_BL 0x00002000 846 #define TSP_CTRL_NOEA_QMEM_ACK_DIS 0x00004000 847 #define TSP_CTRL_MEM_TS_WORDER 0x00008000 848 #define TSP_SYNC_BYTE_MASK 0x00FF0000 849 #define TSP_SYNC_BYTE_SHIFT 16 850 851 REG32 PKT_CNT; // 0xbf802bf0 0x7c 852 #define TSP_PKT_CNT_MASK 0x000000FF 853 #define TSP_DBG_SEL_MASK 0xFFFF0000 854 #define TSP_DBG_SEL_SHIFT 16 855 856 REG16 HwInt_Stat; // 0xbf802bf8 0x7e 857 #define TSP_HWINT_STATUS_MASK 0xFF00 // Tsp2hk_int enable bits. 858 #define TSP_HWINT_TSP_PVR_TAIL0_STATUS 0x0100 859 #define TSP_HWINT_TSP_PVR_MID0_STATUS 0x0200 860 #define TSP_HWINT_TSP_HK_INT_FORCE_STATUS 0x0400 861 #define TSP_HWINT_TSP_FILEIN_MID_INT_STATUS 0x0800 862 #define TSP_HWINT_TSP_FILEIN_TAIL_INT_STATUS 0x1000 863 #define TSP_HWINT_TSP_SW_INT_STATUS 0x2000 864 #define TSP_HWINT_TSP_DMA_READ_DONE 0x4000 865 #define TSP_HWINT_TSP_AV_PKT_ERR 0x8000 866 867 #define TSP_HWINT_HW_PVR1_MASK (TSP_HWINT_TSP_PVR_TAIL0_STATUS | TSP_HWINT_TSP_PVR_MID0_STATUS) 868 #define TSP_HWINT_ALL (TSP_HWINT_HW_PVR1_MASK | TSP_HWINT_TSP_SW_INT_STATUS) 869 870 // 0x7f: TSP_CTRL1: hidden in HwInt_Stat 871 REG16 TSP_Ctrl1; // 0xbf802bfc 0x7f 872 #define TSP_CTRL1_FILEIN_TIMER_ENABLE 0x0001 873 #define TSP_CTRL1_TSP_FILE_NON_STOP 0x0002 //Set 1 to enable TSP file data read without timer check 874 #define TSP_CTRL1_FILEIN_PAUSE 0x0004 875 #define TSP_CTRL1_STANDBY 0x0080 876 #define TSP_CTRL1_INT2NOEA 0x0100 877 #define TSP_CTRL1_INT2NOEA_FORCE 0x0200 878 #define TSP_CTRL1_FORCE_XIU_WRDY 0x0400 879 #define TSP_CTRL1_CMDQ_RESET 0x0800 880 #define TSP_CTRL1_DLEND_EN 0x1000 // Set 1 to enable little-endian mode in TSP CPU 881 #define TSP_CTRL1_PVR_CMD_QUEUE_ENABLE 0x2000 882 #define TSP_CTRL1_DMA_RST 0x8000 883 884 //---------------------------------------------- 885 // 0xBF802C00 MIPS direct access 886 //---------------------------------------------- 887 REG32 MCU_Data0; // 0xbf802c00 0x00 888 #define TSP_MCU_DATA_ALIVE TSP_MCU_CMD_ALIVE 889 890 REG32 PVR1_LPcr1; // 0xbf802c08 0x02 891 892 REG32 LPcr2; // 0xbf802c10 0x04 893 894 REG32 reg160C; // 0xbf802c18 0x06 895 #define TSP_PVR1_LPCR1_WLD 0x00000001 // Set 1 to load LPCR1 value 896 #define TSP_PVR1_LPCR1_RLD 0x00000002 // Set 1 to read LPCR1 value (Default: 1) 897 #define TSP_LPCR2_WLD 0x00000004 // Set 1 to load LPCR2 value 898 #define TSP_LPCR2_RLD 0x00000008 // Set 1 to read LPCR2 value (Default: 1) 899 #define TSP_RECORD192_EN 0x00000010 // 160C bit(5)enable TS packets with 192 bytes on record mode 900 #define TSP_FILEIN192_EN 0x00000020 // 160C bit(5)enable TS packets with 192 bytes on file-in mode 901 #define TSP_RVU_TIMESTAMP_EN 0x00000040 902 #define TSP_ORZ_DMAW_PROT_EN 0x00000080 // 160C bit(7) open RISC DMA write protection 903 #define TSP_CLR_PIDFLT_BYTE_CNT 0x00000100 // Clear pidflt0_file byte counter 904 #define TSP_DOUBLE_BUF_DESC 0x00004000 // 160d bit(6) remove buffer limitation, Force pinpong buffer to flush 905 #define TSP_TIMESTAMP_RESET 0x00008000 // 160d bit(7) reset timestamp, reset all file in path 906 #define TSP_VQTX0_BLOCK_DIS 0x00010000 907 #define TSP_VQTX1_BLOCK_DIS 0x00020000 908 #define TSP_VQTX2_BLOCK_DIS 0x00040000 909 #define TSP_DIS_MIU_RQ 0x00100000 // Disable miu R/W request for reset TSP usage 910 #define TSP_RM_DMA_GLITCH 0x00800000 // Fix sec_dma overflow glitch 911 #define TSP_RESET_VFIFO 0x01000000 // Reset VFIFO -- ECO Done 912 #define TSP_RESET_AFIFO 0x02000000 // Reset AFIFO -- ECO Done 913 #define TSP_RESET_GDMA 0x04000000 // Set 1 to reset GDMA bridge 914 #define TSP_CLR_ALL_FLT_MATCH 0x08000000 // Set 1 to clean all flt_match in a packet 915 #define TSP_RESET_AFIFO2 0x10000000 916 #define TSP_RESET_VFIFO3D 0x20000000 917 #define TSP_PVR_WPRI_HIGH 0x20000000 918 #define TSP_OPT_ORACESS_TIMING 0x80000000 919 920 REG32 PktChkSizeFilein; // 0xbf802c20 0x08 921 #define TSP_PKT_SIZE_MASK 0x000000ff 922 #define TSP_PKT192_BLK_DIS_FIN 0x00000100 // Set 1 to disable file-in timestamp block scheme 923 #define TSP_AV_CLR 0x00000200 // Clear AV FIFO overflow flag and in/out counter 924 #define TSP_HW_STANDBY_MODE 0x00000400 // Set 1 to disable all SRAM in TSP for low power mode automatically 925 #define TSP_CNT_34B_DEFF_EN 0x00020000 // Switch STC DIFF Mode (Output STC+DIFF to MVD and MAD) 926 #define TSP_SYSTIME_MODE_STC64 0x00080000 // Switch normal STC or STC diff 927 #define TSP_SEC_DMA_BURST_EN 0x00800000 // ECO bit for section DMA burst mode 928 #define TSP_REMOVE_DUP_VIDEO_PKT 0x02000000 // Set 1 to remove duplicate video packet 929 #define TSP_REMOVE_DUP_VIDEO3D_PKT 0x04000000 // Set 1 to remove duplicate video 3D packet 930 #define TSP_REMOVE_DUP_AUDIO_PKT 0x08000000 // Set 1 to remove duplicate audio packet 931 #define TSP_REMOVE_DUP_AUDIOB_PKT 0x10000000 // Set 1 to remove duplicate audio description packet 932 933 #define TSP_REMOVE_DUP_AV_PKT (TSP_REMOVE_DUP_VIDEO_PKT|TSP_REMOVE_DUP_AUDIO_PKT|TSP_REMOVE_DUP_AUDIOB_PKT | TSP_REMOVE_DUP_VIDEO3D_PKT) 934 935 REG32 Dnld_Ctrl2; // 0xbf802c28 0x0a 936 #define TSP_DMA_RADDR_MSB_MASK 0x000000FF 937 #define TSP_DMA_RADDR_MSB_SHIFT 0 938 //#define TSP_CMQ_WORD_EN 0x00400000 // Set 1 to access CMDQ related registers in word. 939 //#define TSP_RESET_PVR_MOBF 0x04000000 940 //#define TSP_RESET_FILEIN_MOBF 0x08000000 941 #define TSP_TSIF0_VPID_3D_BYPASS 0x0F000000 // bypass TS for matched video 3D pid 942 #define TSP_VPID_3D_ERR_RM_EN 0x10000000 // enable removing v3d err pkt 943 #define TSP_PS_VID3D_EN 0x40000000 944 #define TSP_PREVENT_OVF_META 0x80000000 945 946 REG32 TsPidScmbStatTsin; // 0xbf802c30 0x0c 947 948 REG32 _xbf802c38; // 0xbf802c38 0x0e 949 950 REG32 PCR64_2_L; // 0xbf802c40 0x10 951 952 REG32 PCR64_2_H; // 0xbf802c48 0x12 953 954 #define TSP_DMAW_BND_MASK 0xFFFFFFFFF 955 REG32 DMAW_LBND0; // 0xbf802c50 0x14 956 957 REG32 DMAW_UBND0; // 0xbf802c58 0x16 958 959 REG32 DMAW_LBND1; // 0xbf802c60 0x18 960 961 REG32 DMAW_UBND1; // 0xbf802c68 0x1A 962 963 REG32 DMAW_ERR_WADDR_SRC_SEL; // 0x1C ~ 0x1D 964 #define TSP_CLR_NO_HIT_INT 0x00000001 // set 1 clear all dma write function not hit interrupt 965 #define DMAW_ERR_WADDR_SRC_SEL_MASK 0x0000001E 966 #define DMAW_ERR_WADDR_SRC_SEL_SHIFT 1 967 #define TSP_PVR1_DWMA_WADDR_ERR 0x0 968 #define TSP_SEC_DWMA_WADDR_ERR 0x1 969 #define TSP_PVR_CB_DWMA_WADDR_ERR 0x2 970 #define TSP_VQTX0_DWMA_WADDR_ERR 0x3 971 #define TSP_VQTX1_DWMA_WADDR_ERR 0x4 972 #define TSP_ORZ_DWMA_WADDR_ERR 0x5 973 #define TSP_VQTX2_DWMA_WADDR_ERR 0x6 974 #define TSP_PVR2_DWMA_WADDR_ERR 0x8 975 #define TSP_CLR_SEC_DMAW_OVERFLOW 0x00000040 976 #define TSP_APES_B_ERR_RM_EN 0x00000080 977 #define TSP_BLK_AF_SCRMB_BIT 0x00000400 978 979 REG32 reg163C; // 0xbf802c78 0x1e 980 981 #define TSP_CLR_SRC_MASK 0x00070000 982 #define TSP_CLR_SRC_SHIFT 16 983 #define TSP_CLR_SRC_CH_0 1 984 #define TSP_CLR_SRC_CH_FI 2 985 #define TSP_CLR_SRC_CH_1 3 986 #define TSP_CLR_SRC_CH_MMFI0 6 987 #define TSP_CLR_SRC_CH_MMFI1 7 988 #define TSP_DISCONTI_VD_CLR 0x00080000 //Set 1 to clear video discontinuity count 989 #define TSP_DISCONTI_AUD_CLR 0x00200000 //Set 1 to clear audio discontinuity count 990 #define TSP_DISCONTI_AUDB_CLR 0x00400000 //Set 1 to clear videoB discontinuity count 991 #define TSL_CLR_SRAM_COLLISION 0x02000000 992 #define TSP_TS_OUT_EN 0x04000000 //set 1 to enable ts_out 993 994 #define TSP_ALL_VALID_EN 0x08000000 995 #define TSP_PKT130_PUSI_EN 0x10000000 996 #define TSP_PKT130_TEI_EN 0x20000000 997 #define TSP_PKT130_ERR_CLR 0x40000000 998 #define TSP_PKT130_EN 0x80000000 // file in only 999 1000 REG32 VQ0_BASE; // 0xbf802c80 0x20 1001 REG32 VQ0_CTRL; // 0xbf802c88 0x22 1002 #define TSP_VQ0_SIZE_208PK_MASK 0x0000FFFF 1003 #define TSP_VQ0_SIZE_208PK_SHIFT 0 1004 #define TSP_VQ0_WR_THRESHOLD_MASK 0x000F0000 1005 #define TSP_VQ0_WR_THRESHOLD_SHIFT 16 1006 #define TSP_VQ0_PRIORTY_THRESHOLD_MASK 0x00F00000 1007 #define TSP_VQ0_PRIORTY_THRESHOL_SHIFT 20 1008 #define TSP_VQ0_FORCE_FIRE_CNT_1K_MASK 0x0F000000 1009 #define TSP_VQ0_FORCE_FIRE_CNT_1K_SHIFT 24 1010 #define TSP_VQ0_RESET 0x10000000 1011 #define TSP_VQ0_OVERFLOW_INT_EN 0x40000000 // Enable the interrupt for overflow happened on Virtual Queue path 1012 #define TSP_VQ0_CLR_OVERFLOW_INT 0x80000000 // Clear the interrupt and the overflow flag 1013 1014 REG32 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 1015 #define TSP_REQ_VQ_RX_THRESHOLD_MASKE 0x000E0000 1016 #define TSP_REQ_VQ_RX_THRESHOLD_SHIFT 17 1017 #define TSP_REQ_VQ_RX_THRESHOLD_LEN1 0x00000000 1018 #define TSP_REQ_VQ_RX_THRESHOLD_LEN2 0x00020000 1019 #define TSP_REQ_VQ_RX_THRESHOLD_LEN4 0x00040000 1020 #define TSP_REQ_VQ_RX_THRESHOLD_LEN8 0x00060000 1021 #define TSP_PIDFLT0_OVF_INT_EN 0x00400000 1022 #define TSP_PIDFLT0_CLR_OVF_INT 0x00800000 1023 #define TSP_PIDFLT0_FILE_OVF_INT_EN 0x01000000 1024 #define TSP_PIDFLT0_FILE_CLR_OVF_INT 0x02000000 1025 #define TSP_PIDFLT1_OVF_INT_EN 0x04000000 1026 #define TSP_PIDFLT1_CLR_OVF_INT 0x08000000 1027 #define TSP_PIDFLT2_OVF_INT_EN 0x10000000 1028 #define TSP_PIDFLT2_CLR_OVF_INT 0x20000000 1029 #define TSP_PIDFLT_CB_OVF_INT_EN 0x40000000 1030 #define TSP_PIDFLT_CB_CLR_OVF_INT 0x80000000 1031 1032 REG32 MOBF_PVR1_Index; // 0xbf3a2c98 0x26 1033 #define TSP_MOBF_PVR1_INDEX0_MASK 0x0000000F 1034 #define TSP_MOBF_PVR1_INDEX0_SHIFT 0 1035 #define TSP_MOBF_PVR1_INDEX1_MASK 0x000F0000 1036 #define TSP_MOBF_PVR1_INDEX1_SHIFT 16 1037 1038 REG32 MOBF_PVR2_Index; // 0xbf3a2cA0 0x28 1039 #define TSP_MOBF_PVR2_INDEX0_MASK 0x0000000F 1040 #define TSP_MOBF_PVR2_INDEX0_SHIFT 0 1041 #define TSP_MOBF_PVR2_INDEX1_MASK 0x000F0000 1042 #define TSP_MOBF_PVR2_INDEX1_SHIFT 16 1043 1044 REG32 DMAW_LBND2; // 0xbf802ca8 0x2a 1045 1046 REG32 DMAW_UBND2; // 0xbf802cb0 0x2c 1047 1048 REG32 DMAW_LBND3; // 0xbf802cb8 0x2e //reserved 1049 1050 REG32 DMAW_UBND3; // 0xbf802cc0 0x30 //reserved 1051 1052 REG32 DMAW_LBND4; // 0xbf802cc8 0x32 1053 1054 REG32 DMAW_UBND4; // 0xbf802cd0 0x34 1055 1056 REG32 ORZ_DMAW_LBND; // 0xbf802cd8 0x36 1057 #define TSP_ORZ_DMAW_LBND_MASK 0xffffffff 1058 REG32 ORZ_DMAW_UBND; // 0xbf802ce0 0x38 1059 #define TSP_ORZ_DMAW_UBND_MASK 0xffffffff 1060 REG32 _xbf802ce8_xbf802cec; // 0xbf802ce8_0xbf802cec 0x3a~0x3b 1061 1062 REG32 HWPCR0_L; // 0xbf802cf0 0x3c 1063 REG32 HWPCR0_H; // 0xbf802cf8 0x3e 1064 1065 REG32 CA_CTRL; // 0xbf802d00 0x40 1066 #define TSP_CA_CTRL_MASK 0xffffffff 1067 #define TSP_CA0_CTRL_MASK 0x00003077 1068 #define TSP_CA0_INPUT_TSIF0_LIVEIN 0x00000001 1069 #define TSP_CA0_INPUT_TSIF0_FILEIN 0x00000002 1070 #define TSP_CA0_INPUT_TSIF1 0x00000004 1071 #define TSP_CA0_OUTPUT_PKTDMX0_LIVE 0x00000010 1072 #define TSP_CA0_OUTPUT_PKTDMX0_FILE 0x00000020 1073 #define TSP_CA0_OUTPUT_PKTDMX1 0x00000040 1074 #define TSP_CA0_INPUT_TSIF2 0x00001000 1075 #define TSP_CA0_OUTPUT_PKTDMX2 0x00002000 1076 #define TSP_CA0_OUTPUT_CA2 0x00004000 1077 1078 #define TSP_CA1_CTRL_MASK 0x77308000 1079 #define TSP_CA1_OUTPUT_CA2 0x00008000 1080 #define TSP_CA1_INPUT_TSIF2 0x00100000 1081 #define TSP_CA1_OUTPUT_PKTDMX2 0x00200000 1082 1083 #define TSP_CA1_INPUT_TSIF0_LIVEIN 0x01000000 1084 #define TSP_CA1_INPUT_TSIF0_FILEIN 0x02000000 1085 #define TSP_CA1_INPUT_TSIF1 0x04000000 1086 #define TSP_CA1_OUTPUT_PKTDMX0_LIVE 0x10000000 1087 #define TSP_CA1_OUTPUT_PKTDMX0_FILE 0x20000000 1088 #define TSP_CA1_OUTPUT_PKTDMX1 0x40000000 1089 1090 REG32 REG_ONEWAY; // 0xbf802d08 0x42 1091 #define TSP_ONEWAY_REC_DISABLE 0x00000001 // Disable PVR 1092 #define TSP_ONEWAY_PVR_PORT 0x00000002 // Oneway for PVR buffer 1093 #define TSP_ONEWAY_LOAD_FW_PORT 0x00000004 // Oneway for f/w load address 1094 1095 REG32 HWPCR1_L; // 0xbf802d10 0x44 1096 REG32 HWPCR1_H; // 0xbf802d18 0x46 1097 1098 REG32 LPCR_CB; // 0xbf802d20 0x48 1099 1100 REG32 CHBW_BUF_HEAD; // 0xbf802d28 0x4a, channel browser 1101 1102 REG32 CHBW_BUF_MID_Wptr; // 0xbf802d30 0x4C, channel browser, Mid & Wptr share same register 1103 1104 REG32 CHBW_BUF_TAIL; // 0xbf802d38 0x4E, channel browser 1105 1106 REG32 FIFO_Src; // 0xbf802d40 0x50 1107 #define TSP_AUD_SRC_MASK 0x00000007 1108 #define TSP_AUD_SRC_SHIFT 0 1109 #define TSP_SRC_FROM_PKTDMX0 0x00000001 1110 #define TSP_SRC_FROM_PKTDMXFL 0x00000002 1111 #define TSP_SRC_FROM_PKTDMX1 0x00000003 1112 #define TSP_SRC_FROM_PKTDMX2 0x00000004 1113 #define TSP_SRC_FROM_MMFI0 0x00000006 1114 #define TSP_SRC_FROM_MMFI1 0x00000007 1115 #define TSP_AUDB_SRC_MASK 0x00000038 1116 #define TSP_AUDB_SRC_SHIFT 3 1117 #define TSP_VID_SRC_MASK 0x000001C0 1118 #define TSP_VID_SRC_SHIFT 6 1119 #define TSP_VID3D_SRC_MASK 0x00000E00 1120 #define TSP_VID3D_SRC_SHIFT 9 1121 #define TSP_PVR1_SRC_MASK 0x00007000 1122 #define TSP_PVR1_SRC_SHIFT 12 1123 #define TSP_PVR2_SRC_MASK 0x00038000 1124 #define TSP_PVR2_SRC_SHIFT 15 1125 #define TSP_PCR0_SRC_MASK 0x001C0000 1126 #define TSP_PCR0_SRC_SHIFT 18 1127 #define TSP_TEI_SKIP_PKT_PCR0 0x01000000 1128 #define TSP_PCR0_RESET 0x02000000 1129 #define TSP_PCR0_INT_CLR 0x04000000 1130 #define TSP_PCR0_READ 0x08000000 1131 1132 REG32 STC_DIFF_BUF; // 0xbf802d48 0x52 1133 1134 REG32 STC_DIFF_BUF_H; // 0xbf802d50 0x54 1135 #define TSP_STC_DIFF_BUF_H_MASK 0x0000007F 1136 #define TSP_STC_DIFF_BUF_H_AHIFT 0 1137 1138 REG32 VQ1_Base; // 0xbf802d58 0x56 1139 1140 REG32 Hw_Config5; // 0xbf802d60 0x58 1141 1142 REG32 CH_BW_CTRL; // 0xbf802d68 0x5a 1143 #define TSP_CH_BW_WP_LD 0x00000100 1144 1145 REG32 VQ1_Config; // 0xbf802d70 0x5C 1146 #define TSP_VQ1_SIZE_208BYTE_MASK 0x0000ffff 1147 #define TSP_VQ1_SIZE_208BYTE_SHIFT 0 1148 #define TSP_VQ1_WR_THRESHOLD_MASK 0x000F0000 1149 #define TSP_VQ1_WR_THRESHOLD_SHIFT 16 1150 #define TSP_VQ1_PRI_THRESHOLD_MASK 0x00F00000 1151 #define TSP_VQ1_PRI_THRESHOLD_SHIFT 20 1152 #define TSP_VQ1_FORCEFIRE_CNT_1K_MASK 0x0F000000 1153 #define TSP_VQ1_FORCEFIRE_CNT_1K_SHIFT 24 1154 #define TSP_VQ1_RESET 0x10000000 1155 #define TSP_VQ1_OVF_INT_EN 0x40000000 1156 #define TSP_VQ1_CLR_OVF_INT 0x80000000 1157 1158 REG32 VQ2_Base; // 0xbf802d78 0x5E 1159 1160 REG32 Pkt_Info3; // 0xbf802d80 0x60 1161 #define TSP_AFIFOC_STATUS 0x0000000F 1162 #define TSP_AFIFOC_STATUS_SHFT 0 1163 #define TSP_AFIFOD_STATUS 0x000000F0 1164 #define TSP_AFIFOD_STATUS_SHFT 4 1165 1166 REG32 Bist_Fail; // 0xbf802d88 0x62 1167 #define TSP_BIST_FAIL_STATUS_MASK 0x00FF0000 1168 #define TSP_BIST_FAIL_STATUS_SRAM1P192x8_MASK 0x00070000 1169 #define TSP_BIST_FAIL_STATUS_SRAM2P512x32w8 0x00080000 1170 #define TSP_BIST_FAIL_STATUS_SRAM2P16x128_MASK 0x00600000 1171 #define TSP_BIST_FAIL_STATUS_SRAM1P2048x32w8 0x00800000 1172 #define TSP_BIST_FAIL_STATUS_SRAM1P1024x32w8 0x01000000 1173 #define TSP_BIST_FAIL_STATUS_SRAM1P512x20 0x00200000 1174 1175 REG32 VQ2_Config; // 0xbf802d90 0x64 1176 #define TSP_VQ2_SIZE_208BYTE_MASK 0x0000ffff 1177 #define TSP_VQ2_SIZE_208BYTE_SHIFT 0 1178 #define TSP_VQ2_WR_THRESHOLD_MASK 0x000F0000 1179 #define TSP_VQ2_WR_THRESHOLD_SHIFT 16 1180 #define TSP_VQ2_PRI_THRESHOLD_MASK 0x00F00000 1181 #define TSP_VQ2_PRI_THRESHOLD_SHIFT 20 1182 #define TSP_VQ2_FORCEFIRE_CNT_1K_MASK 0x0F000000 1183 #define TSP_VQ2_FORCEFIRE_CNT_1K_SHIFT 24 1184 #define TSP_VQ2_RESET 0x10000000 1185 #define TSP_VQ2_OVF_INT_EN 0x40000000 1186 #define TSP_VQ2_CLR_OVF_INT 0x80000000 1187 1188 REG32 VQ_STATUS; // 0xbf802d98 0x66 1189 #define TSP_VQ_STATUS_MASK 0xFFFFFFFF 1190 #define TSP_VQ_STATUS_SHIFT 0 1191 #define TSP_VQ0_STATUS_READ_EVER_FULL 0x00001000 1192 #define TSP_VQ0_STATUS_READ_EVER_OVERFLOW 0x00002000 1193 #define TSP_VQ0_STATUS_EMPTY 0x00004000 1194 #define TSP_VQ0_STATUS_READ_BUSY 0x00008000 1195 #define TSP_VQ1_STATUS_READ_EVER_FULL 0x00010000 1196 #define TSP_VQ1_STATUS_READ_EVER_OVERFLOW 0x00020000 1197 #define TSP_VQ1_STATUS_EMPTY 0x00040000 1198 #define TSP_VQ1_STATUS_READ_BUSY 0x00080000 1199 #define TSP_VQ2_STATUS_READ_EVER_FULL 0x00100000 1200 #define TSP_VQ2_STATUS_READ_EVER_OVERFLOW 0x00200000 1201 #define TSP_VQ2_STATUS_EMPTY 0x00400000 1202 #define TSP_VQ2_STATUS_READ_BUSY 0x00800000 1203 #define TSP_VQ3_STATUS_READ_EVER_FULL 0x01000000 1204 #define TSP_VQ3_STATUS_READ_EVER_OVERFLOW 0x02000000 1205 #define TSP_VQ3_STATUS_EMPTY 0x04000000 1206 #define TSP_VQ3_STATUS_READ_BUSY 0x08000000 1207 #define TSP_VQ0_STATUS_TX_OVERFLOW 0x10000000 1208 #define TSP_VQ1_STATUS_TX_OVERFLOW 0x20000000 1209 #define TSP_VQ2_STATUS_TX_OVERFLOW 0x40000000 1210 #define TSP_VQ3_STATUS_TX_OVERFLOW 0x80000000 1211 1212 REG32 DM2MI_WAddr_Err; // 0xbf802da0 0x68 , DM2MI_WADDR_ERR0 1213 1214 REG32 ORZ_DMAW_WAddr_Err; // 0xbf802da8 0x6a , ORZ_WADDR_ERR0 1215 1216 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c 1217 #define TSP_HWINT2_EN_MASK 0x00FF 1218 #define TSP_HWINT2_EN_SHIFT 0 1219 #define TSP_HWINT2_STATUS_MASK 0xFF00 1220 #define TSP_HWINT2_STATUS_SHIFT 8 1221 #define TSP_HWINT2_PCR1_UPDATE_END 0x0400 1222 #define TSP_HWINT2_PCR0_UPDATE_END 0x0800 1223 #define TSP_HWINT2_PVRCB_MEET_MID_TAIL 0x1000 1224 #define TSP_HWINT2_ALL_DMA_WADDR_NOT_IN_PROCT_Z 0x2000 1225 #define TSP_HWINT2_VQ0_VQ1_VQ2_VQ3_OVERFLOW 0x4000 1226 #define TSP_HWINT2_PVR2_MID_TAIL_STATUS 0x8000 1227 1228 #define TSP_HWINT_HW_PVRCB_MASK TSP_HWINT2_PVRCB_MEET_MID_TAIL 1229 #define TSP_HWINT_HW_PVR2_MASK TSP_HWINT2_PVR2_MID_TAIL_STATUS 1230 #define TSP_HWINT2_ALL (TSP_HWINT_HW_PVRCB_MASK|TSP_HWINT_HW_PVR2_MASK|TSP_HWINT2_PCR0_UPDATE_END|TSP_HWINT2_PCR1_UPDATE_END) 1231 1232 #define TSP_SWINT1_L_SHFT 16 1233 #define TSP_SWINT1_L_MASK 0xFFFF0000 1234 1235 REG16 SwInt_Stat1_M; 1236 REG32 SwInt_Stat1_H; // 0xbf802dB8 0x6e 1237 #define TSP_SWINT1_H_SHFT 0 1238 #define TSP_SWINT1_H_MASK 0x0000FFFF 1239 1240 REG32 TimeStamp_FileIn; // 0xbf802dC0 0x70 1241 1242 REG32 HW2_Config3; // 0xbf802dC0 0x72 1243 #define TSP_WADDR_ERR_SRC_SEL_MASK 0x00000006 1244 #define TSP_WADDR_ERR_SRC_SEL_SHIFT 1 1245 #define TSP_WADDR_ERR_SRC_PVR 0x00000000 1246 #define TSP_WADDR_ERR_SRC_VQ 0x00000002 1247 #define TSP_WADDR_ERR_SRC_SEC_CB 0x00000004 1248 #define TSP_RM_OVF_GLITCH 0x00000008 1249 #define TSP_FILEIN_RADDR_READ 0x00000010 1250 #define TSP_DUP_PKT_CNT_CLR 0x00000040 1251 #define TSP_REC_AT_SYNC_DIS 0x00000100 1252 #define TSP_PVR1_ALIGN_EN 0x00000200 1253 #define TSP_REC_FORCE_SYNC_EN 0x00000400 1254 #define TSP_RM_PKT_DEMUX_PIPE 0x00000800 1255 #define TSP_VQ_EN 0x00004000 1256 #define TSP_VQ2PINGPONG_EN 0x00008000 1257 #define TSP_PVR1_REC_ALL_EN 0x00010000 1258 #define TSP_PVR2_REC_ALL_EN 0x00020000 1259 #define TSP_DMA_FLUSH_EN 0x00040000 //PVR1, PVR2 dma flush 1260 #define TSP_REC_ALL_OLD 0x00080000 1261 #define TSP_RESET_AFIFO3 0x00400000 1262 #define TSP_RESET_AFIFO4 0x00800000 1263 #define TSP_TSIF0_CLK_STAMP_27_EN 0x01000000 1264 #define TSP_PVR1_CLK_STAMP_27_EN 0x02000000 1265 #define TSP_PVR2_CLK_STAMP_27_EN 0x04000000 1266 #define TSP_REC_NULL 0x40000000 // No used 1267 1268 REG32 VQ3_BASE; // 0xbf802dC0 0x74 1269 1270 REG32 VQ3_Config; // 0xbf802dC0 0x76 1271 1272 REG32 VQ_RX_Status; // 0xbf802dC0 0x78 1273 #define VQ_RX_ARBITER_MODE_MASK 0x0000000F 1274 #define VQ_RX_ARBITER_MODE_SHIFT 0 1275 #define VQ_RX0_PRI_MASK 0x000000F0 1276 #define VQ_RX0_PRI_SHIFT 4 1277 #define VQ_RX1_PRI_MASK 0x00000F00 1278 #define VQ_RX1_PRI_SHIFT 8 1279 #define VQ_RX2_PRI_MASK 0x0000F000 1280 #define VQ_RX2_PRI_SHIFT 12 1281 1282 REG32 _xbf802dC0; // 0xbf802dC0 0x7a 1283 1284 REG32 MCU_Data1; // 0xbf802dC0 0x7c 1285 } REG_Ctrl; 1286 1287 // TSP part 2 1288 typedef struct _REG_Ctrl2 1289 { 1290 REG16 Qmem_Dbg; // 0xbf803ac0 0x70 1291 #define QMEM_DBG_MODE 0x0001 1292 #define QMEM_DBG_TSP_SEL_SRAM 0x0002 1293 REG16 Qmem_Dbg_RAddr; // 0xbf803ac4 0x71 1294 #define QMEM_DBG_RADDR_MASK 0xFFFF 1295 REG32 Qmem_Dbg_RD ; // 0xbf803ac8~0xbf803acc 0x72~0x73 1296 1297 } REG_Ctrl2; 1298 1299 typedef struct _REG_Ctrl3 1300 { 1301 REG16 PktConverterCfg[3]; // 0x10~12 1302 #define INPUT_MODE_MASK 0x0007 1303 #define INPUT_MODE_SHIF 0 1304 #define FORCE_SYNC_0X47 0x0008 1305 #define BYPASS_PKT_CONVERTER 0x0010 1306 #define BYPASS_SRC_ID_PARSER 0x0020 1307 1308 REG16 _reserved_TSP3_13; // 0x13 1309 1310 REG16 HW3_Cfg0; // 0x14 1311 #define PREVENT_SRAM_COLLISION 0x0001 1312 #define PUSI_THREE_BYTE_MODE 0x0002 1313 #define PCR0_SRC_MASK 0x0F00 1314 #define PCR0_SRC_SHIFT 8 1315 1316 REG16 HW3_Cfg1; // 0x15 1317 #define MASK_SCR_VID_EN 0x0001 1318 #define MASK_SCR_VID_3D_EN 0x0002 1319 #define MASK_SCR_AUD_EN 0x0004 1320 #define MASK_SCR_AUD_B_EN 0x0008 1321 #define MASK_SCR_PVR1_EN 0x0040 1322 #define MASK_SCR_PVR2_EN 0x0080 1323 #define RST_CC_MODE 0x0100 1324 #define DIS_CNTR_INC_BY_PL 0x0200 1325 #define BYPASS_TIMESTAMP_SEL0 0x0400 1326 #define BYPASS_TIMESTAMP_SEL1 0x0800 1327 1328 REG32 _reserved_TSP3_16_19[2]; // 0x16~17, 0x18~19 1329 1330 REG32 PIDFLR_PCR[1]; // 0x1a-0x1b 1331 #define TSP_PIDFLT_PCR_PID_MASK 0x00001fff 1332 #define TSP_PIDFLT_PCR_EN 0x00008000 1333 #define TSP_PIDFLT_PCR_SOURCE_MASK 0x000F0000 1334 #define TSP_PIDFLT_PCR_SOURCE_SHIFT 16 1335 1336 REG32 _reserved_TSP3_1c_1f[2]; // 0x1c~0x1f 1337 1338 REG16 HW_Semaphore0; // 0x20 1339 REG16 HW_Semaphore1; // 0x21 1340 REG16 HW_Semaphore2; // 0x22 1341 1342 REG16 HWeco0; // 0x23 1343 #define HW_ECO_RVU 0x0001 1344 #define HW_ECO_NEW_SYNCP_IN_ECO 0x0002 1345 #define HW_ECO_BURST_NEW_MODE0 0x0004 1346 #define HW_ECO_BURST_NEW_MODE1 0x0008 1347 #define HW_ECO_FIX_FIQ_RESDEADLOCK 0x0010 1348 #define HW_ECO_FIX_SEC_NULLPKT_ERR 0x0020 1349 1350 REG16 HWeco1; // 0x24 1351 REG16 ModeCfg; // 0x25 1352 #define TSP_3WIRE_SERIAL_MODE_MASK 0x001F //set 1 to enable 3 wire serial in mode: Combine valid and clk.Valid always 1 and gated clk when no data in 1353 #define TSP_3WIRE_SERIAL_TSIF0 0x0001 1354 #define TSP_3WIRE_SERIAL_TSIF1 0x0002 1355 #define TSP_3WIRE_SERIAL_TSIFFI 0x0010 1356 #define TSP_NEW_OVERFLOW_MODE 0x0100 // 1: new dma_overflow 0:old dma_overflow 1357 #define TSP_NON_188_CNT_MODE 0x0200 1358 1359 REG16 _reserved_TSP3_26_27[2]; // 0x26~27 1360 1361 REG16 SyncByte_tsif0[4]; // 0x28~2b 1362 #define TSP_SYNC_BYTE0_MAASK0 0x00FF 1363 #define TSP_SYNC_BYTE0_MAASK1 0xFF00 1364 REG16 SourceId_tsif0[2]; // 0x2c~2d 1365 #define TSP_SRCID_MASK0 0x000F 1366 #define TSP_SRCID_MASK1 0x00F0 1367 #define TSP_SRCID_MASK2 0x0F00 1368 #define TSP_SRCID_MASK3 0xF000 1369 REG16 SyncByte_file[4]; 1370 REG16 SourceId_file[2]; 1371 REG16 SyncByte_tsif1[4]; 1372 REG16 SourceId_tsif1[2]; 1373 } REG_Ctrl3; 1374 1375 // TSP part 4 1376 typedef struct _REG_Ctrl4 1377 { 1378 REG16 Overflow0; // 0xbf803900 0x00 1379 #define PID_HIT_0_EVER_OVERFLOW 0x0001 1380 #define PID_HIT_1_EVER_OVERFLOW 0x0002 1381 #define PID_HIT_FILE_EVER_OVERFLOW 0x0008 1382 #define AFIFO_EVER_OVERFLOW 0x0020 1383 #define AFIFOB_EVER_OVERFLOW 0x0040 1384 #define VFIFO_EVER_OVERFLOW 0x0080 1385 #define V3DFIFO_EVER_OVERFLOW 0x0100 1386 #define PVR_1_EVER_OVERFLOW 0x0200 1387 #define PVR_2_EVER_OVERFLOW 0x0400 1388 #define VQ_TX0_EVER_OVERFLOW 0x1000 1389 #define VQ_TX1_EVER_OVERFLOW 0x2000 1390 #define VQ_TX2_EVER_OVERFLOW 0x4000 1391 1392 REG16 Overflow1; // 0xbf803904 0x01 1393 #define SEC_DMAW_OVERFLOW 0x0004 1394 #define SEC_SINGLE_EVER_OVERFLOW 0x0002 1395 #define SEC_PINGPONG_EVER_OVERFLOW 0x0001 1396 1397 REG16 FifoStatus; // 0xbf803908 0x02 1398 #define AFIFO_STATUS_MASK 0x000F 1399 #define AFIFO_STATUS_SHFT 0 1400 #define AFIFOB_STATUS_MASK 0x00F0 1401 #define AFIFOB_STATUS_SHFT 4 1402 #define VFIFO_STATUS_MASK 0x0F00 1403 #define VFIFO_STATUS_SHFT 8 1404 #define V3DFIFO_STATUS_MASK 0xF000 1405 #define V3DFIFO_STATUS_SHFT 12 1406 1407 REG16 PvrFifoStatus; // 0xbf80390C 0x03 1408 #define PVR_1_STATUS_MASK 0x000F 1409 #define PVR_1_STATUS_SHFT 0 1410 #define PVR_2_STATUS_MASK 0x00F0 1411 #define PVR_2_STATUS_SHFT 4 1412 1413 REG16 VQTxFifoStatus; // 0xbf803910 0x04 1414 #define VQ_TX0_STATUS_MASK 0x000F 1415 #define VQ_TX0_STATUS_SHFT 0 1416 #define VQ_TX1_STATUS_MASK 0x0F00 1417 #define VQ_TX1_STATUS_SHFT 8 1418 1419 REG16 PktCnt_video; // 0x05 1420 REG16 PktCnt_v3d; // 0x06 1421 REG16 PktCnt_aud; // 0x07 1422 REG16 PktCnt_audB; // 0x08 1423 REG16 PktCnt_audC; // 0x09 1424 REG16 PktCnt_audD; // 0x0a 1425 REG16 Reserved[0xd-0xb]; 1426 REG16 LockedPktCnt; // 0x0d 1427 REG16 AVPktCnt; // 0x0e 1428 1429 REG16 PktErrStatus; // 0xbf80392C 0x0x0f 1430 REG16 PidMatched0; // 0xbf803930 0x10 1431 REG16 PidMatched1; // 0xbf803934 0x11 1432 REG16 PidMatched2; // 0xbf803938 0x12 1433 REG16 PidMatched3; // 0xbf80393C 0x13 1434 REG16 dummy[2]; // 0x14~0x15 1435 REG16 Sram2p_collision; // 0x16 1436 #define SRAM_COLLISION_BY_SW 0x1000 1437 #define SRAM_COLLISION_BY_HW 0x2000 1438 #define SECFLT_SRAM1_EVER_COLLISION 0x4000 1439 #define SECFLT_SRAM0_EVER_COLLISION 0x8000 1440 REG16 AVPktCnt1; //for vid_3d/audb 0x17 1441 REG16 ErrPktCnt; //use reg_err_pkt_src_sel 0x18 1442 REG16 AVPktCnt2; //for audc/audd 0x19 1443 1444 REG16 EverUnlockStatus; // 0x1a 1445 #define EVER_UNLOCK_TS0 0x0001 // set 1 mean there are unlock pkts 1446 #define EVER_UNLOCK_TS1 0x0002 1447 #define EVER_UNLOCK_TS2 0x0004 1448 1449 REG16 Overflow2; // 0xbf803904 0x1b 1450 #define PC_EVER_OVERFLOW_0 0x0001 1451 #define PC_EVER_OVERFLOW_FILE 0x0002 1452 #define PC_EVER_OVERFLOW_1 0x0004 1453 #define PC_EVER_OVERFLOW_2 0x0008 1454 1455 REG16 dummy1[0x70-0x1c]; 1456 REG16 ErrPktSrcSel; //select source of ErrPktCnt 0x70 1457 #define ERR_PKT_SRC_TS0 0x0001 1458 #define ERR_PKT_SRC_FILE 0x0002 1459 #define ERR_PKT_SRC_TS1 0x0003 1460 #define ERR_PKT_SRC_TS2 0x0004 1461 #define ERR_PKT_SRC_MMFI0 0x0005 1462 #define ERR_PKT_SRC_MMFI1 0x0006 1463 1464 REG16 ErrPktCntLoad; // 0x71 1465 #define ERR_PKT_CNT_0_LOAD 0x0001 1466 #define ERR_PKT_CNT_FILE_LOAD 0x0002 1467 #define ERR_PKT_CNT_1_LOAD 0x0004 1468 #define ERR_PKT_CNT_2_LOAD 0x0008 1469 #define ERR_PKT_CNT_MMFI0_LOAD 0x0010 1470 #define ERR_PKT_CNT_MMFI1_LOAD 0x0020 1471 1472 REG16 ErrPktCntClr; // 0x72 1473 #define ERR_PKT_CNT_0_CLR 0x0001 1474 #define ERR_PKT_CNT_FILE_CLR 0x0002 1475 #define ERR_PKT_CNT_1_CLR 0x0004 1476 #define ERR_PKT_CNT_2_CLR 0x0008 1477 #define ERR_PKT_CNT_MMFI0_CLR 0x0010 1478 #define ERR_PKT_CNT_MMFI1_CLR 0x0020 1479 1480 REG16 dummy2[0x78-0x73]; // 0x73~0x77 1481 REG16 AudCSrc; // ?? //0x78 1482 REG16 dummy3; 1483 REG16 PktCntLoad; // 0x7a 1484 #define LOCK_PKT_CNT_0_LOAD 0x0001 1485 #define LOCK_PKT_CNT_1_LOAD 0x0002 1486 #define LOCK_PKT_CNT_2_LOAD 0x0004 1487 #define LOCK_PKT_CNT_CB_LOAD 0x0008 1488 #define LOCK_PKT_CNT_FI_LOAD 0x0010 1489 1490 #define V_PKT_CNT_LOAD 0x0100 1491 #define V3D_PKT_CNT_LOAD 0x0200 1492 #define AUD_PKT_CNT_LOAD 0x0400 1493 #define AUDB_PKT_CNT_LOAD 0x0800 1494 #define AUDC_PKT_CNT_LOAD 0x1000 1495 #define AUDD_PKT_CNT_LOAD 0x2000 1496 1497 REG16 PktCntLoad1; // 0x7b 1498 #define V_DROP_PKT_CNT_LOAD 0x0001 1499 #define V3D_DROP_PKT_CNT_LOAD 0x0002 1500 #define AUD_DROP_PKT_CNT_LOAD 0x0004 1501 #define AUDB_DROP_PKT_CNT_LOAD 0x0008 1502 #define AUDC_DROP_PKT_CNT_LOAD 0x0010 1503 #define AUDD_DROP_PKT_CNT_LOAD 0x0020 1504 1505 #define V_DIS_CNTR_PKT_CNT_LOAD 0x0100 1506 #define V3D_DIS_CNTR_PKT_CNT_LOAD 0x0200 1507 #define AUD_DIS_CNTR_PKT_CNT_LOAD 0x0400 1508 #define AUDB_DIS_CNTR_PKT_CNT_LOAD 0x0800 1509 #define AUDC_DIS_CNTR_PKT_CNT_LOAD 0x1000 1510 #define AUDD_DIS_CNTR_PKT_CNT_LOAD 0x2000 1511 1512 1513 REG16 PktCntClr; // 0x7c 1514 #define LOCK_PKT_CNT_0_CLR 0x0001 1515 #define LOCK_PKT_CNT_1_CLR 0x0002 1516 #define LOCK_PKT_CNT_2_CLR 0x0004 1517 #define LOCK_PKT_CNT_CB_CLR 0x0008 1518 #define LOCK_PKT_CNT_FI_CLR 0x0010 1519 1520 #define V_PKT_CNT_CLR 0x0100 1521 #define V3D_PKT_CNT_CLR 0x0200 1522 #define AUD_PKT_CNT_CLR 0x0400 1523 #define AUDB_PKT_CNT_CLR 0x0800 1524 1525 REG16 PktCntClr1; // 0x7d 1526 #define V_DROP_PKT_CNT_CLR 0x0001 1527 #define V3D_DROP_PKT_CNT_CLR 0x0002 1528 #define AUD_DROP_PKT_CNT_CLR 0x0004 1529 #define AUDB_DROP_PKT_CNT_CLR 0x0008 1530 1531 #define V_DIS_CNTR_PKT_CNT_CLR 0x0100 1532 #define V3D_DIS_CNTR_PKT_CNT_CLR 0x0200 1533 #define AUD_DIS_CNTR_PKT_CNT_CLR 0x0400 1534 #define AUDB_DIS_CNTR_PKT_CNT_CLR 0x0800 1535 1536 REG16 PktCntSrc; // 0x7e 1537 #define VID_SRC_MASK 0x0007 1538 #define VID_SRC_SHIFT 0 1539 #define V3D_SRC_MASK 0x0031 1540 #define V3D_SRC_SHIFT 3 1541 #define AUD_SRC_MASK 0x01C0 1542 #define AUD_SRC_SHIFT 6 1543 #define AUDB_SRC_MASK 0x0E00 1544 #define AUDB_SRC_SHIFT 9 1545 1546 REG16 DebugSrcSel; // 0x7f 1547 #define SRC_SEL_MASK 0x0001 1548 #define DROP_PKT_MODE_MASK 0x0002 1549 #define PIDFLT_SRC_SEL_MASK 0x001C 1550 #define TSIF_SRC_SEL_MASK 0x00E0 1551 #define TSIF_SRC_SEL_SHIFT 5 1552 #define TSIF_SRC_SEL_TSIF0 0x000 1553 #define TSIF_SRC_SEL_TSIF1 0x001 1554 #define TSIF_SRC_SEL_TSIF_FI 0x004 1555 1556 #define AV_PKT_SRC_SEL 0x0100 1557 #define AV_PKT_SRC_SEL_MASK 0x0100 1558 #define AV_PKT_SRC_SEL_SHIFT 8 1559 #define AV_PKT_SRC_VID 0x0 1560 #define AV_PKT_SRC_AUD 0x1 1561 #define AV_PKT_SRC_V3D 0x0 1562 #define AV_PKT_SRC_AUDB 0x1 1563 #define CLR_SRC_MASK 0x0E00 1564 1565 }REG_Ctrl4; 1566 1567 // TSP part 4 1568 typedef struct _REG_Ctrl5 1569 { 1570 REG16 ATS_Adj_Period; // 0x00 1571 #define TSP_ATS_ADJ_PERIOD_MASK 0x000F 1572 1573 REG16 AtsCfg; // 0x01 1574 #define TSP_ATS_MODE_FI_ENABLE 0x0001 1575 #define TSP_ATS_OFFSET_FI_ENABLE 0x0002 1576 #define TSP_ATS_OFFSET_FI_SHIFT 8 1577 #define TSP_ATS_OFFSET_FI_MASK 0x0F00 1578 #define TSP_ATS_OFFSET_FI_POSITIVE 0x0000 1579 #define TSP_ATS_OFFSET_FI_NEGATIVE 0x1000 1580 1581 REG16 Ts_If_Fi_Cfg; // 0x02 1582 #define TSP_FIIF_EN 0x0001 1583 #define TSP_FIIF_DATA_SWAP 0x0002 1584 #define TSP_FIIF_P_SEL 0x0004 1585 #define TSP_FIIF_EXT_SYNC_SEL 0x0008 1586 #define TSP_FIIF_MUX_MASK 0x0010 1587 #define TSP_FIIF_MUX_FILE_PATH 0x0000 1588 #define TSP_FIIF_MUX_LIVE_PATH 0x0010 1589 #define TSP_PKT_CHK_SIZE_FI_MASK 0xFF00 1590 #define TSP_PKT_CHK_SIZE_FI_SHIFT 8 1591 1592 REG16 S2PCfg; // 0x03 1593 #define TSP_MATCH_PID_SEL_MASK 0x000F // 0: #0~#31, 1: #32~#63, 2: #64~#95, 3: #96~#127 1594 #define TSP_MATCH_PID_SEL_SHIFT 0 1595 1596 REG16 S2PCfg1; // 0x04 1597 #define TSP_S2PCFG1_TSIF_0_TSO_BLK_EN 0x0100 1598 #define TSP_S2PCFG1_TSIF_1_TSO_BLK_EN 0x0200 1599 #define TSP_S2PCFG1_TSIF_FI_TSO_BLK_EN 0x0800 1600 #define TSP_S2PCFG1_WB_FSM_RST 0x1000 1601 #define TSP_S2PCFG1_WB_FSM_RST_FINISHED 0x2000 1602 1603 REG16 TSP5_Reserve_5; // 0x05 1604 REG16 TSP5_Eco; // 0x06 1605 #define TSP_192_TIMER_0_EN 0x0001 1606 REG16 TSP5_Reserve[9]; // 0x07~0x0F 1607 1608 1609 REG16 TS_MUX_CFG0; // 0x10 1610 #define TS_MUX_CFG_TS0_MUX_MASK 0x000F 1611 #define TS_MUX_CFG_TS0_MUX_SHIFT 0 1612 #define TS_MUX_CFG_TS1_MUX_MASK 0x00F0 1613 #define TS_MUX_CFG_TS1_MUX_SHIFT 4 1614 #define TS_MUX_CFG_TSFI_MUX_MASK 0xF000 1615 #define TS_MUX_CFG_TSFI_MUX_SHIFT 12 1616 #define TS_MUX_CFG_TS_MUX_TS0 0x0000 1617 #define TS_MUX_CFG_TS_MUX_TS1 0x0001 1618 #define TS_MUX_CFG_TS_MUX_TS2 0x0002 1619 #define TS_MUX_CFG_TS_MUX_TSO 0x0006 1620 #define TS_MUX_CFG_TS_MUX_DMD 0x0007 1621 REG16 TS_MUX_CFG1; // 0x11 1622 1623 REG16 TS_MUX_CFG_S2P; // 0x12 1624 #define TS_MUX_CFG_S2P0_MUX_MASK 0x000F 1625 #define TS_MUX_CFG_S2P_MUX_TS0 0x0000 1626 #define TS_MUX_CFG_S2P_MUX_TS1 0x0001 1627 #define TS_MUX_CFG_S2P_MUX_TS2 0x0002 1628 1629 REG16 TS_MUX_CFG0_TSOIN; // 0x13 1630 #define TS_MUX_CFG_TSOIN0_MUX_MASK 0x000F 1631 #define TS_MUX_CFG_TSOIN0_MUX_SHIFT 0 1632 #define TS_MUX_CFG_TSOIN1_MUX_MASK 0x00F0 1633 #define TS_MUX_CFG_TSOIN1_MUX_SHIFT 4 1634 1635 REG16 TSP5_Reserve_14; // 0x14 1636 1637 REG16 TS_MUX_CFG_TSOOUT; // 0x15 1638 #define TS_MUX_CFG_TSOOUT_MASK 0x000F 1639 #define TS_MUX_CFG_TSOOUT_FROM_TSO 0x0000 1640 #define TS_MUX_CFG_TSOOUT_FROM_S2P 0x0001 1641 }REG_Ctrl5; 1642 1643 // TSP: ts sample part 1644 typedef struct _REG_TS_Sample 1645 { 1646 REG16 TS0_Clk_Sample; // 0x00 1647 #define TS0_PHASE_ADJUST_COUNT_MASK 0x001F 1648 #define TS0_PHASE_ADJUST_EN 0x0020 1649 #define TS0_RESAMPLE_VOTE_ADJUST_EN 0x0040 1650 1651 REG16 TS1_Clk_Sample; // 0x01 1652 #define TS1_PHASE_ADJUST_COUNT_MASK 0x001F 1653 #define TS1_PHASE_ADJUST_EN 0x0020 1654 #define TS1_RESAMPLE_VOTE_ADJUST_EN 0x0040 1655 1656 REG16 TS2_Clk_Sample; // 0x02 1657 #define TS2_PHASE_ADJUST_COUNT_MASK 0x001F 1658 #define TS2_PHASE_ADJUST_EN 0x0020 1659 #define TS2_RESAMPLE_VOTE_ADJUST_EN 0x0040 1660 1661 REG16 TS3_Clk_Sample; // 0x03 1662 #define TS3_PHASE_ADJUST_COUNT_MASK 0x001F 1663 #define TS3_PHASE_ADJUST_EN 0x0020 1664 #define TS3_RESAMPLE_VOTE_ADJUST_EN 0x0040 1665 1666 REG16 TS4_Clk_Sample; // 0x04 1667 #define TS4_PHASE_ADJUST_COUNT_MASK 0x001F 1668 #define TS4_PHASE_ADJUST_EN 0x0020 1669 #define TS4_RESAMPLE_VOTE_ADJUST_EN 0x0040 1670 1671 REG16 TS5_Clk_Sample; // 0x05 1672 #define TS5_PHASE_ADJUST_COUNT_MASK 0x001F 1673 #define TS5_PHASE_ADJUST_EN 0x0020 1674 #define TS5_RESAMPLE_VOTE_ADJUST_EN 0x0040 1675 1676 REG16 TsSample_Reserved0[0x10-0x6]; // 0x06 - 0x0F 1677 1678 REG16 TSO_Clk_Sample; // 0x10 1679 #define TSO_PHASE_ADJUST_COUNT_MASK 0x001F 1680 #define TSO_PHASE_ADJUST_EN 0x0020 1681 #define TSO_RESAMPLE_VOTE_ADJUST_EN 0x0040 1682 #define TSO_CLK_INVERT 0x0080 1683 1684 REG16 TsSample_Reserved1[0x20-0x11]; // 0x11 - 0x1F 1685 1686 REG16 TS_Out_Clk_Sample; // 0x20 (for old path: TSIF2 out) 1687 #define TS_OUT_PHASE_ADJUST_COUNT_MASK 0x001F 1688 #define TS_OUT_PHASE_ADJUST_EN 0x0020 1689 #define TS_OUT_RESAMPLE_VOTE_ADJUST_EN 0x0040 1690 #define TS_OUT_CLK_INVERT 0x0080 1691 1692 REG16 S2P_Out_Clk_Sample; // 0x21 1693 #define S2P_PHASE_ADJUST_COUNT_MASK 0x001F 1694 #define S2P_PHASE_ADJUST_EN 0x0020 1695 #define S2P_RESAMPLE_VOTE_ADJUST_EN 0x0040 1696 #define S2P_CLK_INVERT 0x0080 1697 1698 REG16 TsSample_Reserved2[0x30-0x23]; // 0x22 - 0x30 1699 1700 REG16 TSO_Out_Clk_Sel; // 0x30 1701 #define TSO_0_sel_MASK 0x0003 1702 #define TSO_0_sel_TSO 0x0000 1703 #define TSO_0_sel_S2P0 0x0001 1704 #define TSO_0_sel_S2P1 0x0002 1705 1706 #define TSO_1_sel_MASK 0x0030 1707 #define TSO_1_sel_TSO 0x0000 1708 #define TSO_1_sel_S2P0 0x0010 1709 #define TSO_1_sel_S2P1 0x0020 1710 1711 }REG_TS_Sample; 1712 1713 // Firmware status 1714 #define TSP_FW_STATE_MASK 0xFFFF0000 1715 #define TSP_FW_STATE_LOAD 0x00010000 1716 #define TSP_FW_STATE_ENG_OVRUN 0x00020000 1717 #define TSP_FW_STATE_ENG1_OVRUN 0x00040000 //[reserved] 1718 #define TSP_FW_STATE_IC_ENABLE 0x01000000 1719 #define TSP_FW_STATE_DC_ENABLE 0x02000000 1720 #define TSP_FW_STATE_IS_ENABLE 0x04000000 1721 #define TSP_FW_STATE_DS_ENABLE 0x08000000 1722 1723 1724 // TSP AEON specific IP address 1725 #define OPENRISC_IP_1_ADDR 0x00200000 1726 #define OPENRISC_IP_1_SIZE 0x00020000 1727 #define OPENRISC_IP_2_ADDR 0x90000000 1728 #define OPENRISC_IP_2_SIZE 0x00010000 1729 #define OPENRISC_IP_3_ADDR 0x40080000 1730 #define OPENRISC_IP_3_SIZE 0x00020000 1731 #define OPENRISC_QMEM_ADDR 0x00000000 1732 #define OPENRISC_QMEM_SIZE 0x00003000 1733 #endif // _TSP_REG_H_ 1734