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Searched refs:postdiv1 (Results 1 – 24 of 24) sorted by relevance

/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_pll.c83 u32 *postdiv1, in rockchip_pll_clk_set_postdiv() argument
90 for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) { in rockchip_pll_clk_set_postdiv()
92 freq = fout_hz * (*postdiv1) * (*postdiv2); in rockchip_pll_clk_set_postdiv()
103 *postdiv1 = 1; in rockchip_pll_clk_set_postdiv()
117 u32 f_frac, postdiv1, postdiv2; in rockchip_pll_clk_set_by_auto() local
123 rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco); in rockchip_pll_clk_set_by_auto()
124 rate_table->postdiv1 = postdiv1; in rockchip_pll_clk_set_by_auto()
141 rate_table->fbdiv, rate_table->postdiv1, in rockchip_pll_clk_set_by_auto()
147 rate_table->postdiv1, rate_table->postdiv2, foutvco); in rockchip_pll_clk_set_by_auto()
305 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv); in rk3036_pll_set_rate()
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H A Dclk_rk3399.c38 u32 postdiv1; member
51 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz};
344 u32 refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
356 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
359 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
370 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
374 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
397 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | in rkclk_set_pll()
448 u32 postdiv1, postdiv2 = 1; in pll_para_config() local
461 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); in pll_para_config()
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H A Dclk_rk3036.c52 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
70 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
74 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
87 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
204 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
230 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
235 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
H A Dclk_rv1108.c34 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
73 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
76 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
95 (div->postdiv1 << POSTDIV1_SHIFT | in rkclk_set_pll()
120 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
132 postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT; in rkclk_pll_get_rate()
135 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
H A Dclk_px30.c37 .postdiv1 = _postdiv1, \
111 u32 postdiv1, postdiv2 = 1; in pll_clk_set_by_auto() local
124 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, rate_khz); in pll_clk_set_by_auto()
125 if (postdiv1 > max_postdiv1) { in pll_clk_set_by_auto()
126 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_clk_set_by_auto()
127 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); in pll_clk_set_by_auto()
130 vco_khz = rate_khz * postdiv1 * postdiv2; in pll_clk_set_by_auto()
139 rate->postdiv1 = postdiv1; in pll_clk_set_by_auto()
229 output_hz = vco_hz / rate->postdiv1 / rate->postdiv2; in rkclk_set_pll()
232 pll, rate->fbdiv, rate->refdiv, rate->postdiv1, in rkclk_set_pll()
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/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_cru.c62 u32 postdiv1, fbdiv, dsmpd, postdiv2, refdiv, frac, bypass; in rk628_cru_clk_get_rate_pll() local
99 postdiv1 = (con0 & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rk628_cru_clk_get_rate_pll()
120 do_div(foutpostdiv, postdiv1); in rk628_cru_clk_get_rate_pll()
132 u8 dsmpd = 1, postdiv1 = 0, postdiv2 = 0, refdiv = 0; in rk628_cru_clk_set_rate_pll() local
184 postdiv1 = postdiv / postdiv2; in rk628_cru_clk_set_rate_pll()
185 if (postdiv1 > 0 && postdiv1 < 8) in rk628_cru_clk_set_rate_pll()
195 fout *= postdiv1 * postdiv2; in rk628_cru_clk_set_rate_pll()
197 postdiv1 = 1; in rk628_cru_clk_set_rate_pll()
251 do_div(foutpostdiv, postdiv1); in rk628_cru_clk_set_rate_pll()
255 PLL_BYPASS(0) | PLL_POSTDIV1(postdiv1) | in rk628_cru_clk_set_rate_pll()
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_rk3328.c79 unsigned int refdiv, postdiv1, postdiv2, fbdiv; in rkclk_set_dpll() local
85 postdiv1 = 4; in rkclk_set_dpll()
88 postdiv1 = 6; in rkclk_set_dpll()
91 postdiv1 = 4; in rkclk_set_dpll()
94 postdiv1 = 3; in rkclk_set_dpll()
97 postdiv1 = 2; in rkclk_set_dpll()
100 postdiv1 = 1; in rkclk_set_dpll()
103 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
106 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->dpll_con[0]); in rkclk_set_dpll()
H A Dsdram_px30.c78 unsigned int refdiv, postdiv1, postdiv2, fbdiv; in rkclk_set_dpll() local
84 postdiv1 = 4; in rkclk_set_dpll()
87 postdiv1 = 6; in rkclk_set_dpll()
90 postdiv1 = 4; in rkclk_set_dpll()
93 postdiv1 = 3; in rkclk_set_dpll()
96 postdiv1 = 2; in rkclk_set_dpll()
99 postdiv1 = 1; in rkclk_set_dpll()
102 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
106 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0); in rkclk_set_dpll()
H A Dsdram_rk3308.c90 pll_priv->postdiv1 << POSTDIV1_SHIFT); in pll_set()
134 rk3308_pll_div.postdiv1 = 2; in rkdclk_init()
144 rk3308_pll_div.postdiv1 = 4; in rkdclk_init()
152 rk3308_pll_div.postdiv1 = 2; in rkdclk_init()
188 rk3308_pll_div.postdiv1 = 2; in rkdclk_init()
196 rk3308_pll_div.postdiv1 = 1; in rkdclk_init()
265 rk3308_pll_div.postdiv1 = 1; in rkdclk_init()
328 rk3308_pll_div.postdiv1 = 2; in rkdclk_init()
H A Dsdram_rv1108.c52 params_priv->dpll_init_cfg.postdiv1 << POSTDIV1_SHIFT | in rkdclk_init()
H A Dsdram_rv1126.c323 unsigned int refdiv, postdiv1, postdiv2, fbdiv; in rkclk_set_dpll() local
337 postdiv1 = 6; in rkclk_set_dpll()
340 postdiv1 = 4; in rkclk_set_dpll()
343 postdiv1 = 6; in rkclk_set_dpll()
346 postdiv1 = 4; in rkclk_set_dpll()
349 postdiv1 = 6; in rkclk_set_dpll()
352 postdiv1 = 4; in rkclk_set_dpll()
355 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
360 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0); in rkclk_set_dpll()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dclock.h73 .postdiv1 = _postdiv1, \
97 unsigned int postdiv1; member
H A Dcru_rk3036.h69 u32 postdiv1; member
H A Dcru_rv1108.h57 u32 postdiv1; member
H A Dcru_rv1103b.h118 unsigned int postdiv1; member
H A Dcru_rv1106.h122 unsigned int postdiv1; member
H A Dcru_rk3506.h87 unsigned int postdiv1; member
H A Dcru_rv1126.h142 unsigned int postdiv1; member
H A Dcru_px30.h118 unsigned int postdiv1; member
H A Dcru_rk3528.h108 unsigned int postdiv1; member
H A Dcru_rk3562.h143 unsigned int postdiv1; member
H A Dcru_rv1126b.h147 unsigned int postdiv1; member
H A Dcru_rk3568.h115 unsigned int postdiv1; member
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c340 (dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) | in rkdclk_init()