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Searched refs:APLL (Results 1 – 25 of 33) sorted by relevance

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/OK3568_Linux_fs/u-boot/arch/arm/mach-s5pc1xx/
H A Dclock.c34 case APLL: in s5pc100_get_pll_clk()
57 if (pllreg == APLL) in s5pc100_get_pll_clk()
85 case APLL: in s5pc110_get_pll_clk()
108 if (pllreg == APLL || pllreg == MPLL) in s5pc110_get_pll_clk()
121 if (pllreg == APLL) { in s5pc110_get_pll_clk()
147 dout_apll = get_pll_clk(APLL) / (apll_ratio + 1); in s5pc110_get_arm_clk()
169 dout_apll = get_pll_clk(APLL) / (apll_ratio + 1); in s5pc100_get_arm_clk()
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3128.c81 [APLL] = PLL(pll_rk3036, PLL_APLL, RK2928_PLL_CON(0),
108 old_rate = rockchip_pll_get_rate(&rk3128_pll_clks[APLL], in rk3128_armclk_set_clk()
109 priv->cru, APLL); in rk3128_armclk_set_clk()
111 if (rockchip_pll_set_rate(&rk3128_pll_clks[APLL], in rk3128_armclk_set_clk()
112 priv->cru, APLL, hz)) in rk3128_armclk_set_clk()
131 if (rockchip_pll_set_rate(&rk3128_pll_clks[APLL], in rk3128_armclk_set_clk()
132 priv->cru, APLL, hz)) in rk3128_armclk_set_clk()
136 return rockchip_pll_get_rate(&rk3128_pll_clks[APLL], priv->cru, APLL); in rk3128_armclk_set_clk()
543 rate = rockchip_pll_get_rate(&rk3128_pll_clks[APLL], in rk3128_clk_get_rate()
544 priv->cru, APLL); in rk3128_clk_get_rate()
[all …]
H A Dclk_rk322x.c82 [APLL] = PLL(pll_rk3036, PLL_APLL, RK2928_PLL_CON(0),
109 old_rate = rockchip_pll_get_rate(&rk322x_pll_clks[APLL], in rk322x_armclk_set_clk()
110 priv->cru, APLL); in rk322x_armclk_set_clk()
112 if (rockchip_pll_set_rate(&rk322x_pll_clks[APLL], in rk322x_armclk_set_clk()
113 priv->cru, APLL, hz)) in rk322x_armclk_set_clk()
132 if (rockchip_pll_set_rate(&rk322x_pll_clks[APLL], in rk322x_armclk_set_clk()
133 priv->cru, APLL, hz)) in rk322x_armclk_set_clk()
137 return rockchip_pll_get_rate(&rk322x_pll_clks[APLL], priv->cru, APLL); in rk322x_armclk_set_clk()
590 rate = rockchip_pll_get_rate(&rk322x_pll_clks[APLL], in rk322x_clk_get_rate()
591 priv->cru, APLL); in rk322x_clk_get_rate()
[all …]
H A Dclk_rk3308.c76 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3308_PLL_CON(0),
154 old_rate = rockchip_pll_get_rate(&rk3308_pll_clks[APLL], in rk3308_armclk_set_clk()
155 priv->cru, APLL); in rk3308_armclk_set_clk()
157 if (rockchip_pll_set_rate(&rk3308_pll_clks[APLL], in rk3308_armclk_set_clk()
158 priv->cru, APLL, hz)) in rk3308_armclk_set_clk()
175 if (rockchip_pll_set_rate(&rk3308_pll_clks[APLL], in rk3308_armclk_set_clk()
176 priv->cru, APLL, hz)) in rk3308_armclk_set_clk()
180 return rockchip_pll_get_rate(&rk3308_pll_clks[APLL], priv->cru, APLL); in rk3308_armclk_set_clk()
939 rate = rockchip_pll_get_rate(&rk3308_pll_clks[APLL], in rk3308_clk_get_rate()
940 priv->cru, APLL); in rk3308_clk_get_rate()
[all …]
H A Dclk_rk1808.c80 [APLL] = PLL(pll_rk3036, PLL_APLL, RK1808_PLL_CON(0),
877 old_rate = rockchip_pll_get_rate(&rk1808_pll_clks[APLL], in rk1808_armclk_set_clk()
878 priv->cru, APLL); in rk1808_armclk_set_clk()
880 if (rockchip_pll_set_rate(&rk1808_pll_clks[APLL], in rk1808_armclk_set_clk()
881 priv->cru, APLL, hz)) in rk1808_armclk_set_clk()
898 if (rockchip_pll_set_rate(&rk1808_pll_clks[APLL], in rk1808_armclk_set_clk()
899 priv->cru, APLL, hz)) in rk1808_armclk_set_clk()
903 return rockchip_pll_get_rate(&rk1808_pll_clks[APLL], priv->cru, APLL); in rk1808_armclk_set_clk()
923 rate = rockchip_pll_get_rate(&rk1808_pll_clks[APLL], in rk1808_clk_get_rate()
924 priv->cru, APLL); in rk1808_clk_get_rate()
[all …]
H A Dclk_rk3528.c66 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3528_PLL_CON(0),
210 old_rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru, APLL); in rk3528_armclk_set_clk()
212 if (rockchip_pll_set_rate(&rk3528_pll_clks[APLL], in rk3528_armclk_set_clk()
213 priv->cru, APLL, new_rate)) in rk3528_armclk_set_clk()
228 if (rockchip_pll_set_rate(&rk3528_pll_clks[APLL], in rk3528_armclk_set_clk()
229 priv->cru, APLL, new_rate)) in rk3528_armclk_set_clk()
1346 rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru, in rk3528_clk_get_rate()
1347 APLL); in rk3528_clk_get_rate()
1859 rockchip_pll_get_rate(&rk3528_pll_clks[APLL], in rk3528_clk_init()
1860 priv->cru, APLL); in rk3528_clk_init()
[all …]
H A Dclk_rv1106.c39 [APLL] = PLL(pll_rk3328, PLL_APLL, RV1106_PLL_CON(0),
1052 rate = rockchip_pll_get_rate(&rv1106_pll_clks[APLL], priv->cru, in rv1106_clk_get_rate()
1053 APLL); in rv1106_clk_get_rate()
1154 ret = rockchip_pll_set_rate(&rv1106_pll_clks[APLL], priv->cru, in rv1106_clk_set_rate()
1155 APLL, rate); in rv1106_clk_set_rate()
1265 rockchip_pll_get_rate(&rv1106_pll_clks[APLL], in rv1106_clk_init()
1266 priv->cru, APLL); in rv1106_clk_init()
1271 ret = rockchip_pll_set_rate(&rv1106_pll_clks[APLL], priv->cru, in rv1106_clk_init()
1272 APLL, APLL_HZ); in rv1106_clk_init()
H A Dclk_rk3562.c45 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3562_PLL_CON(0),
168 old_rate = rockchip_pll_get_rate(&rk3562_pll_clks[APLL], priv->cru, in rk3562_armclk_set_rate()
169 APLL); in rk3562_armclk_set_rate()
177 if (rockchip_pll_set_rate(&rk3562_pll_clks[APLL], in rk3562_armclk_set_rate()
178 priv->cru, APLL, new_rate)) in rk3562_armclk_set_rate()
192 if (rockchip_pll_set_rate(&rk3562_pll_clks[APLL], in rk3562_armclk_set_rate()
193 priv->cru, APLL, new_rate)) in rk3562_armclk_set_rate()
1363 rate = rockchip_pll_get_rate(&rk3562_pll_clks[APLL], priv->cru, in rk3562_clk_get_rate()
1364 APLL); in rk3562_clk_get_rate()
1791 rockchip_pll_get_rate(&rk3562_pll_clks[APLL], in rk3562_clk_init()
[all …]
H A Dclk_px30.c1264 old_rate = px30_clk_get_pll_rate(priv, APLL); in px30_armclk_set_clk()
1266 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) in px30_armclk_set_clk()
1283 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) in px30_armclk_set_clk()
1287 return px30_clk_get_pll_rate(priv, APLL); in px30_armclk_set_clk()
1303 rate = px30_clk_get_pll_rate(priv, APLL); in px30_clk_get_rate()
1315 rate = px30_clk_get_pll_rate(priv, APLL); in px30_clk_get_rate()
1647 priv->armclk_enter_hz = px30_clk_get_pll_rate(priv, APLL); in px30_clk_probe()
1650 if (px30_clk_get_pll_rate(priv, APLL) != APLL_HZ) { in px30_clk_probe()
H A Dclk_rv1126.c60 [APLL] = PLL(pll_rk3328, PLL_APLL, RV1126_PLL_CON(0),
573 old_rate = rockchip_pll_get_rate(&rv1126_pll_clks[APLL], in rv1126_armclk_set_clk()
574 priv->cru, APLL); in rv1126_armclk_set_clk()
576 if (rockchip_pll_set_rate(&rv1126_pll_clks[APLL], in rv1126_armclk_set_clk()
577 priv->cru, APLL, hz)) in rv1126_armclk_set_clk()
588 if (rockchip_pll_set_rate(&rv1126_pll_clks[APLL], in rv1126_armclk_set_clk()
589 priv->cru, APLL, hz)) in rv1126_armclk_set_clk()
1625 rate = rockchip_pll_get_rate(&rv1126_pll_clks[APLL], priv->cru, in rv1126_clk_get_rate()
1626 APLL); in rv1126_clk_get_rate()
2136 rockchip_pll_get_rate(&rv1126_pll_clks[APLL], in rv1126_clk_init()
[all …]
H A Dclk_rk3568.c68 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3568_PLL_CON(0),
577 old_rate = rockchip_pll_get_rate(&rk3568_pll_clks[APLL], in rk3568_armclk_set_clk()
578 priv->cru, APLL); in rk3568_armclk_set_clk()
580 if (rockchip_pll_set_rate(&rk3568_pll_clks[APLL], in rk3568_armclk_set_clk()
581 priv->cru, APLL, hz)) in rk3568_armclk_set_clk()
608 if (rockchip_pll_set_rate(&rk3568_pll_clks[APLL], in rk3568_armclk_set_clk()
609 priv->cru, APLL, hz)) in rk3568_armclk_set_clk()
2516 rate = rockchip_pll_get_rate(&rk3568_pll_clks[APLL], priv->cru, in rk3568_clk_get_rate()
2517 APLL); in rk3568_clk_get_rate()
3238 rockchip_pll_get_rate(&rk3568_pll_clks[APLL], in rk3568_clk_init()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ti/
H A Dapll.txt1 Binding for Texas Instruments APLL clock.
6 register-mapped APLL with usually two selectable input clocks
10 modes (locked, low power stop etc.) APLL mostly behaves like
20 - reg : address and length of the register set for controlling the APLL.
/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/
H A Dclock.c126 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL || in exynos_get_pll_clk()
193 case APLL: in exynos4_get_pll_clk()
223 case APLL: in exynos4x12_get_pll_clk()
254 case APLL: in exynos5_get_pll_clk()
312 case APLL: in exynos542x_get_pll_clk()
585 armclk = get_pll_clk(APLL) / (core_ratio + 1); in exynos4_get_arm_clk()
607 armclk = get_pll_clk(APLL) / (core_ratio + 1); in exynos4x12_get_arm_clk()
629 armclk = get_pll_clk(APLL) / (arm_ratio + 1); in exynos5_get_arm_clk()
1568 sclk = get_pll_clk(APLL); in exynos4_get_i2c_clk()
/OK3568_Linux_fs/u-boot/arch/arm/mach-s5pc1xx/include/mach/
H A Dclk.h12 #define APLL 0 macro
/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/include/mach/
H A Dclk.h11 #define APLL 0 macro
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dxlnx-zynqmp-clk.h14 #define APLL 2 macro
H A Dxlnx-versal-clk.h27 #define APLL 18 macro
/OK3568_Linux_fs/u-boot/board/rockchip/evb_rv1108/
H A DREADME31 APLL: 400000000 DPLL:798000000 GPLL:384000000
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3128.h63 APLL, enumerator
H A Dcru_rk322x.h60 APLL, enumerator
H A Dcru_rk3328.h58 APLL, enumerator
H A Dcru_rv1106.h26 APLL, enumerator
H A Dcru_rk1808.h20 APLL, enumerator
H A Dcru_rk3528.h22 APLL, enumerator
H A Dcru_rv1126.h48 APLL, enumerator

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