1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2019 Xilinx Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_VERSAL_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_VERSAL_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define PMC_PLL 1 11*4882a593Smuzhiyun #define APU_PLL 2 12*4882a593Smuzhiyun #define RPU_PLL 3 13*4882a593Smuzhiyun #define CPM_PLL 4 14*4882a593Smuzhiyun #define NOC_PLL 5 15*4882a593Smuzhiyun #define PLL_MAX 6 16*4882a593Smuzhiyun #define PMC_PRESRC 7 17*4882a593Smuzhiyun #define PMC_POSTCLK 8 18*4882a593Smuzhiyun #define PMC_PLL_OUT 9 19*4882a593Smuzhiyun #define PPLL 10 20*4882a593Smuzhiyun #define NOC_PRESRC 11 21*4882a593Smuzhiyun #define NOC_POSTCLK 12 22*4882a593Smuzhiyun #define NOC_PLL_OUT 13 23*4882a593Smuzhiyun #define NPLL 14 24*4882a593Smuzhiyun #define APU_PRESRC 15 25*4882a593Smuzhiyun #define APU_POSTCLK 16 26*4882a593Smuzhiyun #define APU_PLL_OUT 17 27*4882a593Smuzhiyun #define APLL 18 28*4882a593Smuzhiyun #define RPU_PRESRC 19 29*4882a593Smuzhiyun #define RPU_POSTCLK 20 30*4882a593Smuzhiyun #define RPU_PLL_OUT 21 31*4882a593Smuzhiyun #define RPLL 22 32*4882a593Smuzhiyun #define CPM_PRESRC 23 33*4882a593Smuzhiyun #define CPM_POSTCLK 24 34*4882a593Smuzhiyun #define CPM_PLL_OUT 25 35*4882a593Smuzhiyun #define CPLL 26 36*4882a593Smuzhiyun #define PPLL_TO_XPD 27 37*4882a593Smuzhiyun #define NPLL_TO_XPD 28 38*4882a593Smuzhiyun #define APLL_TO_XPD 29 39*4882a593Smuzhiyun #define RPLL_TO_XPD 30 40*4882a593Smuzhiyun #define EFUSE_REF 31 41*4882a593Smuzhiyun #define SYSMON_REF 32 42*4882a593Smuzhiyun #define IRO_SUSPEND_REF 33 43*4882a593Smuzhiyun #define USB_SUSPEND 34 44*4882a593Smuzhiyun #define SWITCH_TIMEOUT 35 45*4882a593Smuzhiyun #define RCLK_PMC 36 46*4882a593Smuzhiyun #define RCLK_LPD 37 47*4882a593Smuzhiyun #define WDT 38 48*4882a593Smuzhiyun #define TTC0 39 49*4882a593Smuzhiyun #define TTC1 40 50*4882a593Smuzhiyun #define TTC2 41 51*4882a593Smuzhiyun #define TTC3 42 52*4882a593Smuzhiyun #define GEM_TSU 43 53*4882a593Smuzhiyun #define GEM_TSU_LB 44 54*4882a593Smuzhiyun #define MUXED_IRO_DIV2 45 55*4882a593Smuzhiyun #define MUXED_IRO_DIV4 46 56*4882a593Smuzhiyun #define PSM_REF 47 57*4882a593Smuzhiyun #define GEM0_RX 48 58*4882a593Smuzhiyun #define GEM0_TX 49 59*4882a593Smuzhiyun #define GEM1_RX 50 60*4882a593Smuzhiyun #define GEM1_TX 51 61*4882a593Smuzhiyun #define CPM_CORE_REF 52 62*4882a593Smuzhiyun #define CPM_LSBUS_REF 53 63*4882a593Smuzhiyun #define CPM_DBG_REF 54 64*4882a593Smuzhiyun #define CPM_AUX0_REF 55 65*4882a593Smuzhiyun #define CPM_AUX1_REF 56 66*4882a593Smuzhiyun #define QSPI_REF 57 67*4882a593Smuzhiyun #define OSPI_REF 58 68*4882a593Smuzhiyun #define SDIO0_REF 59 69*4882a593Smuzhiyun #define SDIO1_REF 60 70*4882a593Smuzhiyun #define PMC_LSBUS_REF 61 71*4882a593Smuzhiyun #define I2C_REF 62 72*4882a593Smuzhiyun #define TEST_PATTERN_REF 63 73*4882a593Smuzhiyun #define DFT_OSC_REF 64 74*4882a593Smuzhiyun #define PMC_PL0_REF 65 75*4882a593Smuzhiyun #define PMC_PL1_REF 66 76*4882a593Smuzhiyun #define PMC_PL2_REF 67 77*4882a593Smuzhiyun #define PMC_PL3_REF 68 78*4882a593Smuzhiyun #define CFU_REF 69 79*4882a593Smuzhiyun #define SPARE_REF 70 80*4882a593Smuzhiyun #define NPI_REF 71 81*4882a593Smuzhiyun #define HSM0_REF 72 82*4882a593Smuzhiyun #define HSM1_REF 73 83*4882a593Smuzhiyun #define SD_DLL_REF 74 84*4882a593Smuzhiyun #define FPD_TOP_SWITCH 75 85*4882a593Smuzhiyun #define FPD_LSBUS 76 86*4882a593Smuzhiyun #define ACPU 77 87*4882a593Smuzhiyun #define DBG_TRACE 78 88*4882a593Smuzhiyun #define DBG_FPD 79 89*4882a593Smuzhiyun #define LPD_TOP_SWITCH 80 90*4882a593Smuzhiyun #define ADMA 81 91*4882a593Smuzhiyun #define LPD_LSBUS 82 92*4882a593Smuzhiyun #define CPU_R5 83 93*4882a593Smuzhiyun #define CPU_R5_CORE 84 94*4882a593Smuzhiyun #define CPU_R5_OCM 85 95*4882a593Smuzhiyun #define CPU_R5_OCM2 86 96*4882a593Smuzhiyun #define IOU_SWITCH 87 97*4882a593Smuzhiyun #define GEM0_REF 88 98*4882a593Smuzhiyun #define GEM1_REF 89 99*4882a593Smuzhiyun #define GEM_TSU_REF 90 100*4882a593Smuzhiyun #define USB0_BUS_REF 91 101*4882a593Smuzhiyun #define UART0_REF 92 102*4882a593Smuzhiyun #define UART1_REF 93 103*4882a593Smuzhiyun #define SPI0_REF 94 104*4882a593Smuzhiyun #define SPI1_REF 95 105*4882a593Smuzhiyun #define CAN0_REF 96 106*4882a593Smuzhiyun #define CAN1_REF 97 107*4882a593Smuzhiyun #define I2C0_REF 98 108*4882a593Smuzhiyun #define I2C1_REF 99 109*4882a593Smuzhiyun #define DBG_LPD 100 110*4882a593Smuzhiyun #define TIMESTAMP_REF 101 111*4882a593Smuzhiyun #define DBG_TSTMP 102 112*4882a593Smuzhiyun #define CPM_TOPSW_REF 103 113*4882a593Smuzhiyun #define USB3_DUAL_REF 104 114*4882a593Smuzhiyun #define OUTCLK_MAX 105 115*4882a593Smuzhiyun #define REF_CLK 106 116*4882a593Smuzhiyun #define PL_ALT_REF_CLK 107 117*4882a593Smuzhiyun #define MUXED_IRO 108 118*4882a593Smuzhiyun #define PL_EXT 109 119*4882a593Smuzhiyun #define PL_LB 110 120*4882a593Smuzhiyun #define MIO_50_OR_51 111 121*4882a593Smuzhiyun #define MIO_24_OR_25 112 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #endif 124