1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ASM_ARCH_CRU_rk1808_H 7 #define _ASM_ARCH_CRU_rk1808_H 8 9 #include <common.h> 10 11 #define MHz 1000000 12 #define KHz 1000 13 #define OSC_HZ (24 * MHz) 14 #define APLL_HZ (1200 * MHz) 15 #define PCLK_PMU_HZ (100 * MHz) 16 #define GPLL_HZ (594 * MHz) 17 18 /* PX30 pll id */ 19 enum rk1808_pll_id { 20 APLL, 21 DPLL, 22 CPLL, 23 GPLL, 24 NPLL, 25 PPLL, 26 PLL_COUNT, 27 }; 28 29 struct rk1808_clk_info { 30 unsigned long id; 31 char *name; 32 bool is_cru; 33 }; 34 35 /* Private data for the clock driver - used by rockchip_get_cru() */ 36 struct rk1808_clk_priv { 37 struct rk1808_cru *cru; 38 ulong armclk_hz; 39 ulong cpll_hz; 40 ulong gpll_hz; 41 ulong npll_hz; 42 ulong armclk_enter_hz; 43 ulong armclk_init_hz; 44 bool sync_kernel; 45 bool set_armclk_rate; 46 }; 47 48 struct rk1808_pll { 49 unsigned int con0; 50 unsigned int con1; 51 unsigned int con2; 52 unsigned int con3; 53 unsigned int con4; 54 unsigned int reserved0[3]; 55 }; 56 57 struct rk1808_cru { 58 struct rk1808_pll pll[5]; 59 unsigned int mode; 60 unsigned int misc; 61 unsigned int misc1; 62 unsigned int reserved2[1]; 63 unsigned int glb_cnt_th; 64 unsigned int glb_rst_st; 65 unsigned int glb_srst_fst; 66 unsigned int glb_srst_snd; 67 unsigned int glb_rst_con; 68 unsigned int reserved3[7]; 69 unsigned int hwffc_con0; 70 unsigned int reserved4; 71 unsigned int hwffc_th; 72 unsigned int hwffc_intst; 73 unsigned int apll_con0_s; 74 unsigned int apll_con1_s; 75 unsigned int clksel_con0_s; 76 unsigned int reserved5; 77 unsigned int clksel_con[73]; 78 unsigned int reserved6[3]; 79 unsigned int clkgate_con[20]; 80 unsigned int ssgtbl[32]; 81 unsigned int softrst_con[16]; 82 unsigned int reserved7[(0x380 - 0x33c) / 4 - 1]; 83 unsigned int sdmmc_con[2]; 84 unsigned int sdio_con[2]; 85 unsigned int emmc_con[2]; 86 unsigned int reserved8[(0x400 - 0x394) / 4 - 1]; 87 unsigned int autocs_con[10]; 88 unsigned int reserved9[(0x4000 - 0x424) / 4 - 1]; 89 struct rk1808_pll pmu_pll; 90 unsigned int pmu_mode; 91 unsigned int reserved10[(0x4040 - 0x4020) / 4 - 1]; 92 unsigned int pmu_clksel_con[8]; 93 unsigned int reserved11[(0x4080 - 0x405c) / 4 - 1]; 94 unsigned int pmu_clkgate_con[2]; 95 unsigned int reserved12[(0x40c0 - 0x4084) / 4 - 1]; 96 unsigned int pmu_autocs_con[2]; 97 }; 98 99 check_member(rk1808_cru, pmu_autocs_con[0], 0x40c0); 100 101 #define RK1808_PLL_CON(x) ((x) * 0x4) 102 #define RK1808_MODE_CON 0xa0 103 #define RK1808_PMU_PLL_CON(x) ((x) * 0x4 + 0x4000) 104 #define RK1808_PMU_MODE_CON 0x4020 105 106 enum { 107 /* CRU_CLK_SEL0_CON */ 108 CORE_ACLK_DIV_SHIFT = 12, 109 CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT, 110 CORE_DBG_DIV_SHIFT = 8, 111 CORE_DBG_DIV_MASK = 0x03 << CORE_DBG_DIV_SHIFT, 112 CORE_CLK_PLL_SEL_SHIFT = 7, 113 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 114 CORE_CLK_PLL_SEL_APLL = 0, 115 CORE_CLK_PLL_SEL_GPLL, 116 CORE_DIV_CON_SHIFT = 0, 117 CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, 118 119 /* CRU_CLK_SEL4_CON */ 120 ACLK_VOP_PLL_SEL_GPLL = 0, 121 ACLK_VOP_PLL_SEL_CPLL = 1, 122 ACLK_VOP_PLL_SEL_SHIFT = 7, 123 ACLK_VOP_PLL_SEL_MASK = 1 << ACLK_VOP_PLL_SEL_SHIFT, 124 ACLK_VOP_DIV_CON_SHIFT = 0, 125 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 126 HCLK_VOP_DIV_CON_SHIFT = 8, 127 HCLK_VOP_DIV_CON_MASK = 0x1f << HCLK_VOP_DIV_CON_SHIFT, 128 129 /* CRU_CLK_SEL5_CON */ 130 DCLK_VOPRAW_SEL_VOPRAW = 0, 131 DCLK_VOPRAW_SEL_VOPRAW_FRAC = 1, 132 DCLK_VOPRAW_SEL_XIN24M = 2, 133 DCLK_VOPRAW_SEL_SHIFT = 14, 134 DCLK_VOPRAW_SEL_MASK = 3 << DCLK_VOPRAW_SEL_SHIFT, 135 DCLK_VOPRAW_PLL_SEL_CPLL = 0, 136 DCLK_VOPRAW_PLL_SEL_GPLL = 1, 137 DCLK_VOPRAW_PLL_SEL_NPLL = 2, 138 DCLK_VOPRAW_PLL_SEL_SHIFT = 10, 139 DCLK_VOPRAW_PLL_SEL_MASK = 3 << DCLK_VOPRAW_PLL_SEL_SHIFT, 140 DCLK_VOPRAW_DIV_CON_SHIFT = 0, 141 DCLK_VOPRAW_DIV_CON_MASK = 0xff << DCLK_VOPRAW_DIV_CON_SHIFT, 142 143 /* CRU_CLK_SEL7_CON */ 144 DCLK_VOPLITE_SEL_VOPRAW = 0, 145 DCLK_VOPLITE_SEL_VOPRAW_FRAC = 1, 146 DCLK_VOPLITE_SEL_XIN24M = 2, 147 DCLK_VOPLITE_SEL_SHIFT = 14, 148 DCLK_VOPLITE_SEL_MASK = 3 << DCLK_VOPLITE_SEL_SHIFT, 149 DCLK_VOPLITE_PLL_SEL_CPLL = 0, 150 DCLK_VOPLITE_PLL_SEL_GPLL = 1, 151 DCLK_VOPLITE_PLL_SEL_NPLL = 2, 152 DCLK_VOPLITE_PLL_SEL_SHIFT = 10, 153 DCLK_VOPLITE_PLL_SEL_MASK = 3 << DCLK_VOPLITE_PLL_SEL_SHIFT, 154 DCLK_VOPLITE_DIV_CON_SHIFT = 0, 155 DCLK_VOPLITE_DIV_CON_MASK = 0xff << DCLK_VOPLITE_DIV_CON_SHIFT, 156 157 /* CRU_CLK_SEL19_CON */ 158 CLK_PERI_PLL_SEL_GPLL = 0, 159 CLK_PERI_PLL_SEL_CPLL = 1, 160 CLK_PERI_PLL_SEL_SHIFT = 15, 161 CLK_PERI_PLL_SEL_MASK = 1 << CLK_PERI_PLL_SEL_SHIFT, 162 LSCLK_PERI_DIV_CON_SHIFT = 8, 163 LSCLK_PERI_DIV_CON_MASK = 0x1f << LSCLK_PERI_DIV_CON_SHIFT, 164 MSCLK_PERI_DIV_CON_SHIFT = 0, 165 MSCLK_PERI_DIV_CON_MASK = 0x1f << MSCLK_PERI_DIV_CON_SHIFT, 166 167 /* CRU_CLKSEL24_CON */ 168 EMMC_PLL_SHIFT = 14, 169 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 170 EMMC_SEL_GPLL = 0, 171 EMMC_SEL_CPLL, 172 EMMC_SEL_NPLL, 173 EMMC_SEL_24M, 174 EMMC_DIV_SHIFT = 0, 175 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 176 177 /* CRU_CLKSEL25_CON */ 178 EMMC_CLK_SEL_SHIFT = 15, 179 EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, 180 EMMC_CLK_SEL_EMMC = 0, 181 EMMC_CLK_SEL_EMMC_DIV50, 182 EMMC_DIV50_SHIFT = 0, 183 EMMC_DIV50_MASK = 0xff << EMMC_DIV_SHIFT, 184 185 /* CRU_CLKSEL26_CON */ 186 GMAC_PLL_SEL_SHIFT = 14, 187 GMAC_PLL_SEL_MASK = 3 << GMAC_PLL_SEL_SHIFT, 188 GMAC_PLL_SEL_CPLL = 0, 189 GMAC_PLL_SEL_NPLL, 190 GMAC_PLL_SEL_PPLL, 191 CLK_GMAC_DIV_SHIFT = 8, 192 CLK_GMAC_DIV_MASK = 0x1f << CLK_GMAC_DIV_SHIFT, 193 SFC_PLL_SEL_SHIFT = 7, 194 SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, 195 SFC_DIV_CON_SHIFT = 0, 196 SFC_DIV_CON_MASK = 0x7f, 197 198 /* CRU_CLK_SEL27_CON */ 199 CLK_BUS_PLL_SEL_GPLL = 0, 200 CLK_BUS_PLL_SEL_CPLL = 1, 201 CLK_BUS_PLL_SEL_SHIFT = 15, 202 CLK_BUS_PLL_SEL_MASK = 1 << CLK_BUS_PLL_SEL_SHIFT, 203 HSCLK_BUS_DIV_CON_SHIFT = 8, 204 HSCLK_BUS_DIV_CON_MASK = 0x1f << HSCLK_BUS_DIV_CON_SHIFT, 205 RGMII_CLK_SEL_SHIFT = 2, 206 RGMII_CLK_SEL_MASK = 3 << RGMII_CLK_SEL_SHIFT, 207 RGMII_CLK_SEL_125M = 0, 208 RGMII_CLK_SEL_2M = 2, 209 RGMIIC_CLK_SEL_25M = 3, 210 RMII_CLK_SEL_SHIFT = 1, 211 RMII_CLK_SEL_MASK = 1 << RMII_CLK_SEL_SHIFT, 212 RMII_EXTCLK_SEL_SHIFT = 0, 213 RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, 214 RMII_EXTCLK_SEL_INT = 0, 215 RMII_EXTCLK_SEL_EXT, 216 217 /* CRU_CLK_SEL28_CON */ 218 MSCLK_BUS_DIV_CON_SHIFT = 8, 219 MSCLK_BUS_DIV_CON_MASK = 0x1f << MSCLK_BUS_DIV_CON_SHIFT, 220 LSCLK_BUS_DIV_CON_SHIFT = 0, 221 LSCLK_BUS_DIV_CON_MASK = 0x1f << LSCLK_BUS_DIV_CON_SHIFT, 222 223 /* CRU_CLK_SEL29_CON */ 224 CRYPTO_APK_SEL_SHIFT = 15, 225 CRYPTO_APK_PLL_SEL_MASK = 1 << CRYPTO_APK_SEL_SHIFT, 226 CRYPTO_PLL_SEL_GPLL = 0, 227 CRYPTO_PLL_SEL_CPLL, 228 CRYPTO_APK_DIV_SHIFT = 8, 229 CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT, 230 CRYPTO_PLL_SEL_SHIFT = 7, 231 CRYPTO_PLL_SEL_MASK = 1 << CRYPTO_PLL_SEL_SHIFT, 232 CRYPTO_DIV_SHIFT = 0, 233 CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT, 234 235 /* CRU_CLK_SEL59_CON */ 236 CLK_I2C_PLL_SEL_GPLL = 0, 237 CLK_I2C_PLL_SEL_24M, 238 CLK_I2C2_PLL_SEL_SHIFT = 15, 239 CLK_I2C2_DIV_CON_SHIFT = 8, 240 CLK_I2C2_DIV_CON_MASK = 0x7f << CLK_I2C2_DIV_CON_SHIFT, 241 CLK_I2C2_PLL_SEL_MASK = 1 << CLK_I2C2_PLL_SEL_SHIFT, 242 CLK_I2C1_PLL_SEL_SHIFT = 7, 243 CLK_I2C1_DIV_CON_SHIFT = 0, 244 CLK_I2C1_DIV_CON_MASK = 0x7f, 245 CLK_I2C1_PLL_SEL_MASK = 1 << CLK_I2C1_PLL_SEL_SHIFT, 246 247 /* CRU_CLK_SEL60_CON */ 248 CLK_SPI_PLL_SEL_GPLL = 0, 249 CLK_SPI_PLL_SEL_24M, 250 CLK_SPI0_PLL_SEL_SHIFT = 15, 251 CLK_SPI0_DIV_CON_SHIFT = 8, 252 CLK_SPI0_DIV_CON_MASK = 0x7f << CLK_SPI0_DIV_CON_SHIFT, 253 CLK_SPI0_PLL_SEL_MASK = 1 << CLK_SPI0_PLL_SEL_SHIFT, 254 CLK_I2C3_PLL_SEL_SHIFT = 7, 255 CLK_I2C3_DIV_CON_SHIFT = 0, 256 CLK_I2C3_DIV_CON_MASK = 0x7f, 257 CLK_I2C3_PLL_SEL_MASK = 1 << CLK_I2C3_PLL_SEL_SHIFT, 258 259 /* CRU_CLK_SEL61_CON */ 260 CLK_SPI2_PLL_SEL_SHIFT = 15, 261 CLK_SPI2_DIV_CON_SHIFT = 8, 262 CLK_SPI2_DIV_CON_MASK = 0x7f << CLK_SPI2_DIV_CON_SHIFT, 263 CLK_SPI2_PLL_SEL_MASK = 1 << CLK_SPI2_PLL_SEL_SHIFT, 264 CLK_SPI1_PLL_SEL_SHIFT = 7, 265 CLK_SPI1_DIV_CON_SHIFT = 0, 266 CLK_SPI1_DIV_CON_MASK = 0x7f, 267 CLK_SPI1_PLL_SEL_MASK = 1 << CLK_SPI1_PLL_SEL_SHIFT, 268 269 /* CRU_CLK_SEL62_CON */ 270 CLK_TSADC_DIV_CON_SHIFT = 0, 271 CLK_TSADC_DIV_CON_MASK = 0x3ff, 272 273 /* CRU_CLK_SEL63_CON */ 274 CLK_SARADC_DIV_CON_SHIFT = 0, 275 CLK_SARADC_DIV_CON_MASK = 0x3ff, 276 277 /* CRU_CLK_SEL69_CON */ 278 CLK_PWM_PLL_SEL_GPLL = 0, 279 CLK_PWM_PLL_SEL_24M, 280 CLK_PWM1_PLL_SEL_SHIFT = 15, 281 CLK_PWM1_DIV_CON_SHIFT = 8, 282 CLK_PWM1_DIV_CON_MASK = 0x7f << CLK_PWM1_DIV_CON_SHIFT, 283 CLK_PWM1_PLL_SEL_MASK = 1 << CLK_PWM1_PLL_SEL_SHIFT, 284 CLK_PWM0_PLL_SEL_SHIFT = 7, 285 CLK_PWM0_DIV_CON_SHIFT = 0, 286 CLK_PWM0_DIV_CON_MASK = 0x7f, 287 CLK_PWM0_PLL_SEL_MASK = 1 << CLK_PWM0_PLL_SEL_SHIFT, 288 289 /* CRU_CLK_SEL70_CON */ 290 CLK_PWM2_PLL_SEL_SHIFT = 7, 291 CLK_PWM2_DIV_CON_SHIFT = 0, 292 CLK_PWM2_DIV_CON_MASK = 0x7f, 293 CLK_PWM2_PLL_SEL_MASK = 1 << CLK_PWM2_PLL_SEL_SHIFT, 294 295 /* CRU_CLK_SEL71_CON */ 296 CLK_I2C5_PLL_SEL_SHIFT = 15, 297 CLK_I2C5_DIV_CON_SHIFT = 8, 298 CLK_I2C5_DIV_CON_MASK = 0x7f << CLK_I2C5_DIV_CON_SHIFT, 299 CLK_I2C5_PLL_SEL_MASK = 1 << CLK_I2C5_PLL_SEL_SHIFT, 300 CLK_I2C4_PLL_SEL_SHIFT = 7, 301 CLK_I2C4_DIV_CON_SHIFT = 0, 302 CLK_I2C4_DIV_CON_MASK = 0x7f, 303 CLK_I2C4_PLL_SEL_MASK = 1 << CLK_I2C4_PLL_SEL_SHIFT, 304 305 /* CRU_PMU_CLK_SEL7_CON */ 306 CLK_I2C0_PLL_SEL_PPLL = 0, 307 CLK_I2C0_PLL_SEL_SHIFT = 15, 308 CLK_I2C0_DIV_CON_SHIFT = 8, 309 CLK_I2C0_PLL_SEL_MASK = 1 << CLK_I2C0_PLL_SEL_SHIFT, 310 CLK_I2C0_DIV_CON_MASK = 0x3f << CLK_I2C0_DIV_CON_SHIFT, 311 312 /* PMUCRU_CLK_SEL0_CON */ 313 PCLK_PMU_DIV_CON_SHIFT = 0, 314 PCLK_PMU_DIV_CON_MASK = 0x1f << PCLK_PMU_DIV_CON_SHIFT, 315 }; 316 #endif 317