1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _ASM_ARCH_CRU_RK322X_H 7*4882a593Smuzhiyun #define _ASM_ARCH_CRU_RK322X_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <common.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define MHz 1000 * 1000 12*4882a593Smuzhiyun #define OSC_HZ (24 * MHz) 13*4882a593Smuzhiyun #define APLL_HZ (600 * MHz) 14*4882a593Smuzhiyun #define GPLL_HZ (1200 * MHz) 15*4882a593Smuzhiyun #define CPLL_HZ (500 * MHz) 16*4882a593Smuzhiyun #define ACLK_BUS_HZ (150 * MHz) 17*4882a593Smuzhiyun #define ACLK_PERI_HZ (150 * MHz) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Private data for the clock driver - used by rockchip_get_cru() */ 20*4882a593Smuzhiyun struct rk322x_clk_priv { 21*4882a593Smuzhiyun struct rk322x_cru *cru; 22*4882a593Smuzhiyun ulong gpll_hz; 23*4882a593Smuzhiyun ulong cpll_hz; 24*4882a593Smuzhiyun ulong armclk_hz; 25*4882a593Smuzhiyun ulong armclk_enter_hz; 26*4882a593Smuzhiyun ulong armclk_init_hz; 27*4882a593Smuzhiyun bool sync_kernel; 28*4882a593Smuzhiyun bool set_armclk_rate; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun struct rk322x_cru { 32*4882a593Smuzhiyun struct rk322x_pll { 33*4882a593Smuzhiyun unsigned int con0; 34*4882a593Smuzhiyun unsigned int con1; 35*4882a593Smuzhiyun unsigned int con2; 36*4882a593Smuzhiyun } pll[4]; 37*4882a593Smuzhiyun unsigned int reserved0[4]; 38*4882a593Smuzhiyun unsigned int cru_mode_con; 39*4882a593Smuzhiyun unsigned int cru_clksel_con[35]; 40*4882a593Smuzhiyun unsigned int cru_clkgate_con[16]; 41*4882a593Smuzhiyun unsigned int cru_softrst_con[9]; 42*4882a593Smuzhiyun unsigned int cru_misc_con; 43*4882a593Smuzhiyun unsigned int reserved1[2]; 44*4882a593Smuzhiyun unsigned int cru_glb_cnt_th; 45*4882a593Smuzhiyun unsigned int reserved2[3]; 46*4882a593Smuzhiyun unsigned int cru_glb_rst_st; 47*4882a593Smuzhiyun unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1]; 48*4882a593Smuzhiyun unsigned int cru_sdmmc_con[2]; 49*4882a593Smuzhiyun unsigned int cru_sdio_con[2]; 50*4882a593Smuzhiyun unsigned int reserved4[2]; 51*4882a593Smuzhiyun unsigned int cru_emmc_con[2]; 52*4882a593Smuzhiyun unsigned int reserved5[4]; 53*4882a593Smuzhiyun unsigned int cru_glb_srst_fst_value; 54*4882a593Smuzhiyun unsigned int cru_glb_srst_snd_value; 55*4882a593Smuzhiyun unsigned int cru_pll_mask_con; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun check_member(rk322x_cru, cru_pll_mask_con, 0x01f8); 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun enum rk322x_pll_id { 60*4882a593Smuzhiyun APLL, 61*4882a593Smuzhiyun DPLL, 62*4882a593Smuzhiyun CPLL, 63*4882a593Smuzhiyun GPLL, 64*4882a593Smuzhiyun NPLL, 65*4882a593Smuzhiyun PLL_COUNT, 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun struct rk322x_clk_info { 69*4882a593Smuzhiyun unsigned long id; 70*4882a593Smuzhiyun char *name; 71*4882a593Smuzhiyun bool is_cru; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define RK2928_PLL_CON(x) ((x) * 0x4) 75*4882a593Smuzhiyun #define RK2928_MODE_CON 0x40 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun enum { 78*4882a593Smuzhiyun /* CRU_CLK_SEL0_CON */ 79*4882a593Smuzhiyun BUS_ACLK_PLL_SEL_SHIFT = 13, 80*4882a593Smuzhiyun BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, 81*4882a593Smuzhiyun BUS_ACLK_PLL_SEL_CPLL = 0, 82*4882a593Smuzhiyun BUS_ACLK_PLL_SEL_GPLL, 83*4882a593Smuzhiyun BUS_ACLK_PLL_SEL_HDMIPLL, 84*4882a593Smuzhiyun BUS_ACLK_DIV_SHIFT = 8, 85*4882a593Smuzhiyun BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 86*4882a593Smuzhiyun CORE_CLK_PLL_SEL_SHIFT = 6, 87*4882a593Smuzhiyun CORE_CLK_PLL_SEL_MASK = 3 << CORE_CLK_PLL_SEL_SHIFT, 88*4882a593Smuzhiyun CORE_CLK_PLL_SEL_APLL = 0, 89*4882a593Smuzhiyun CORE_CLK_PLL_SEL_GPLL, 90*4882a593Smuzhiyun CORE_CLK_PLL_SEL_DPLL, 91*4882a593Smuzhiyun CORE_DIV_CON_SHIFT = 0, 92*4882a593Smuzhiyun CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* CRU_CLK_SEL1_CON */ 95*4882a593Smuzhiyun BUS_PCLK_DIV_SHIFT = 12, 96*4882a593Smuzhiyun BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, 97*4882a593Smuzhiyun BUS_HCLK_DIV_SHIFT = 8, 98*4882a593Smuzhiyun BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, 99*4882a593Smuzhiyun CORE_ACLK_DIV_SHIFT = 4, 100*4882a593Smuzhiyun CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, 101*4882a593Smuzhiyun CORE_PERI_DIV_SHIFT = 0, 102*4882a593Smuzhiyun CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* CRU_CLKSEL5_CON */ 105*4882a593Smuzhiyun GMAC_OUT_PLL_SHIFT = 15, 106*4882a593Smuzhiyun GMAC_OUT_PLL_MASK = 1 << GMAC_OUT_PLL_SHIFT, 107*4882a593Smuzhiyun GMAC_OUT_DIV_SHIFT = 8, 108*4882a593Smuzhiyun GMAC_OUT_DIV_MASK = 0x1f << GMAC_OUT_DIV_SHIFT, 109*4882a593Smuzhiyun MAC_PLL_SEL_SHIFT = 7, 110*4882a593Smuzhiyun MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, 111*4882a593Smuzhiyun RMII_EXTCLK_SLE_SHIFT = 5, 112*4882a593Smuzhiyun RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SLE_SHIFT, 113*4882a593Smuzhiyun RMII_EXTCLK_SEL_INT = 0, 114*4882a593Smuzhiyun RMII_EXTCLK_SEL_EXT, 115*4882a593Smuzhiyun CLK_MAC_DIV_SHIFT = 0, 116*4882a593Smuzhiyun CLK_MAC_DIV_MASK = 0x1f << CLK_MAC_DIV_SHIFT, 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* CRU_CLKSEL10_CON */ 119*4882a593Smuzhiyun PERI_PCLK_DIV_SHIFT = 12, 120*4882a593Smuzhiyun PERI_PCLK_DIV_MASK = 7 << PERI_PCLK_DIV_SHIFT, 121*4882a593Smuzhiyun PERI_PLL_SEL_SHIFT = 10, 122*4882a593Smuzhiyun PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, 123*4882a593Smuzhiyun PERI_PLL_CPLL = 0, 124*4882a593Smuzhiyun PERI_PLL_GPLL, 125*4882a593Smuzhiyun PERI_PLL_HDMIPLL, 126*4882a593Smuzhiyun PERI_HCLK_DIV_SHIFT = 8, 127*4882a593Smuzhiyun PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, 128*4882a593Smuzhiyun PERI_ACLK_DIV_SHIFT = 0, 129*4882a593Smuzhiyun PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* CRU_CLKSEL11_CON */ 132*4882a593Smuzhiyun EMMC_PLL_SHIFT = 12, 133*4882a593Smuzhiyun EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 134*4882a593Smuzhiyun EMMC_SEL_CPLL = 0, 135*4882a593Smuzhiyun EMMC_SEL_GPLL, 136*4882a593Smuzhiyun EMMC_SEL_24M, 137*4882a593Smuzhiyun SDIO_PLL_SHIFT = 10, 138*4882a593Smuzhiyun SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, 139*4882a593Smuzhiyun SDIO_SEL_CPLL = 0, 140*4882a593Smuzhiyun SDIO_SEL_GPLL, 141*4882a593Smuzhiyun SDIO_SEL_24M, 142*4882a593Smuzhiyun MMC0_PLL_SHIFT = 8, 143*4882a593Smuzhiyun MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, 144*4882a593Smuzhiyun MMC0_SEL_CPLL = 0, 145*4882a593Smuzhiyun MMC0_SEL_GPLL, 146*4882a593Smuzhiyun MMC0_SEL_24M, 147*4882a593Smuzhiyun MMC0_DIV_SHIFT = 0, 148*4882a593Smuzhiyun MMC0_DIV_MASK = 0xff << MMC0_DIV_SHIFT, 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun /* CRU_CLKSEL12_CON */ 151*4882a593Smuzhiyun EMMC_DIV_SHIFT = 8, 152*4882a593Smuzhiyun EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 153*4882a593Smuzhiyun SDIO_DIV_SHIFT = 0, 154*4882a593Smuzhiyun SDIO_DIV_MASK = 0xff << SDIO_DIV_SHIFT, 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* CLKSEL_CON24 */ 157*4882a593Smuzhiyun CRYPTO_PLL_SEL_SHIFT = 5, 158*4882a593Smuzhiyun CRYPTO_PLL_SEL_MASK = 0x1 << CRYPTO_PLL_SEL_SHIFT, 159*4882a593Smuzhiyun CRYPTO_PLL_SEL_CPLL = 0, 160*4882a593Smuzhiyun CRYPTO_PLL_SEL_GPLL, 161*4882a593Smuzhiyun CRYPTO_DIV_SHIFT = 0, 162*4882a593Smuzhiyun CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT, 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun /* CLKSEL_CON25 */ 165*4882a593Smuzhiyun SPI_PLL_SEL_SHIFT = 8, 166*4882a593Smuzhiyun SPI_PLL_SEL_MASK = 0x1 << SPI_PLL_SEL_SHIFT, 167*4882a593Smuzhiyun SPI_PLL_SEL_CPLL = 0, 168*4882a593Smuzhiyun SPI_PLL_SEL_GPLL, 169*4882a593Smuzhiyun SPI_DIV_SHIFT = 0, 170*4882a593Smuzhiyun SPI_DIV_MASK = 0x7f << SPI_DIV_SHIFT, 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /* CRU_CLKSEL26_CON */ 173*4882a593Smuzhiyun DDR_CLK_PLL_SEL_SHIFT = 8, 174*4882a593Smuzhiyun DDR_CLK_PLL_SEL_MASK = 3 << DDR_CLK_PLL_SEL_SHIFT, 175*4882a593Smuzhiyun DDR_CLK_SEL_DPLL = 0, 176*4882a593Smuzhiyun DDR_CLK_SEL_GPLL, 177*4882a593Smuzhiyun DDR_CLK_SEL_APLL, 178*4882a593Smuzhiyun DDR_DIV_SEL_SHIFT = 0, 179*4882a593Smuzhiyun DDR_DIV_SEL_MASK = 3 << DDR_DIV_SEL_SHIFT, 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun /* CRU_CLKSEL27_CON */ 182*4882a593Smuzhiyun DCLK_LCDC_PLL_SEL_GPLL = 0, 183*4882a593Smuzhiyun DCLK_LCDC_PLL_SEL_CPLL = 1, 184*4882a593Smuzhiyun DCLK_LCDC_PLL_SEL_SHIFT = 0, 185*4882a593Smuzhiyun DCLK_LCDC_PLL_SEL_MASK = 1 << DCLK_LCDC_PLL_SEL_SHIFT, 186*4882a593Smuzhiyun DCLK_LCDC_SEL_HDMIPHY = 0, 187*4882a593Smuzhiyun DCLK_LCDC_SEL_PLL = 1, 188*4882a593Smuzhiyun DCLK_LCDC_SEL_SHIFT = 1, 189*4882a593Smuzhiyun DCLK_LCDC_SEL_MASK = 1 << DCLK_LCDC_SEL_SHIFT, 190*4882a593Smuzhiyun DCLK_LCDC_DIV_CON_SHIFT = 8, 191*4882a593Smuzhiyun DCLK_LCDC_DIV_CON_MASK = 0xFf << DCLK_LCDC_DIV_CON_SHIFT, 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun /* CRU_CLKSEL29_CON */ 194*4882a593Smuzhiyun GMAC_CLK_SRC_SHIFT = 12, 195*4882a593Smuzhiyun GMAC_CLK_SRC_MASK = 1 << GMAC_CLK_SRC_SHIFT, 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun /* CRU_CLKSEL33_CON */ 198*4882a593Smuzhiyun ACLK_VOP_PLL_SEL_SHIFT = 5, 199*4882a593Smuzhiyun ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT, 200*4882a593Smuzhiyun ACLK_VOP_PLL_SEL_CPLL = 0, 201*4882a593Smuzhiyun ACLK_VOP_PLL_SEL_GPLL = 1, 202*4882a593Smuzhiyun ACLK_VOP_PLL_SEL_HDMIPHY = 2, 203*4882a593Smuzhiyun ACLK_VOP_DIV_CON_SHIFT = 0, 204*4882a593Smuzhiyun ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun /* CRU_SOFTRST5_CON */ 207*4882a593Smuzhiyun DDRCTRL_PSRST_SHIFT = 11, 208*4882a593Smuzhiyun DDRCTRL_SRST_SHIFT = 10, 209*4882a593Smuzhiyun DDRPHY_PSRST_SHIFT = 9, 210*4882a593Smuzhiyun DDRPHY_SRST_SHIFT = 8, 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun #endif 213