1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010 Samsung Electronics 3*4882a593Smuzhiyun * Minkyu Kang <mk7.kang@samsung.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_ARM_ARCH_CLK_H_ 9*4882a593Smuzhiyun #define __ASM_ARM_ARCH_CLK_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define APLL 0 12*4882a593Smuzhiyun #define MPLL 1 13*4882a593Smuzhiyun #define EPLL 2 14*4882a593Smuzhiyun #define HPLL 3 15*4882a593Smuzhiyun #define VPLL 4 16*4882a593Smuzhiyun #define BPLL 5 17*4882a593Smuzhiyun #define RPLL 6 18*4882a593Smuzhiyun #define SPLL 7 19*4882a593Smuzhiyun #define CPLL 8 20*4882a593Smuzhiyun #define DPLL 9 21*4882a593Smuzhiyun #define IPLL 10 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8)) 24*4882a593Smuzhiyun #define MASK_RATIO(x) (0xf << (x << 4)) 25*4882a593Smuzhiyun #define SET_PRE_RATIO(x, y) ((y & 0xff) << ((x << 4) + 8)) 26*4882a593Smuzhiyun #define SET_RATIO(x, y) ((y & 0xf) << (x << 4)) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun enum pll_src_bit { 29*4882a593Smuzhiyun EXYNOS_SRC_MPLL = 6, 30*4882a593Smuzhiyun EXYNOS_SRC_EPLL, 31*4882a593Smuzhiyun EXYNOS_SRC_VPLL, 32*4882a593Smuzhiyun EXYNOS542X_SRC_MPLL = 3, 33*4882a593Smuzhiyun EXYNOS542X_SRC_SPLL, 34*4882a593Smuzhiyun EXYNOS542X_SRC_EPLL = 6, 35*4882a593Smuzhiyun EXYNOS542X_SRC_RPLL, 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun unsigned long get_pll_clk(int pllreg); 39*4882a593Smuzhiyun unsigned long get_arm_clk(void); 40*4882a593Smuzhiyun unsigned long get_i2c_clk(void); 41*4882a593Smuzhiyun unsigned long get_pwm_clk(void); 42*4882a593Smuzhiyun unsigned long get_uart_clk(int dev_index); 43*4882a593Smuzhiyun unsigned long get_mmc_clk(int dev_index); 44*4882a593Smuzhiyun void set_mmc_clk(int dev_index, unsigned int div); 45*4882a593Smuzhiyun unsigned long get_lcd_clk(void); 46*4882a593Smuzhiyun void set_lcd_clk(void); 47*4882a593Smuzhiyun void set_mipi_clk(void); 48*4882a593Smuzhiyun int set_i2s_clk_source(unsigned int i2s_id); 49*4882a593Smuzhiyun int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq, 50*4882a593Smuzhiyun unsigned int i2s_id); 51*4882a593Smuzhiyun int set_epll_clk(unsigned long rate); 52*4882a593Smuzhiyun int set_spi_clk(int periph_id, unsigned int rate); 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /** 55*4882a593Smuzhiyun * get the clk frequency of the required peripheral 56*4882a593Smuzhiyun * 57*4882a593Smuzhiyun * @param peripheral Peripheral id 58*4882a593Smuzhiyun * 59*4882a593Smuzhiyun * @return frequency of the peripheral clk 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun unsigned long clock_get_periph_rate(int peripheral); 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #endif 64