1*4882a593SmuzhiyunBinding for Texas Instruments APLL clock. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunBinding status: Unstable - ABI compatibility may be broken in the future 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunThis binding uses the common clock binding[1]. It assumes a 6*4882a593Smuzhiyunregister-mapped APLL with usually two selectable input clocks 7*4882a593Smuzhiyun(reference clock and bypass clock), with analog phase locked 8*4882a593Smuzhiyunloop logic for multiplying the input clock to a desired output 9*4882a593Smuzhiyunclock. This clock also typically supports different operation 10*4882a593Smuzhiyunmodes (locked, low power stop etc.) APLL mostly behaves like 11*4882a593Smuzhiyuna subtype of a DPLL [2], although a simplified one at that. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 14*4882a593Smuzhiyun[2] Documentation/devicetree/bindings/clock/ti/dpll.txt 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunRequired properties: 17*4882a593Smuzhiyun- compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock" 18*4882a593Smuzhiyun- #clock-cells : from common clock binding; shall be set to 0. 19*4882a593Smuzhiyun- clocks : link phandles of parent clocks (clk-ref and clk-bypass) 20*4882a593Smuzhiyun- reg : address and length of the register set for controlling the APLL. 21*4882a593Smuzhiyun It contains the information of registers in the following order: 22*4882a593Smuzhiyun "control" - contains the control register offset 23*4882a593Smuzhiyun "idlest" - contains the idlest register offset 24*4882a593Smuzhiyun "autoidle" - contains the autoidle register offset (OMAP2 only) 25*4882a593Smuzhiyun- ti,clock-frequency : static clock frequency for the clock (OMAP2 only) 26*4882a593Smuzhiyun- ti,idlest-shift : bit-shift for the idlest field (OMAP2 only) 27*4882a593Smuzhiyun- ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only) 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunExamples: 30*4882a593Smuzhiyun apll_pcie_ck: apll_pcie_ck { 31*4882a593Smuzhiyun #clock-cells = <0>; 32*4882a593Smuzhiyun clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; 33*4882a593Smuzhiyun reg = <0x021c>, <0x0220>; 34*4882a593Smuzhiyun compatible = "ti,dra7-apll-clock"; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun apll96_ck: apll96_ck { 38*4882a593Smuzhiyun #clock-cells = <0>; 39*4882a593Smuzhiyun compatible = "ti,omap2-apll-clock"; 40*4882a593Smuzhiyun clocks = <&sys_ck>; 41*4882a593Smuzhiyun ti,bit-shift = <2>; 42*4882a593Smuzhiyun ti,idlest-shift = <8>; 43*4882a593Smuzhiyun ti,clock-frequency = <96000000>; 44*4882a593Smuzhiyun reg = <0x0500>, <0x0530>, <0x0520>; 45*4882a593Smuzhiyun }; 46