1 /* 2 * Copyright (c) 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RK3128_H 8 #define _ASM_ARCH_CRU_RK3128_H 9 10 #include <common.h> 11 12 #define MHz 1000000 13 #define OSC_HZ (24 * MHz) 14 15 #define APLL_HZ (600 * MHz) 16 #define GPLL_HZ (594 * MHz) 17 #define CPLL_HZ (400 * MHz) 18 #define ACLK_BUS_HZ (148500000) 19 #define ACLK_PERI_HZ (148500000) 20 21 /* Private data for the clock driver - used by rockchip_get_cru() */ 22 struct rk3128_clk_priv { 23 struct rk3128_cru *cru; 24 ulong gpll_hz; 25 ulong armclk_hz; 26 ulong armclk_enter_hz; 27 ulong armclk_init_hz; 28 bool sync_kernel; 29 bool set_armclk_rate; 30 }; 31 32 struct rk3128_cru { 33 struct rk3128_pll { 34 unsigned int con0; 35 unsigned int con1; 36 unsigned int con2; 37 unsigned int con3; 38 } pll[4]; 39 unsigned int cru_mode_con; 40 unsigned int cru_clksel_con[35]; 41 unsigned int cru_clkgate_con[11]; 42 unsigned int reserved; 43 unsigned int cru_glb_srst_fst_value; 44 unsigned int cru_glb_srst_snd_value; 45 unsigned int reserved1[2]; 46 unsigned int cru_softrst_con[9]; 47 unsigned int cru_misc_con; 48 unsigned int reserved2[2]; 49 unsigned int cru_glb_cnt_th; 50 unsigned int reserved3[3]; 51 unsigned int cru_glb_rst_st; 52 unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1]; 53 unsigned int cru_sdmmc_con[2]; 54 unsigned int cru_sdio_con[2]; 55 unsigned int reserved5[2]; 56 unsigned int cru_emmc_con[2]; 57 unsigned int reserved6[4]; 58 unsigned int cru_pll_prg_en; 59 }; 60 check_member(rk3128_cru, cru_pll_prg_en, 0x01f0); 61 62 enum rk3128_pll_id { 63 APLL, 64 DPLL, 65 CPLL, 66 GPLL, 67 PLL_COUNT, 68 }; 69 70 struct rk3128_clk_info { 71 unsigned long id; 72 char *name; 73 bool is_cru; 74 }; 75 76 #define RK2928_PLL_CON(x) ((x) * 0x4) 77 #define RK2928_MODE_CON 0x40 78 79 enum { 80 /* CRU_CLK_SEL0_CON */ 81 BUS_PLL_SEL_SHIFT = 13, 82 BUS_PLL_SEL_MASK = 3 << BUS_PLL_SEL_SHIFT, 83 BUS_PLL_SEL_CPLL = 0, 84 BUS_PLL_SEL_GPLL, 85 BUS_PLL_SEL_GPLL_DIV2, 86 BUS_PLL_SEL_GPLL_DIV3, 87 ACLK_BUS_DIV_SHIFT = 8, 88 ACLK_BUS_DIV_MASK = 0x1f << ACLK_BUS_DIV_SHIFT, 89 CORE_CLK_PLL_SEL_SHIFT = 7, 90 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 91 CORE_CLK_PLL_SEL_APLL = 0, 92 CORE_CLK_PLL_SEL_GPLL_DIV2, 93 CORE_DIV_CON_SHIFT = 0, 94 CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 95 96 /* CRU_CLK_SEL1_CON */ 97 PCLK_BUS_DIV_SHIFT = 12, 98 PCLK_BUS_DIV_MASK = 7 << PCLK_BUS_DIV_SHIFT, 99 HCLK_BUS_DIV_SHIFT = 8, 100 HCLK_BUS_DIV_MASK = 3 << HCLK_BUS_DIV_SHIFT, 101 CORE_ACLK_DIV_SHIFT = 4, 102 CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT, 103 CORE_DBG_DIV_SHIFT = 0, 104 CORE_DBG_DIV_MASK = 0x0f << CORE_DBG_DIV_SHIFT, 105 106 /* CRU_CLK_SEL2_CON */ 107 NANDC_PLL_SEL_SHIFT = 14, 108 NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT, 109 NANDC_PLL_SEL_CPLL = 0, 110 NANDC_PLL_SEL_GPLL, 111 NANDC_CLK_DIV_SHIFT = 8, 112 NANDC_CLK_DIV_MASK = 0x1f << NANDC_CLK_DIV_SHIFT, 113 PVTM_CLK_DIV_SHIFT = 0, 114 PVTM_CLK_DIV_MASK = 0x3f << PVTM_CLK_DIV_SHIFT, 115 116 /* CRU_CLKSEL10_CON */ 117 PERI_PLL_SEL_SHIFT = 14, 118 PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, 119 PERI_PLL_SEL_GPLL = 0, 120 PERI_PLL_SEL_CPLL, 121 PERI_PLL_SEL_GPLL_DIV2, 122 PERI_PLL_SEL_GPLL_DIV3, 123 PCLK_PERI_DIV_SHIFT = 12, 124 PCLK_PERI_DIV_MASK = 3 << PCLK_PERI_DIV_SHIFT, 125 HCLK_PERI_DIV_SHIFT = 8, 126 HCLK_PERI_DIV_MASK = 3 << HCLK_PERI_DIV_SHIFT, 127 ACLK_PERI_DIV_SHIFT = 0, 128 ACLK_PERI_DIV_MASK = 0x1f << ACLK_PERI_DIV_SHIFT, 129 130 /* CRU_CLKSEL11_CON */ 131 SFC_PLL_SEL_SHIFT = 14, 132 SFC_PLL_SEL_MASK = 3 << SFC_PLL_SEL_SHIFT, 133 SFC_PLL_SEL_CPLL = 0, 134 SFC_PLL_SEL_GPLL, 135 SFC_CLK_DIV_SHIFT = 8, 136 SFC_CLK_DIV_MASK = 0x1f << SFC_CLK_DIV_SHIFT, 137 MMC0_PLL_SHIFT = 6, 138 MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, 139 MMC0_SEL_APLL = 0, 140 MMC0_SEL_GPLL, 141 MMC0_SEL_GPLL_DIV2, 142 MMC0_SEL_24M, 143 MMC0_DIV_SHIFT = 0, 144 MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, 145 146 /* CRU_CLKSEL12_CON */ 147 EMMC_PLL_SHIFT = 14, 148 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 149 EMMC_SEL_APLL = 0, 150 EMMC_SEL_GPLL, 151 EMMC_SEL_GPLL_DIV2, 152 EMMC_SEL_24M, 153 EMMC_DIV_SHIFT = 8, 154 EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT, 155 SDIO_PLL_SHIFT = 6, 156 SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, 157 SDIO_SEL_APLL = 0, 158 SDIO_SEL_GPLL, 159 SDIO_SEL_GPLL_DIV2, 160 SDIO_SEL_24M, 161 SDIO_DIV_SHIFT = 0, 162 SDIO_DIV_MASK = 0x3f << SDIO_DIV_SHIFT, 163 164 /* CLKSEL_CON24 */ 165 SARADC_DIV_CON_SHIFT = 8, 166 SARADC_DIV_CON_MASK = GENMASK(15, 8), 167 SARADC_DIV_CON_WIDTH = 8, 168 CLK_CRYPTO_DIV_CON_SHIFT= 0, 169 CLK_CRYPTO_DIV_CON_MASK = GENMASK(1, 0), 170 171 /* CLKSEL_CON25 */ 172 SPI_PLL_SEL_SHIFT = 8, 173 SPI_PLL_SEL_MASK = 0x3 << SPI_PLL_SEL_SHIFT, 174 SPI_PLL_SEL_CPLL = 0, 175 SPI_PLL_SEL_GPLL, 176 SPI_PLL_SEL_GPLL_DIV2, 177 SPI_DIV_SHIFT = 0, 178 SPI_DIV_MASK = 0x7f << SPI_DIV_SHIFT, 179 180 /* CRU_CLKSEL27_CON*/ 181 DCLK_VOP_SEL_SHIFT = 0, 182 DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, 183 DCLK_VOP_PLL_SEL_CPLL = 0, 184 DCLK_VOP_DIV_CON_SHIFT = 8, 185 DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT, 186 187 /* CRU_CLKSEL31_CON */ 188 VIO0_PLL_SHIFT = 5, 189 VIO0_PLL_MASK = 7 << VIO0_PLL_SHIFT, 190 VI00_SEL_CPLL = 0, 191 VIO0_SEL_GPLL, 192 VIO0_DIV_SHIFT = 0, 193 VIO0_DIV_MASK = 0x1f << VIO0_DIV_SHIFT, 194 VIO1_PLL_SHIFT = 13, 195 VIO1_PLL_MASK = 7 << VIO1_PLL_SHIFT, 196 VI01_SEL_CPLL = 0, 197 VIO1_SEL_GPLL, 198 VIO1_DIV_SHIFT = 8, 199 VIO1_DIV_MASK = 0x1f << VIO1_DIV_SHIFT, 200 201 /* CRU_SOFTRST5_CON */ 202 DDRCTRL_PSRST_SHIFT = 11, 203 DDRCTRL_SRST_SHIFT = 10, 204 DDRPHY_PSRST_SHIFT = 9, 205 DDRPHY_SRST_SHIFT = 8, 206 }; 207 #endif 208