clk/rockchip/clk_rv1126.c

60 	[APLL] = PLL(pll_rk3328, PLL_APLL, RV1126_PLL_CON(0),
573 	old_rate = rockchip_pll_get_rate(&rv1126_pll_clks[APLL],  in rv1126_armclk_set_clk()
574 					 priv->cru, APLL);  in rv1126_armclk_set_clk()
576 		if (rockchip_pll_set_rate(&rv1126_pll_clks[APLL],  in rv1126_armclk_set_clk()
577 					  priv->cru, APLL, hz))  in rv1126_armclk_set_clk()
588 		if (rockchip_pll_set_rate(&rv1126_pll_clks[APLL],  in rv1126_armclk_set_clk()
589 					  priv->cru, APLL, hz))  in rv1126_armclk_set_clk()
1625 		rate = rockchip_pll_get_rate(&rv1126_pll_clks[APLL], priv->cru,  in rv1126_clk_get_rate()
1626 					     APLL);  in rv1126_clk_get_rate()
2136 			rockchip_pll_get_rate(&rv1126_pll_clks[APLL],  in rv1126_clk_init()
2137 					      priv->cru, APLL);  in rv1126_clk_init()