81 	[APLL] = PLL(pll_rk3036, PLL_APLL, RK2928_PLL_CON(0),
108 	old_rate = rockchip_pll_get_rate(&rk3128_pll_clks[APLL],  in rk3128_armclk_set_clk()
109 					 priv->cru, APLL);  in rk3128_armclk_set_clk()
111 		if (rockchip_pll_set_rate(&rk3128_pll_clks[APLL],  in rk3128_armclk_set_clk()
112 					  priv->cru, APLL, hz))  in rk3128_armclk_set_clk()
131 		if (rockchip_pll_set_rate(&rk3128_pll_clks[APLL],  in rk3128_armclk_set_clk()
132 					  priv->cru, APLL, hz))  in rk3128_armclk_set_clk()
136 	return rockchip_pll_get_rate(&rk3128_pll_clks[APLL], priv->cru, APLL);  in rk3128_armclk_set_clk()
543 		rate = rockchip_pll_get_rate(&rk3128_pll_clks[APLL],  in rk3128_clk_get_rate()
544 					     priv->cru, APLL);  in rk3128_clk_get_rate()
810 	if (rockchip_pll_get_rate(&rk3128_pll_clks[APLL],  in rkclk_init()
811 				  priv->cru, APLL) != APLL_HZ)  in rkclk_init()
848 		rockchip_pll_get_rate(&rk3128_pll_clks[APLL],  in rk3128_clk_probe()
849 				      priv->cru, APLL);  in rk3128_clk_probe()
853 		rockchip_pll_get_rate(&rk3128_pll_clks[APLL],  in rk3128_clk_probe()
854 				      priv->cru, APLL);  in rk3128_clk_probe()