1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Xilinx Zynq MPSoC Firmware layer 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014-2018 Xilinx, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_ZYNQMP_H 10*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_ZYNQMP_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define IOPLL 0 13*4882a593Smuzhiyun #define RPLL 1 14*4882a593Smuzhiyun #define APLL 2 15*4882a593Smuzhiyun #define DPLL 3 16*4882a593Smuzhiyun #define VPLL 4 17*4882a593Smuzhiyun #define IOPLL_TO_FPD 5 18*4882a593Smuzhiyun #define RPLL_TO_FPD 6 19*4882a593Smuzhiyun #define APLL_TO_LPD 7 20*4882a593Smuzhiyun #define DPLL_TO_LPD 8 21*4882a593Smuzhiyun #define VPLL_TO_LPD 9 22*4882a593Smuzhiyun #define ACPU 10 23*4882a593Smuzhiyun #define ACPU_HALF 11 24*4882a593Smuzhiyun #define DBF_FPD 12 25*4882a593Smuzhiyun #define DBF_LPD 13 26*4882a593Smuzhiyun #define DBG_TRACE 14 27*4882a593Smuzhiyun #define DBG_TSTMP 15 28*4882a593Smuzhiyun #define DP_VIDEO_REF 16 29*4882a593Smuzhiyun #define DP_AUDIO_REF 17 30*4882a593Smuzhiyun #define DP_STC_REF 18 31*4882a593Smuzhiyun #define GDMA_REF 19 32*4882a593Smuzhiyun #define DPDMA_REF 20 33*4882a593Smuzhiyun #define DDR_REF 21 34*4882a593Smuzhiyun #define SATA_REF 22 35*4882a593Smuzhiyun #define PCIE_REF 23 36*4882a593Smuzhiyun #define GPU_REF 24 37*4882a593Smuzhiyun #define GPU_PP0_REF 25 38*4882a593Smuzhiyun #define GPU_PP1_REF 26 39*4882a593Smuzhiyun #define TOPSW_MAIN 27 40*4882a593Smuzhiyun #define TOPSW_LSBUS 28 41*4882a593Smuzhiyun #define GTGREF0_REF 29 42*4882a593Smuzhiyun #define LPD_SWITCH 30 43*4882a593Smuzhiyun #define LPD_LSBUS 31 44*4882a593Smuzhiyun #define USB0_BUS_REF 32 45*4882a593Smuzhiyun #define USB1_BUS_REF 33 46*4882a593Smuzhiyun #define USB3_DUAL_REF 34 47*4882a593Smuzhiyun #define USB0 35 48*4882a593Smuzhiyun #define USB1 36 49*4882a593Smuzhiyun #define CPU_R5 37 50*4882a593Smuzhiyun #define CPU_R5_CORE 38 51*4882a593Smuzhiyun #define CSU_SPB 39 52*4882a593Smuzhiyun #define CSU_PLL 40 53*4882a593Smuzhiyun #define PCAP 41 54*4882a593Smuzhiyun #define IOU_SWITCH 42 55*4882a593Smuzhiyun #define GEM_TSU_REF 43 56*4882a593Smuzhiyun #define GEM_TSU 44 57*4882a593Smuzhiyun #define GEM0_TX 45 58*4882a593Smuzhiyun #define GEM1_TX 46 59*4882a593Smuzhiyun #define GEM2_TX 47 60*4882a593Smuzhiyun #define GEM3_TX 48 61*4882a593Smuzhiyun #define GEM0_RX 49 62*4882a593Smuzhiyun #define GEM1_RX 50 63*4882a593Smuzhiyun #define GEM2_RX 51 64*4882a593Smuzhiyun #define GEM3_RX 52 65*4882a593Smuzhiyun #define QSPI_REF 53 66*4882a593Smuzhiyun #define SDIO0_REF 54 67*4882a593Smuzhiyun #define SDIO1_REF 55 68*4882a593Smuzhiyun #define UART0_REF 56 69*4882a593Smuzhiyun #define UART1_REF 57 70*4882a593Smuzhiyun #define SPI0_REF 58 71*4882a593Smuzhiyun #define SPI1_REF 59 72*4882a593Smuzhiyun #define NAND_REF 60 73*4882a593Smuzhiyun #define I2C0_REF 61 74*4882a593Smuzhiyun #define I2C1_REF 62 75*4882a593Smuzhiyun #define CAN0_REF 63 76*4882a593Smuzhiyun #define CAN1_REF 64 77*4882a593Smuzhiyun #define CAN0 65 78*4882a593Smuzhiyun #define CAN1 66 79*4882a593Smuzhiyun #define DLL_REF 67 80*4882a593Smuzhiyun #define ADMA_REF 68 81*4882a593Smuzhiyun #define TIMESTAMP_REF 69 82*4882a593Smuzhiyun #define AMS_REF 70 83*4882a593Smuzhiyun #define PL0_REF 71 84*4882a593Smuzhiyun #define PL1_REF 72 85*4882a593Smuzhiyun #define PL2_REF 73 86*4882a593Smuzhiyun #define PL3_REF 74 87*4882a593Smuzhiyun #define WDT 75 88*4882a593Smuzhiyun #define IOPLL_INT 76 89*4882a593Smuzhiyun #define IOPLL_PRE_SRC 77 90*4882a593Smuzhiyun #define IOPLL_HALF 78 91*4882a593Smuzhiyun #define IOPLL_INT_MUX 79 92*4882a593Smuzhiyun #define IOPLL_POST_SRC 80 93*4882a593Smuzhiyun #define RPLL_INT 81 94*4882a593Smuzhiyun #define RPLL_PRE_SRC 82 95*4882a593Smuzhiyun #define RPLL_HALF 83 96*4882a593Smuzhiyun #define RPLL_INT_MUX 84 97*4882a593Smuzhiyun #define RPLL_POST_SRC 85 98*4882a593Smuzhiyun #define APLL_INT 86 99*4882a593Smuzhiyun #define APLL_PRE_SRC 87 100*4882a593Smuzhiyun #define APLL_HALF 88 101*4882a593Smuzhiyun #define APLL_INT_MUX 89 102*4882a593Smuzhiyun #define APLL_POST_SRC 90 103*4882a593Smuzhiyun #define DPLL_INT 91 104*4882a593Smuzhiyun #define DPLL_PRE_SRC 92 105*4882a593Smuzhiyun #define DPLL_HALF 93 106*4882a593Smuzhiyun #define DPLL_INT_MUX 94 107*4882a593Smuzhiyun #define DPLL_POST_SRC 95 108*4882a593Smuzhiyun #define VPLL_INT 96 109*4882a593Smuzhiyun #define VPLL_PRE_SRC 97 110*4882a593Smuzhiyun #define VPLL_HALF 98 111*4882a593Smuzhiyun #define VPLL_INT_MUX 99 112*4882a593Smuzhiyun #define VPLL_POST_SRC 100 113*4882a593Smuzhiyun #define CAN0_MIO 101 114*4882a593Smuzhiyun #define CAN1_MIO 102 115*4882a593Smuzhiyun #define ACPU_FULL 103 116*4882a593Smuzhiyun #define GEM0_REF 104 117*4882a593Smuzhiyun #define GEM1_REF 105 118*4882a593Smuzhiyun #define GEM2_REF 106 119*4882a593Smuzhiyun #define GEM3_REF 107 120*4882a593Smuzhiyun #define GEM0_REF_UNG 108 121*4882a593Smuzhiyun #define GEM1_REF_UNG 109 122*4882a593Smuzhiyun #define GEM2_REF_UNG 110 123*4882a593Smuzhiyun #define GEM3_REF_UNG 111 124*4882a593Smuzhiyun #define LPD_WDT 112 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #endif 127