1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_CRU_RK322X_H 7 #define _ASM_ARCH_CRU_RK322X_H 8 9 #include <common.h> 10 11 #define MHz 1000 * 1000 12 #define OSC_HZ (24 * MHz) 13 #define APLL_HZ (600 * MHz) 14 #define GPLL_HZ (1200 * MHz) 15 #define CPLL_HZ (500 * MHz) 16 #define ACLK_BUS_HZ (150 * MHz) 17 #define ACLK_PERI_HZ (150 * MHz) 18 19 /* Private data for the clock driver - used by rockchip_get_cru() */ 20 struct rk322x_clk_priv { 21 struct rk322x_cru *cru; 22 ulong gpll_hz; 23 ulong cpll_hz; 24 ulong armclk_hz; 25 ulong armclk_enter_hz; 26 ulong armclk_init_hz; 27 bool sync_kernel; 28 bool set_armclk_rate; 29 }; 30 31 struct rk322x_cru { 32 struct rk322x_pll { 33 unsigned int con0; 34 unsigned int con1; 35 unsigned int con2; 36 } pll[4]; 37 unsigned int reserved0[4]; 38 unsigned int cru_mode_con; 39 unsigned int cru_clksel_con[35]; 40 unsigned int cru_clkgate_con[16]; 41 unsigned int cru_softrst_con[9]; 42 unsigned int cru_misc_con; 43 unsigned int reserved1[2]; 44 unsigned int cru_glb_cnt_th; 45 unsigned int reserved2[3]; 46 unsigned int cru_glb_rst_st; 47 unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1]; 48 unsigned int cru_sdmmc_con[2]; 49 unsigned int cru_sdio_con[2]; 50 unsigned int reserved4[2]; 51 unsigned int cru_emmc_con[2]; 52 unsigned int reserved5[4]; 53 unsigned int cru_glb_srst_fst_value; 54 unsigned int cru_glb_srst_snd_value; 55 unsigned int cru_pll_mask_con; 56 }; 57 check_member(rk322x_cru, cru_pll_mask_con, 0x01f8); 58 59 enum rk322x_pll_id { 60 APLL, 61 DPLL, 62 CPLL, 63 GPLL, 64 NPLL, 65 PLL_COUNT, 66 }; 67 68 struct rk322x_clk_info { 69 unsigned long id; 70 char *name; 71 bool is_cru; 72 }; 73 74 #define RK2928_PLL_CON(x) ((x) * 0x4) 75 #define RK2928_MODE_CON 0x40 76 77 enum { 78 /* CRU_CLK_SEL0_CON */ 79 BUS_ACLK_PLL_SEL_SHIFT = 13, 80 BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, 81 BUS_ACLK_PLL_SEL_CPLL = 0, 82 BUS_ACLK_PLL_SEL_GPLL, 83 BUS_ACLK_PLL_SEL_HDMIPLL, 84 BUS_ACLK_DIV_SHIFT = 8, 85 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 86 CORE_CLK_PLL_SEL_SHIFT = 6, 87 CORE_CLK_PLL_SEL_MASK = 3 << CORE_CLK_PLL_SEL_SHIFT, 88 CORE_CLK_PLL_SEL_APLL = 0, 89 CORE_CLK_PLL_SEL_GPLL, 90 CORE_CLK_PLL_SEL_DPLL, 91 CORE_DIV_CON_SHIFT = 0, 92 CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 93 94 /* CRU_CLK_SEL1_CON */ 95 BUS_PCLK_DIV_SHIFT = 12, 96 BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, 97 BUS_HCLK_DIV_SHIFT = 8, 98 BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, 99 CORE_ACLK_DIV_SHIFT = 4, 100 CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, 101 CORE_PERI_DIV_SHIFT = 0, 102 CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, 103 104 /* CRU_CLKSEL5_CON */ 105 GMAC_OUT_PLL_SHIFT = 15, 106 GMAC_OUT_PLL_MASK = 1 << GMAC_OUT_PLL_SHIFT, 107 GMAC_OUT_DIV_SHIFT = 8, 108 GMAC_OUT_DIV_MASK = 0x1f << GMAC_OUT_DIV_SHIFT, 109 MAC_PLL_SEL_SHIFT = 7, 110 MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, 111 RMII_EXTCLK_SLE_SHIFT = 5, 112 RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SLE_SHIFT, 113 RMII_EXTCLK_SEL_INT = 0, 114 RMII_EXTCLK_SEL_EXT, 115 CLK_MAC_DIV_SHIFT = 0, 116 CLK_MAC_DIV_MASK = 0x1f << CLK_MAC_DIV_SHIFT, 117 118 /* CRU_CLKSEL10_CON */ 119 PERI_PCLK_DIV_SHIFT = 12, 120 PERI_PCLK_DIV_MASK = 7 << PERI_PCLK_DIV_SHIFT, 121 PERI_PLL_SEL_SHIFT = 10, 122 PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, 123 PERI_PLL_CPLL = 0, 124 PERI_PLL_GPLL, 125 PERI_PLL_HDMIPLL, 126 PERI_HCLK_DIV_SHIFT = 8, 127 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, 128 PERI_ACLK_DIV_SHIFT = 0, 129 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 130 131 /* CRU_CLKSEL11_CON */ 132 EMMC_PLL_SHIFT = 12, 133 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 134 EMMC_SEL_CPLL = 0, 135 EMMC_SEL_GPLL, 136 EMMC_SEL_24M, 137 SDIO_PLL_SHIFT = 10, 138 SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, 139 SDIO_SEL_CPLL = 0, 140 SDIO_SEL_GPLL, 141 SDIO_SEL_24M, 142 MMC0_PLL_SHIFT = 8, 143 MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, 144 MMC0_SEL_CPLL = 0, 145 MMC0_SEL_GPLL, 146 MMC0_SEL_24M, 147 MMC0_DIV_SHIFT = 0, 148 MMC0_DIV_MASK = 0xff << MMC0_DIV_SHIFT, 149 150 /* CRU_CLKSEL12_CON */ 151 EMMC_DIV_SHIFT = 8, 152 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 153 SDIO_DIV_SHIFT = 0, 154 SDIO_DIV_MASK = 0xff << SDIO_DIV_SHIFT, 155 156 /* CLKSEL_CON24 */ 157 CRYPTO_PLL_SEL_SHIFT = 5, 158 CRYPTO_PLL_SEL_MASK = 0x1 << CRYPTO_PLL_SEL_SHIFT, 159 CRYPTO_PLL_SEL_CPLL = 0, 160 CRYPTO_PLL_SEL_GPLL, 161 CRYPTO_DIV_SHIFT = 0, 162 CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT, 163 164 /* CLKSEL_CON25 */ 165 SPI_PLL_SEL_SHIFT = 8, 166 SPI_PLL_SEL_MASK = 0x1 << SPI_PLL_SEL_SHIFT, 167 SPI_PLL_SEL_CPLL = 0, 168 SPI_PLL_SEL_GPLL, 169 SPI_DIV_SHIFT = 0, 170 SPI_DIV_MASK = 0x7f << SPI_DIV_SHIFT, 171 172 /* CRU_CLKSEL26_CON */ 173 DDR_CLK_PLL_SEL_SHIFT = 8, 174 DDR_CLK_PLL_SEL_MASK = 3 << DDR_CLK_PLL_SEL_SHIFT, 175 DDR_CLK_SEL_DPLL = 0, 176 DDR_CLK_SEL_GPLL, 177 DDR_CLK_SEL_APLL, 178 DDR_DIV_SEL_SHIFT = 0, 179 DDR_DIV_SEL_MASK = 3 << DDR_DIV_SEL_SHIFT, 180 181 /* CRU_CLKSEL27_CON */ 182 DCLK_LCDC_PLL_SEL_GPLL = 0, 183 DCLK_LCDC_PLL_SEL_CPLL = 1, 184 DCLK_LCDC_PLL_SEL_SHIFT = 0, 185 DCLK_LCDC_PLL_SEL_MASK = 1 << DCLK_LCDC_PLL_SEL_SHIFT, 186 DCLK_LCDC_SEL_HDMIPHY = 0, 187 DCLK_LCDC_SEL_PLL = 1, 188 DCLK_LCDC_SEL_SHIFT = 1, 189 DCLK_LCDC_SEL_MASK = 1 << DCLK_LCDC_SEL_SHIFT, 190 DCLK_LCDC_DIV_CON_SHIFT = 8, 191 DCLK_LCDC_DIV_CON_MASK = 0xFf << DCLK_LCDC_DIV_CON_SHIFT, 192 193 /* CRU_CLKSEL29_CON */ 194 GMAC_CLK_SRC_SHIFT = 12, 195 GMAC_CLK_SRC_MASK = 1 << GMAC_CLK_SRC_SHIFT, 196 197 /* CRU_CLKSEL33_CON */ 198 ACLK_VOP_PLL_SEL_SHIFT = 5, 199 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT, 200 ACLK_VOP_PLL_SEL_CPLL = 0, 201 ACLK_VOP_PLL_SEL_GPLL = 1, 202 ACLK_VOP_PLL_SEL_HDMIPHY = 2, 203 ACLK_VOP_DIV_CON_SHIFT = 0, 204 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 205 206 /* CRU_SOFTRST5_CON */ 207 DDRCTRL_PSRST_SHIFT = 11, 208 DDRCTRL_SRST_SHIFT = 10, 209 DDRPHY_PSRST_SHIFT = 9, 210 DDRPHY_SRST_SHIFT = 8, 211 }; 212 #endif 213