1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2017 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ASM_ARCH_CRU_RK3128_H 8*4882a593Smuzhiyun #define _ASM_ARCH_CRU_RK3128_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define MHz 1000000 13*4882a593Smuzhiyun #define OSC_HZ (24 * MHz) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define APLL_HZ (600 * MHz) 16*4882a593Smuzhiyun #define GPLL_HZ (594 * MHz) 17*4882a593Smuzhiyun #define CPLL_HZ (400 * MHz) 18*4882a593Smuzhiyun #define ACLK_BUS_HZ (148500000) 19*4882a593Smuzhiyun #define ACLK_PERI_HZ (148500000) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* Private data for the clock driver - used by rockchip_get_cru() */ 22*4882a593Smuzhiyun struct rk3128_clk_priv { 23*4882a593Smuzhiyun struct rk3128_cru *cru; 24*4882a593Smuzhiyun ulong gpll_hz; 25*4882a593Smuzhiyun ulong armclk_hz; 26*4882a593Smuzhiyun ulong armclk_enter_hz; 27*4882a593Smuzhiyun ulong armclk_init_hz; 28*4882a593Smuzhiyun bool sync_kernel; 29*4882a593Smuzhiyun bool set_armclk_rate; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun struct rk3128_cru { 33*4882a593Smuzhiyun struct rk3128_pll { 34*4882a593Smuzhiyun unsigned int con0; 35*4882a593Smuzhiyun unsigned int con1; 36*4882a593Smuzhiyun unsigned int con2; 37*4882a593Smuzhiyun unsigned int con3; 38*4882a593Smuzhiyun } pll[4]; 39*4882a593Smuzhiyun unsigned int cru_mode_con; 40*4882a593Smuzhiyun unsigned int cru_clksel_con[35]; 41*4882a593Smuzhiyun unsigned int cru_clkgate_con[11]; 42*4882a593Smuzhiyun unsigned int reserved; 43*4882a593Smuzhiyun unsigned int cru_glb_srst_fst_value; 44*4882a593Smuzhiyun unsigned int cru_glb_srst_snd_value; 45*4882a593Smuzhiyun unsigned int reserved1[2]; 46*4882a593Smuzhiyun unsigned int cru_softrst_con[9]; 47*4882a593Smuzhiyun unsigned int cru_misc_con; 48*4882a593Smuzhiyun unsigned int reserved2[2]; 49*4882a593Smuzhiyun unsigned int cru_glb_cnt_th; 50*4882a593Smuzhiyun unsigned int reserved3[3]; 51*4882a593Smuzhiyun unsigned int cru_glb_rst_st; 52*4882a593Smuzhiyun unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1]; 53*4882a593Smuzhiyun unsigned int cru_sdmmc_con[2]; 54*4882a593Smuzhiyun unsigned int cru_sdio_con[2]; 55*4882a593Smuzhiyun unsigned int reserved5[2]; 56*4882a593Smuzhiyun unsigned int cru_emmc_con[2]; 57*4882a593Smuzhiyun unsigned int reserved6[4]; 58*4882a593Smuzhiyun unsigned int cru_pll_prg_en; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun check_member(rk3128_cru, cru_pll_prg_en, 0x01f0); 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun enum rk3128_pll_id { 63*4882a593Smuzhiyun APLL, 64*4882a593Smuzhiyun DPLL, 65*4882a593Smuzhiyun CPLL, 66*4882a593Smuzhiyun GPLL, 67*4882a593Smuzhiyun PLL_COUNT, 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct rk3128_clk_info { 71*4882a593Smuzhiyun unsigned long id; 72*4882a593Smuzhiyun char *name; 73*4882a593Smuzhiyun bool is_cru; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define RK2928_PLL_CON(x) ((x) * 0x4) 77*4882a593Smuzhiyun #define RK2928_MODE_CON 0x40 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun enum { 80*4882a593Smuzhiyun /* CRU_CLK_SEL0_CON */ 81*4882a593Smuzhiyun BUS_PLL_SEL_SHIFT = 13, 82*4882a593Smuzhiyun BUS_PLL_SEL_MASK = 3 << BUS_PLL_SEL_SHIFT, 83*4882a593Smuzhiyun BUS_PLL_SEL_CPLL = 0, 84*4882a593Smuzhiyun BUS_PLL_SEL_GPLL, 85*4882a593Smuzhiyun BUS_PLL_SEL_GPLL_DIV2, 86*4882a593Smuzhiyun BUS_PLL_SEL_GPLL_DIV3, 87*4882a593Smuzhiyun ACLK_BUS_DIV_SHIFT = 8, 88*4882a593Smuzhiyun ACLK_BUS_DIV_MASK = 0x1f << ACLK_BUS_DIV_SHIFT, 89*4882a593Smuzhiyun CORE_CLK_PLL_SEL_SHIFT = 7, 90*4882a593Smuzhiyun CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 91*4882a593Smuzhiyun CORE_CLK_PLL_SEL_APLL = 0, 92*4882a593Smuzhiyun CORE_CLK_PLL_SEL_GPLL_DIV2, 93*4882a593Smuzhiyun CORE_DIV_CON_SHIFT = 0, 94*4882a593Smuzhiyun CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* CRU_CLK_SEL1_CON */ 97*4882a593Smuzhiyun PCLK_BUS_DIV_SHIFT = 12, 98*4882a593Smuzhiyun PCLK_BUS_DIV_MASK = 7 << PCLK_BUS_DIV_SHIFT, 99*4882a593Smuzhiyun HCLK_BUS_DIV_SHIFT = 8, 100*4882a593Smuzhiyun HCLK_BUS_DIV_MASK = 3 << HCLK_BUS_DIV_SHIFT, 101*4882a593Smuzhiyun CORE_ACLK_DIV_SHIFT = 4, 102*4882a593Smuzhiyun CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT, 103*4882a593Smuzhiyun CORE_DBG_DIV_SHIFT = 0, 104*4882a593Smuzhiyun CORE_DBG_DIV_MASK = 0x0f << CORE_DBG_DIV_SHIFT, 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* CRU_CLK_SEL2_CON */ 107*4882a593Smuzhiyun NANDC_PLL_SEL_SHIFT = 14, 108*4882a593Smuzhiyun NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT, 109*4882a593Smuzhiyun NANDC_PLL_SEL_CPLL = 0, 110*4882a593Smuzhiyun NANDC_PLL_SEL_GPLL, 111*4882a593Smuzhiyun NANDC_CLK_DIV_SHIFT = 8, 112*4882a593Smuzhiyun NANDC_CLK_DIV_MASK = 0x1f << NANDC_CLK_DIV_SHIFT, 113*4882a593Smuzhiyun PVTM_CLK_DIV_SHIFT = 0, 114*4882a593Smuzhiyun PVTM_CLK_DIV_MASK = 0x3f << PVTM_CLK_DIV_SHIFT, 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* CRU_CLKSEL10_CON */ 117*4882a593Smuzhiyun PERI_PLL_SEL_SHIFT = 14, 118*4882a593Smuzhiyun PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, 119*4882a593Smuzhiyun PERI_PLL_SEL_GPLL = 0, 120*4882a593Smuzhiyun PERI_PLL_SEL_CPLL, 121*4882a593Smuzhiyun PERI_PLL_SEL_GPLL_DIV2, 122*4882a593Smuzhiyun PERI_PLL_SEL_GPLL_DIV3, 123*4882a593Smuzhiyun PCLK_PERI_DIV_SHIFT = 12, 124*4882a593Smuzhiyun PCLK_PERI_DIV_MASK = 3 << PCLK_PERI_DIV_SHIFT, 125*4882a593Smuzhiyun HCLK_PERI_DIV_SHIFT = 8, 126*4882a593Smuzhiyun HCLK_PERI_DIV_MASK = 3 << HCLK_PERI_DIV_SHIFT, 127*4882a593Smuzhiyun ACLK_PERI_DIV_SHIFT = 0, 128*4882a593Smuzhiyun ACLK_PERI_DIV_MASK = 0x1f << ACLK_PERI_DIV_SHIFT, 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* CRU_CLKSEL11_CON */ 131*4882a593Smuzhiyun SFC_PLL_SEL_SHIFT = 14, 132*4882a593Smuzhiyun SFC_PLL_SEL_MASK = 3 << SFC_PLL_SEL_SHIFT, 133*4882a593Smuzhiyun SFC_PLL_SEL_CPLL = 0, 134*4882a593Smuzhiyun SFC_PLL_SEL_GPLL, 135*4882a593Smuzhiyun SFC_CLK_DIV_SHIFT = 8, 136*4882a593Smuzhiyun SFC_CLK_DIV_MASK = 0x1f << SFC_CLK_DIV_SHIFT, 137*4882a593Smuzhiyun MMC0_PLL_SHIFT = 6, 138*4882a593Smuzhiyun MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, 139*4882a593Smuzhiyun MMC0_SEL_APLL = 0, 140*4882a593Smuzhiyun MMC0_SEL_GPLL, 141*4882a593Smuzhiyun MMC0_SEL_GPLL_DIV2, 142*4882a593Smuzhiyun MMC0_SEL_24M, 143*4882a593Smuzhiyun MMC0_DIV_SHIFT = 0, 144*4882a593Smuzhiyun MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* CRU_CLKSEL12_CON */ 147*4882a593Smuzhiyun EMMC_PLL_SHIFT = 14, 148*4882a593Smuzhiyun EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 149*4882a593Smuzhiyun EMMC_SEL_APLL = 0, 150*4882a593Smuzhiyun EMMC_SEL_GPLL, 151*4882a593Smuzhiyun EMMC_SEL_GPLL_DIV2, 152*4882a593Smuzhiyun EMMC_SEL_24M, 153*4882a593Smuzhiyun EMMC_DIV_SHIFT = 8, 154*4882a593Smuzhiyun EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT, 155*4882a593Smuzhiyun SDIO_PLL_SHIFT = 6, 156*4882a593Smuzhiyun SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, 157*4882a593Smuzhiyun SDIO_SEL_APLL = 0, 158*4882a593Smuzhiyun SDIO_SEL_GPLL, 159*4882a593Smuzhiyun SDIO_SEL_GPLL_DIV2, 160*4882a593Smuzhiyun SDIO_SEL_24M, 161*4882a593Smuzhiyun SDIO_DIV_SHIFT = 0, 162*4882a593Smuzhiyun SDIO_DIV_MASK = 0x3f << SDIO_DIV_SHIFT, 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun /* CLKSEL_CON24 */ 165*4882a593Smuzhiyun SARADC_DIV_CON_SHIFT = 8, 166*4882a593Smuzhiyun SARADC_DIV_CON_MASK = GENMASK(15, 8), 167*4882a593Smuzhiyun SARADC_DIV_CON_WIDTH = 8, 168*4882a593Smuzhiyun CLK_CRYPTO_DIV_CON_SHIFT= 0, 169*4882a593Smuzhiyun CLK_CRYPTO_DIV_CON_MASK = GENMASK(1, 0), 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* CLKSEL_CON25 */ 172*4882a593Smuzhiyun SPI_PLL_SEL_SHIFT = 8, 173*4882a593Smuzhiyun SPI_PLL_SEL_MASK = 0x3 << SPI_PLL_SEL_SHIFT, 174*4882a593Smuzhiyun SPI_PLL_SEL_CPLL = 0, 175*4882a593Smuzhiyun SPI_PLL_SEL_GPLL, 176*4882a593Smuzhiyun SPI_PLL_SEL_GPLL_DIV2, 177*4882a593Smuzhiyun SPI_DIV_SHIFT = 0, 178*4882a593Smuzhiyun SPI_DIV_MASK = 0x7f << SPI_DIV_SHIFT, 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun /* CRU_CLKSEL27_CON*/ 181*4882a593Smuzhiyun DCLK_VOP_SEL_SHIFT = 0, 182*4882a593Smuzhiyun DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, 183*4882a593Smuzhiyun DCLK_VOP_PLL_SEL_CPLL = 0, 184*4882a593Smuzhiyun DCLK_VOP_DIV_CON_SHIFT = 8, 185*4882a593Smuzhiyun DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT, 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun /* CRU_CLKSEL31_CON */ 188*4882a593Smuzhiyun VIO0_PLL_SHIFT = 5, 189*4882a593Smuzhiyun VIO0_PLL_MASK = 7 << VIO0_PLL_SHIFT, 190*4882a593Smuzhiyun VI00_SEL_CPLL = 0, 191*4882a593Smuzhiyun VIO0_SEL_GPLL, 192*4882a593Smuzhiyun VIO0_DIV_SHIFT = 0, 193*4882a593Smuzhiyun VIO0_DIV_MASK = 0x1f << VIO0_DIV_SHIFT, 194*4882a593Smuzhiyun VIO1_PLL_SHIFT = 13, 195*4882a593Smuzhiyun VIO1_PLL_MASK = 7 << VIO1_PLL_SHIFT, 196*4882a593Smuzhiyun VI01_SEL_CPLL = 0, 197*4882a593Smuzhiyun VIO1_SEL_GPLL, 198*4882a593Smuzhiyun VIO1_DIV_SHIFT = 8, 199*4882a593Smuzhiyun VIO1_DIV_MASK = 0x1f << VIO1_DIV_SHIFT, 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun /* CRU_SOFTRST5_CON */ 202*4882a593Smuzhiyun DDRCTRL_PSRST_SHIFT = 11, 203*4882a593Smuzhiyun DDRCTRL_SRST_SHIFT = 10, 204*4882a593Smuzhiyun DDRPHY_PSRST_SHIFT = 9, 205*4882a593Smuzhiyun DDRPHY_SRST_SHIFT = 8, 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun #endif 208