Home
last modified time | relevance | path

Searched +full:rk3399 +full:- +full:grf (Results 1 – 25 of 123) sorted by relevance

12345

/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/soc/rockchip/
H A Dgrf.txt1 * Rockchip General Register Files (GRF)
6 From RK3368 SoCs, the GRF is divided into two sections,
7 - GRF, used for general non-secure system,
8 - SGRF, used for general secure system,
9 - PMUGRF, used for always on system
11 On RK3328 SoCs, the GRF adds a section for USB2PHYGRF,
13 ON RK3308 SoC, the GRF is divided into four sections:
14 - GRF, used for general non-secure system,
15 - SGRF, used for general secure system,
16 - DETECTGRF, used for audio codec system,
[all …]
H A Drockchip-pvtm.txt2 ----------------------------------
4 The Process-Voltage-Temperature Monitor (PVTM) is used to monitor the chip
9 - compatible: Should be one of the following.
10 - "rockchip,px30-pvtm" - for PX30 SoCs.
11 - "rockchip,px30-pmu-pvtm" - for PX30 SoCs.
12 - "rockchip,rk1808-pvtm" - for RK1808 SoCs.
13 - "rockchip,rk1808-pmu-pvtm" - for RK1808 SoCs.
14 - "rockchip,rk1808-npu-pvtm" - for RK1808 SoCs.
15 - "rockchip,rk3288-pvtm" - for RK3288 SoCs.
16 - "rockchip,rk3308-pvtm" - for RK3308 SoCs.
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Drockchip-mipi-dphy-rx0.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
[all …]
H A Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
H A Dphy-rockchip-inno-usb2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-usb2phy
16 - rockchip,rk1808-usb2phy
17 - rockchip,rk3128-usb2phy
18 - rockchip,rk3228-usb2phy
19 - rockchip,rk3308-usb2phy
[all …]
H A Drockchip-pcie-phy.txt2 -----------------------
5 - compatible: rockchip,rk3399-pcie-phy
6 - clocks: Must contain an entry in clock-names.
7 See ../clocks/clock-bindings.txt for details.
8 - clock-names: Must be "refclk"
9 - resets: Must contain an entry in reset-names.
11 - reset-names: Must be "phy"
14 - #phy-cells: must be 0
16 Required properties for per-lane PHY mode (preferred):
17 - #phy-cells: must be 1
[all …]
H A Drockchip-emmc-phy.txt2 -----------------------
5 - compatible: rockchip,rk3399-emmc-phy
6 - #phy-cells: must be 0
7 - reg: PHY register address offset and length in "general
11 - clock-names: Should contain "emmcclk". Although this is listed as optional
14 See ../clock/clock-bindings.txt for details.
15 - clocks: Should have a phandle to the card clock exported by the SDHCI driver.
16 - drive-impedance-ohm: Specifies the drive impedance in Ohm.
23 grf: syscon@ff770000 {
24 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/soc/rockchip-system-status.h>
14 #include <dt-bindings/suspend/rockchip-rk3399.h>
[all …]
H A Drk3399-linux.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/display/drm_mipi_dsi.h>
8 #include "rk3399-vop-clk-set.dtsi"
11 compatible = "rockchip,linux", "rockchip,rk3399";
20 …bootargs = "earlycon=uart8250,mmio32,0xff1a0000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 roo…
23 reserved-memory {
24 #address-cells = <2>;
25 #size-cells = <2>;
28 drm_logo: drm-logo@00000000 {
29 compatible = "rockchip,drm-logo";
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Drockchip,rk3399-cru.txt1 * Rockchip RK3399 Clock and Reset Unit
3 The RK3399 clock controller generates and supplies clock to various
9 - compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
10 - compatible: CRU should be "rockchip,rk3399-cru"
11 - reg: physical base address of the controller and length of memory mapped
13 - #clock-cells: should be 1.
14 - #reset-cells: should be 1.
18 - rockchip,grf: phandle to the syscon managing the "general register files".
19 It is used for GRF muxes, if missing any muxes present in the GRF will not
24 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3399.dtsi2 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/clock/rk3399-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/power/rk3399-power.h>
13 #include <dt-bindings/thermal/thermal.h>
17 compatible = "rockchip,rk3399";
[all …]
H A D.rk3399-evb.dtb.dts.tmp
H A D.rk3399-firefly.dtb.dts.tmp
H A D.rk3399-puma-ddr1600.dtb.dts.tmp
H A D.rk3399-puma-ddr1866.dtb.dts.tmp
H A D.rk3399-puma-ddr1333.dtb.dts.tmp
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/i2c/
H A Di2c-rk3x.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-rk3x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - $ref: /schemas/i2c/i2c-controller.yaml#
17 - Heiko Stuebner <heiko@sntech.de>
23 - const: rockchip,rv1108-i2c
24 - const: rockchip,rk3066-i2c
25 - const: rockchip,rk3188-i2c
26 - const: rockchip,rk3228-i2c
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/rockchip/
H A Dcdn-dp-rockchip.txt1 Rockchip RK3399 specific extensions to the cdn Display Port
5 - compatible: must be "rockchip,rk3399-cdn-dp"
7 - reg: physical base address of the controller and length
9 - clocks: from common clock binding: handle to dp clock.
11 - clock-names: from common clock binding:
12 Required elements: "core-clk" "pclk" "spdif" "grf"
14 - resets : a list of phandle + reset specifier pairs
15 - reset-names : string of reset names
17 - power-domains : power-domain property defined with a phandle
19 - assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
[all …]
H A Ddw_mipi_dsi_rockchip.txt5 - #address-cells: Should be <1>.
6 - #size-cells: Should be <0>.
7 - compatible: one of
8 "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
9 "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
10 "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
11 - reg: Represent the physical address range of the controller.
12 - interrupts: Represent the controller's interrupt to the CPU(s).
13 - clocks, clock-names: Phandles to the controller's pll reference
15 For RK3399, a phy config clock (phy_cfg) and a grf clock(grf)
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/video/
H A Drockchip_dp.txt1 Rockchip RK3399 specific extensions to the cdn Display Port with rkfb
5 - compatible: must be "rockchip,rk3399-cdn-dp-fb"
7 - reg: physical base address of the controller and length
9 - clocks: from common clock binding: handle to dp clock.
11 - clock-names: from common clock binding:
12 Required elements: "core-clk" "pclk" "spdif"
14 - resets : a list of phandle + reset specifier pairs
15 - reset-names : string reset name, must be:
17 - power-domains : power-domain property defined with a phandle
19 - assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/power/
H A Drockchip-io-domain.txt2 -------------------------------------
9 - If the regulator hooked up to a pin like SDMMC0_VDD is 3.3V then
14 general register file (GRF) in sync with the actual value of a voltage
18 - any logic for deciding what voltage we should set regulators to
19 - any logic for deciding whether regulators (or internal SoC blocks)
33 - compatible: should be one of:
34 - "rockchip,px30-io-voltage-domain" for px30
35 - "rockchip,px30-pmu-io-voltage-domain" for px30 pmu-domains
36 - "rockchip,rk3188-io-voltage-domain" for rk3188
37 - "rockchip,rk3228-io-voltage-domain" for rk3228
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3399/
H A Drk3399.c4 * SPDX-License-Identifier: GPL-2.0+
83 struct rk3399_grf_regs * const grf = (void *)GRF_BASE; in arch_cpu_init() local
99 rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0); in arch_cpu_init()
100 rk_clrreg(&sgrf->slv_secure_con4, 0x2000); in arch_cpu_init()
104 rk_clrreg(&grf->emmccore_con[11], 0x0ff); in arch_cpu_init()
107 rk_clrreg(&pmugrf->soc_con0, 1 << 5); in arch_cpu_init()
113 writel(0x7f002000, &pmucru->pmucru_clksel[1]); in arch_cpu_init()
114 writel(0x01000100, &pmucru->pmucru_clkgate_con[0]); in arch_cpu_init()
127 struct rk3399_grf_regs * const grf = (void *)GRF_BASE; in board_debug_uart_init() local
130 /* Enable early UART0 on the RK3399 */ in board_debug_uart_init()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/
H A Drockchip-mipi-dphy.txt1 Rockchip SoC MIPI RX D-PHY
2 -------------------------------------------------------------
5 - compatible: value should be one of the following
6 "rockchip,rk1808-mipi-dphy-rx"
7 "rockchip,rk3288-mipi-dphy"
8 "rockchip,rk3326-mipi-dphy"
9 "rockchip,rk3368-mipi-dphy"
10 "rockchip,rk3399-mipi-dphy"
11 "rockchip,rv1126-csi-dphy"
12 - clocks : list of clock specifiers, corresponding to entries in
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/
H A Drockchip,pinctrl.txt8 Please refer to pinctrl-bindings.txt in this directory for details of the
16 settings such as pull-up, etc.
19 defined as gpio sub-nodes of the pinmux controller.
22 - compatible: should be
23 "rockchip,px30-pinctrl": for Rockchip PX30
24 "rockchip,rv1108-pinctrl": for Rockchip RV1108
25 "rockchip,rk2928-pinctrl": for Rockchip RK2928
26 "rockchip,rk3066a-pinctrl": for Rockchip RK3066a
27 "rockchip,rk3066b-pinctrl": for Rockchip RK3066b
28 "rockchip,rk3128-pinctrl": for Rockchip RK3128
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Drockchip-dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: "http://devicetree.org/schemas/net/rockchip-dwmac.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - David Wu <david.wu@rock-chips.com>
18 - rockchip,px30-gmac
19 - rockchip,rk3128-gmac
20 - rockchip,rk3228-gmac
21 - rockchip,rk3288-gmac
22 - rockchip,rk3308-gmac
[all …]

12345