xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/soc/rockchip/rockchip-pvtm.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunRockchip pvtm device tree bindings
2*4882a593Smuzhiyun----------------------------------
3*4882a593Smuzhiyun
4*4882a593SmuzhiyunThe Process-Voltage-Temperature Monitor (PVTM) is used to monitor the chip
5*4882a593Smuzhiyunperformance variance caused by chip process, voltage and temperature.
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun
8*4882a593SmuzhiyunRequired properties:
9*4882a593Smuzhiyun- compatible: Should be one of the following.
10*4882a593Smuzhiyun - "rockchip,px30-pvtm" - for PX30 SoCs.
11*4882a593Smuzhiyun - "rockchip,px30-pmu-pvtm" - for PX30 SoCs.
12*4882a593Smuzhiyun - "rockchip,rk1808-pvtm" - for RK1808 SoCs.
13*4882a593Smuzhiyun - "rockchip,rk1808-pmu-pvtm" - for RK1808 SoCs.
14*4882a593Smuzhiyun - "rockchip,rk1808-npu-pvtm" - for RK1808 SoCs.
15*4882a593Smuzhiyun - "rockchip,rk3288-pvtm" - for RK3288 SoCs.
16*4882a593Smuzhiyun - "rockchip,rk3308-pvtm" - for RK3308 SoCs.
17*4882a593Smuzhiyun - "rockchip,rk3308-pmu-pvtm" - for RK3308 SoCs.
18*4882a593Smuzhiyun - "rockchip,rk3399-pvtm" - for RK3399 SoCs.
19*4882a593Smuzhiyun - "rockchip,rk3399-pmu-pvtm" - for RK3399 SoCs.
20*4882a593Smuzhiyun - "rockchip,rk3568-core-pvtm" - for RK3568 SoCs.
21*4882a593Smuzhiyun - "rockchip,rk3568-gpu-pvtm" - for RK3568 SoCs.
22*4882a593Smuzhiyun - "rockchip,rk3568-npu-pvtm" - for RK3568 SoCs.
23*4882a593Smuzhiyun - "rockchip,rk3588-bigcore0-pvtm" - for RK3588 SoCs.
24*4882a593Smuzhiyun - "rockchip,rk3588-bigcore1-pvtm" - for RK3588 SoCs.
25*4882a593Smuzhiyun - "rockchip,rk3588-litcore-pvtm" - for RK3588 SoCs.
26*4882a593Smuzhiyun - "rockchip,rk3588-gpu-pvtm" - for RK3588 SoCs.
27*4882a593Smuzhiyun - "rockchip,rk3588-npu-pvtm" - for RK3588 SoCs.
28*4882a593Smuzhiyun - "rockchip,rk3588-pmu-pvtm" - for RK3588 SoCs.
29*4882a593Smuzhiyun - "rockchip,rv1126-cpu-pvtm" - for RV1126 SoCs.
30*4882a593Smuzhiyun - "rockchip,rv1126-npu-pvtm" - for RV1126 SoCs.
31*4882a593Smuzhiyun - "rockchip,rv1126-pmu-pvtm" - for RV1126 SoCs.
32*4882a593Smuzhiyun- clocks: Must contain an entry for each entry in clock-names.
33*4882a593Smuzhiyun  See ../../clocks/clock-bindings.txt for details.
34*4882a593Smuzhiyun- clock-names: Should be "clk", "pclk".
35*4882a593Smuzhiyun
36*4882a593SmuzhiyunOptional properties:
37*4882a593Smuzhiyun- resets: Must contain an entry for each entry in reset-names.
38*4882a593Smuzhiyun  See ../../reset/reset.txt for details.
39*4882a593Smuzhiyun- reset-names: Should be "rst", "rst-p".
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun
42*4882a593SmuzhiyunExample:
43*4882a593Smuzhiyun
44*4882a593Smuzhiyungrf: syscon@ff770000 {
45*4882a593Smuzhiyun	compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
46*4882a593Smuzhiyun	reg = <0x0 0xff770000 0x0 0x10000>;
47*4882a593Smuzhiyun	#address-cells = <1>;
48*4882a593Smuzhiyun	#size-cells = <1>;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun...
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun	pvtm: pvtm {
53*4882a593Smuzhiyun		compatible = "rockchip,rk3399-pvtm";
54*4882a593Smuzhiyun		#address-cells = <1>;
55*4882a593Smuzhiyun		#size-cells = <0>;
56*4882a593Smuzhiyun		status = "disabled";
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun		pvtm@0 {
59*4882a593Smuzhiyun			reg = <0>;
60*4882a593Smuzhiyun			clocks = <&cru SCLK_PVTM_CORE_L>;
61*4882a593Smuzhiyun			clock-names = "clk";
62*4882a593Smuzhiyun			resets = <&cru SRST_PVTM_CORE_L>;
63*4882a593Smuzhiyun			reset-names = "rst";
64*4882a593Smuzhiyun		};
65*4882a593Smuzhiyun		pvtm@1 {
66*4882a593Smuzhiyun			reg = <1>;
67*4882a593Smuzhiyun			clocks = <&cru SCLK_PVTM_CORE_B>;
68*4882a593Smuzhiyun			clock-names = "clk";
69*4882a593Smuzhiyun			resets = <&cru SRST_PVTM_CORE_B>;
70*4882a593Smuzhiyun			reset-names = "rst";
71*4882a593Smuzhiyun		};
72*4882a593Smuzhiyun		pvtm@2 {
73*4882a593Smuzhiyun			reg = <2>;
74*4882a593Smuzhiyun			clocks = <&cru SCLK_PVTM_DDR>;
75*4882a593Smuzhiyun			clock-names = "clk";
76*4882a593Smuzhiyun			resets = <&cru SRST_PVTM_DDR>;
77*4882a593Smuzhiyun			reset-names = "rst";
78*4882a593Smuzhiyun		};
79*4882a593Smuzhiyun		pvtm@3 {
80*4882a593Smuzhiyun			reg = <3>;
81*4882a593Smuzhiyun			clocks = <&cru SCLK_PVTM_GPU>;
82*4882a593Smuzhiyun			clock-names = "clk";
83*4882a593Smuzhiyun			resets = <&cru SRST_PVTM_GPU>;
84*4882a593Smuzhiyun			reset-names = "rst";
85*4882a593Smuzhiyun		};
86*4882a593Smuzhiyun	};
87*4882a593Smuzhiyun}
88