1Rockchip RK3399 specific extensions to the cdn Display Port with rkfb 2================================ 3 4Required properties: 5- compatible: must be "rockchip,rk3399-cdn-dp-fb" 6 7- reg: physical base address of the controller and length 8 9- clocks: from common clock binding: handle to dp clock. 10 11- clock-names: from common clock binding: 12 Required elements: "core-clk" "pclk" "spdif" 13 14- resets : a list of phandle + reset specifier pairs 15- reset-names : string reset name, must be: 16 "spdif" 17- power-domains : power-domain property defined with a phandle 18 to respective power domain. 19- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE> 20- assigned-clock-rates : the DP core clk frequency, shall be: 100000000 21 22- rockchip,grf: this soc should set GRF regs, so need get grf here. 23 24- phys: from general PHY binding: the phandle for the PHY device. 25 26- extcon: extcon specifier for the Power Delivery 27 28- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF 29 30------------------------------------------------------------------------------- 31 32Example: 33 cdn_dp_fb: dp-fb@fec00000 { 34 compatible = "rockchip,rk3399-cdn-dp-fb"; 35 reg = <0x0 0xfec00000 0x0 0x100000>; 36 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 37 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 38 <&cru SCLK_SPDIF_REC_DPTX>; 39 clock-names = "core-clk", "pclk", "spdif"; 40 assigned-clocks = <&cru SCLK_DP_CORE>; 41 assigned-clock-rates = <100000000>; 42 power-domains = <&power RK3399_PD_HDCP>; 43 phys = <&tcphy0 0>, <&tcphy1 0>; 44 resets = <&cru SRST_DPTX_SPDIF_REC>; 45 reset-names = "spdif"; 46 rockchip,grf = <&grf>; 47 #address-cells = <1>; 48 #size-cells = <0>; 49 #sound-dai-cells = <1>; 50 }; 51