xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunRockchip RK3399 specific extensions to the cdn Display Port
2*4882a593Smuzhiyun================================
3*4882a593Smuzhiyun
4*4882a593SmuzhiyunRequired properties:
5*4882a593Smuzhiyun- compatible: must be "rockchip,rk3399-cdn-dp"
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun- reg: physical base address of the controller and length
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun- clocks: from common clock binding: handle to dp clock.
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun- clock-names: from common clock binding:
12*4882a593Smuzhiyun	       Required elements: "core-clk" "pclk" "spdif" "grf"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun- resets : a list of phandle + reset specifier pairs
15*4882a593Smuzhiyun- reset-names : string of reset names
16*4882a593Smuzhiyun		Required elements: "apb", "core", "dptx", "spdif"
17*4882a593Smuzhiyun- power-domains : power-domain property defined with a phandle
18*4882a593Smuzhiyun		  to respective power domain.
19*4882a593Smuzhiyun- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
20*4882a593Smuzhiyun- assigned-clock-rates : the DP core clk frequency, shall be: 100000000
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun- rockchip,grf: this soc should set GRF regs, so need get grf here.
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun- ports: contain a port nodes with endpoint definitions as defined in
25*4882a593Smuzhiyun	 Documentation/devicetree/bindings/media/video-interfaces.txt.
26*4882a593Smuzhiyun	 contained 2 endpoints, connecting to the output of vop.
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun- phys: from general PHY binding: the phandle for the PHY device.
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun- extcon: extcon specifier for the Power Delivery
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun-------------------------------------------------------------------------------
35*4882a593Smuzhiyun
36*4882a593SmuzhiyunExample:
37*4882a593Smuzhiyun	cdn_dp: dp@fec00000 {
38*4882a593Smuzhiyun		compatible = "rockchip,rk3399-cdn-dp";
39*4882a593Smuzhiyun		reg = <0x0 0xfec00000 0x0 0x100000>;
40*4882a593Smuzhiyun		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
41*4882a593Smuzhiyun		clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
42*4882a593Smuzhiyun			 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
43*4882a593Smuzhiyun		clock-names = "core-clk", "pclk", "spdif", "grf";
44*4882a593Smuzhiyun		assigned-clocks = <&cru SCLK_DP_CORE>;
45*4882a593Smuzhiyun		assigned-clock-rates = <100000000>;
46*4882a593Smuzhiyun		power-domains = <&power RK3399_PD_HDCP>;
47*4882a593Smuzhiyun		phys = <&tcphy0_dp>, <&tcphy1_dp>;
48*4882a593Smuzhiyun		resets = <&cru SRST_DPTX_SPDIF_REC>;
49*4882a593Smuzhiyun		reset-names = "spdif";
50*4882a593Smuzhiyun		extcon = <&fusb0>, <&fusb1>;
51*4882a593Smuzhiyun		rockchip,grf = <&grf>;
52*4882a593Smuzhiyun		#address-cells = <1>;
53*4882a593Smuzhiyun		#size-cells = <0>;
54*4882a593Smuzhiyun		#sound-dai-cells = <1>;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun		ports {
57*4882a593Smuzhiyun			#address-cells = <1>;
58*4882a593Smuzhiyun			#size-cells = <0>;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun			dp_in: port {
61*4882a593Smuzhiyun				#address-cells = <1>;
62*4882a593Smuzhiyun				#size-cells = <0>;
63*4882a593Smuzhiyun				dp_in_vopb: endpoint@0 {
64*4882a593Smuzhiyun					reg = <0>;
65*4882a593Smuzhiyun					remote-endpoint = <&vopb_out_dp>;
66*4882a593Smuzhiyun				};
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun				dp_in_vopl: endpoint@1 {
69*4882a593Smuzhiyun					reg = <1>;
70*4882a593Smuzhiyun					remote-endpoint = <&vopl_out_dp>;
71*4882a593Smuzhiyun				};
72*4882a593Smuzhiyun			};
73*4882a593Smuzhiyun		};
74*4882a593Smuzhiyun	};
75