1 /*
2 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <asm/armv8/mmu.h>
9 #include <asm/arch/bootrom.h>
10 #include <asm/arch/grf_rk3399.h>
11 #include <asm/arch/cru_rk3399.h>
12 #include <asm/arch/hardware.h>
13 #include <asm/io.h>
14 #include <syscon.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 #define GRF_EMMCCORE_CON11 0xff77f02c
19 #define PMU_GRF_SOC_CON0 0xff320180
20
21 static struct mm_region rk3399_mem_map[] = {
22 {
23 .virt = 0x0UL,
24 .phys = 0x0UL,
25 .size = 0xf8000000UL,
26 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
27 PTE_BLOCK_INNER_SHARE
28 }, {
29 .virt = 0xf8000000UL,
30 .phys = 0xf8000000UL,
31 .size = 0x08000000UL,
32 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
33 PTE_BLOCK_NON_SHARE |
34 PTE_BLOCK_PXN | PTE_BLOCK_UXN
35 }, {
36 /* List terminator */
37 0,
38 }
39 };
40
41 struct mm_region *mem_map = rk3399_mem_map;
42
43 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
44 [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
45 [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
46 [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000",
47 };
48
49 #ifdef CONFIG_SPL_BUILD
50
51 #define TIMER_CHN10_BASE 0xff8680a0
52 #define TIMER_END_COUNT_L 0x00
53 #define TIMER_END_COUNT_H 0x04
54 #define TIMER_INIT_COUNT_L 0x10
55 #define TIMER_INIT_COUNT_H 0x14
56 #define TIMER_CONTROL_REG 0x1c
57
58 #define TIMER_EN 0x1
59 #define TIMER_FMODE (0 << 1)
60 #define TIMER_RMODE (1 << 1)
61
rockchip_stimer_init(void)62 void rockchip_stimer_init(void)
63 {
64 writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
65 writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
66 writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
67 writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
68 writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
69 }
70 #endif
71
72 #define GRF_BASE 0xff770000
73 #define PMUGRF_BASE 0xff320000
74 #define PMUSGRF_BASE 0xff330000
75 #define PMUCRU_BASE 0xff750000
76 #define NIU_PERILP_NSP_ADDR 0xffad8188
77 #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3))
78
79 #ifndef CONFIG_TPL_BUILD
arch_cpu_init(void)80 int arch_cpu_init(void)
81 {
82 struct rk3399_pmugrf_regs *pmugrf = (void *)PMUGRF_BASE;
83 struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
84
85 /* We do some SoC one time setting here. */
86
87 #ifdef CONFIG_SPL_BUILD
88 struct rk3399_pmusgrf_regs *sgrf = (void *)PMUSGRF_BASE;
89
90 /*
91 * Disable DDR and SRAM security regions.
92 *
93 * As we are entered from the BootROM, the region from
94 * 0x0 through 0xfffff (i.e. the first MB of memory) will
95 * be protected. This will cause issues with the DW_MMC
96 * driver, which tries to DMA from/to the stack (likely)
97 * located in this range.
98 */
99 rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
100 rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
101 #endif
102
103 /* eMMC clock generator: disable the clock multipilier */
104 rk_clrreg(&grf->emmccore_con[11], 0x0ff);
105
106 /* PWM3 select pwm3a io */
107 rk_clrreg(&pmugrf->soc_con0, 1 << 5);
108
109 #if defined(CONFIG_ROCKCHIP_RK3399PRO)
110 struct rk3399_pmucru *pmucru = (void *)PMUCRU_BASE;
111
112 /* set wifi_26M to 24M and disabled by default */
113 writel(0x7f002000, &pmucru->pmucru_clksel[1]);
114 writel(0x01000100, &pmucru->pmucru_clkgate_con[0]);
115 #endif
116
117 /* Set perilp_nsp QOS priority to 3 for USB 3.0 */
118 writel(QOS_PRIORITY_LEVEL(3, 3), NIU_PERILP_NSP_ADDR);
119
120 return 0;
121 }
122 #endif
123
board_debug_uart_init(void)124 void board_debug_uart_init(void)
125 {
126 #define GRF_BASE 0xff770000
127 struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
128
129 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
130 /* Enable early UART0 on the RK3399 */
131 rk_clrsetreg(&grf->gpio2c_iomux,
132 GRF_GPIO2C0_SEL_MASK,
133 GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
134 rk_clrsetreg(&grf->gpio2c_iomux,
135 GRF_GPIO2C1_SEL_MASK,
136 GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
137 #else
138 /* Enable early UART2 channel on the RK3399/RK3399PRO */
139 rk_clrsetreg(&grf->gpio4c_iomux,
140 GRF_GPIO4C3_SEL_MASK,
141 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
142 rk_clrsetreg(&grf->gpio4c_iomux,
143 GRF_GPIO4C4_SEL_MASK,
144 GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
145 #if defined(CONFIG_ROCKCHIP_RK3399PRO)
146 /* Set channel A as UART2 input */
147 rk_clrsetreg(&grf->soc_con7,
148 GRF_UART_DBG_SEL_MASK,
149 GRF_UART_DBG_SEL_A << GRF_UART_DBG_SEL_SHIFT);
150 #else
151 /* Set channel C as UART2 input */
152 rk_clrsetreg(&grf->soc_con7,
153 GRF_UART_DBG_SEL_MASK,
154 GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
155 #endif
156 #endif
157 }
158