1/* 2 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3399-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/power/rk3399-power.h> 13#include <dt-bindings/thermal/thermal.h> 14#define USB_CLASS_HUB 9 15 16/ { 17 compatible = "rockchip,rk3399"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 i2c4 = &i2c4; 29 i2c5 = &i2c5; 30 i2c6 = &i2c6; 31 i2c7 = &i2c7; 32 i2c8 = &i2c8; 33 serial0 = &uart0; 34 serial1 = &uart1; 35 serial2 = &uart2; 36 serial3 = &uart3; 37 serial4 = &uart4; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 cpu-map { 45 cluster0 { 46 core0 { 47 cpu = <&cpu_l0>; 48 }; 49 core1 { 50 cpu = <&cpu_l1>; 51 }; 52 core2 { 53 cpu = <&cpu_l2>; 54 }; 55 core3 { 56 cpu = <&cpu_l3>; 57 }; 58 }; 59 60 cluster1 { 61 core0 { 62 cpu = <&cpu_b0>; 63 }; 64 core1 { 65 cpu = <&cpu_b1>; 66 }; 67 }; 68 }; 69 70 cpu_l0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53", "arm,armv8"; 73 reg = <0x0 0x0>; 74 enable-method = "psci"; 75 #cooling-cells = <2>; /* min followed by max */ 76 clocks = <&cru ARMCLKL>; 77 }; 78 79 cpu_l1: cpu@1 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a53", "arm,armv8"; 82 reg = <0x0 0x1>; 83 enable-method = "psci"; 84 clocks = <&cru ARMCLKL>; 85 }; 86 87 cpu_l2: cpu@2 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53", "arm,armv8"; 90 reg = <0x0 0x2>; 91 enable-method = "psci"; 92 clocks = <&cru ARMCLKL>; 93 }; 94 95 cpu_l3: cpu@3 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a53", "arm,armv8"; 98 reg = <0x0 0x3>; 99 enable-method = "psci"; 100 clocks = <&cru ARMCLKL>; 101 }; 102 103 cpu_b0: cpu@100 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a72", "arm,armv8"; 106 reg = <0x0 0x100>; 107 enable-method = "psci"; 108 #cooling-cells = <2>; /* min followed by max */ 109 clocks = <&cru ARMCLKB>; 110 }; 111 112 cpu_b1: cpu@101 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a72", "arm,armv8"; 115 reg = <0x0 0x101>; 116 enable-method = "psci"; 117 clocks = <&cru ARMCLKB>; 118 }; 119 }; 120 121 display_subsystem: display-subsystem { 122 compatible = "rockchip,display-subsystem"; 123 ports = <&vopb_out>, <&vopl_out>; 124 status = "okay"; 125 126 route { 127 route_hdmi: route-hdmi { 128 status = "disabled"; 129 logo,uboot = "logo.bmp"; 130 logo,kernel = "logo_kernel.bmp"; 131 logo,mode = "center"; 132 charge_logo,mode = "center"; 133 connect = <&vopb_out_hdmi>; 134 }; 135 136 route_edp: route-edp { 137 status = "disabled"; 138 logo,uboot = "logo.bmp"; 139 logo,kernel = "logo_kernel.bmp"; 140 logo,mode = "center"; 141 charge_logo,mode = "center"; 142 connect = <&vopb_out_edp>; 143 }; 144 }; 145 }; 146 147 pmu_a53 { 148 compatible = "arm,cortex-a53-pmu"; 149 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 150 }; 151 152 pmu_a72 { 153 compatible = "arm,cortex-a72-pmu"; 154 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 155 }; 156 157 psci: psci { 158 compatible = "arm,psci-1.0"; 159 method = "smc"; 160 }; 161 162 timer { 163 compatible = "arm,armv8-timer"; 164 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 165 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 166 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 167 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 168 arm,no-tick-in-suspend; 169 }; 170 171 xin24m: xin24m { 172 compatible = "fixed-clock"; 173 clock-frequency = <24000000>; 174 clock-output-names = "xin24m"; 175 #clock-cells = <0>; 176 }; 177 178 amba { 179 compatible = "simple-bus"; 180 #address-cells = <2>; 181 #size-cells = <2>; 182 ranges; 183 184 dmac_bus: dma-controller@ff6d0000 { 185 compatible = "arm,pl330", "arm,primecell"; 186 reg = <0x0 0xff6d0000 0x0 0x4000>; 187 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 188 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 189 #dma-cells = <1>; 190 clocks = <&cru ACLK_DMAC0_PERILP>; 191 clock-names = "apb_pclk"; 192 }; 193 194 dmac_peri: dma-controller@ff6e0000 { 195 compatible = "arm,pl330", "arm,primecell"; 196 reg = <0x0 0xff6e0000 0x0 0x4000>; 197 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 198 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 199 #dma-cells = <1>; 200 clocks = <&cru ACLK_DMAC1_PERILP>; 201 clock-names = "apb_pclk"; 202 }; 203 }; 204 205 crypto: crypto@ff8b0000 { 206 compatible = "rockchip,rk3399-crypto"; 207 reg = <0x0 0xff8b0000 0x0 0x10000>; 208 clock-names = "sclk_crypto0", "sclk_crypto1"; 209 clocks = <&cru SCLK_CRYPTO0>, <&cru SCLK_CRYPTO1>; 210 status = "disabled"; 211 }; 212 213 pcie0: pcie@f8000000 { 214 compatible = "rockchip,rk3399-pcie"; 215 reg = <0x0 0xf8000000 0x0 0x2000000>, 216 <0x0 0xfd000000 0x0 0x1000000>; 217 reg-names = "axi-base", "apb-base"; 218 #address-cells = <3>; 219 #size-cells = <2>; 220 #interrupt-cells = <1>; 221 aspm-no-l0s; 222 bus-range = <0x0 0x1>; 223 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 224 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 225 clock-names = "aclk", "aclk-perf", 226 "hclk", "pm"; 227 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 228 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 229 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 230 interrupt-names = "sys", "legacy", "client"; 231 interrupt-map-mask = <0 0 0 7>; 232 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 233 <0 0 0 2 &pcie0_intc 1>, 234 <0 0 0 3 &pcie0_intc 2>, 235 <0 0 0 4 &pcie0_intc 3>; 236 linux,pci-domain = <0>; 237 max-link-speed = <1>; 238 msi-map = <0x0 &its 0x0 0x1000>; 239 phys = <&pcie_phy>; 240 phy-names = "pcie-phy"; 241 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000 242 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>; 243 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 244 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 245 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 246 <&cru SRST_A_PCIE>; 247 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 248 "pm", "pclk", "aclk"; 249 status = "disabled"; 250 251 pcie0_intc: interrupt-controller { 252 interrupt-controller; 253 #address-cells = <0>; 254 #interrupt-cells = <1>; 255 }; 256 }; 257 258 gmac: ethernet@fe300000 { 259 compatible = "rockchip,rk3399-gmac"; 260 reg = <0x0 0xfe300000 0x0 0x10000>; 261 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 262 interrupt-names = "macirq"; 263 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 264 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 265 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 266 <&cru PCLK_GMAC>; 267 clock-names = "stmmaceth", "mac_clk_rx", 268 "mac_clk_tx", "clk_mac_ref", 269 "clk_mac_refout", "aclk_mac", 270 "pclk_mac"; 271 power-domains = <&power RK3399_PD_GMAC>; 272 resets = <&cru SRST_A_GMAC>; 273 reset-names = "stmmaceth"; 274 rockchip,grf = <&grf>; 275 status = "disabled"; 276 }; 277 278 sdio0: dwmmc@fe310000 { 279 compatible = "rockchip,rk3399-dw-mshc", 280 "rockchip,rk3288-dw-mshc"; 281 reg = <0x0 0xfe310000 0x0 0x4000>; 282 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 283 max-frequency = <150000000>; 284 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 285 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 286 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 287 fifo-depth = <0x100>; 288 power-domains = <&power RK3399_PD_SDIOAUDIO>; 289 resets = <&cru SRST_SDIO0>; 290 reset-names = "reset"; 291 status = "disabled"; 292 }; 293 294 sdmmc: dwmmc@fe320000 { 295 compatible = "rockchip,rk3399-dw-mshc", 296 "rockchip,rk3288-dw-mshc"; 297 reg = <0x0 0xfe320000 0x0 0x4000>; 298 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 299 max-frequency = <150000000>; 300 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 301 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 302 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 303 fifo-depth = <0x100>; 304 power-domains = <&power RK3399_PD_SD>; 305 resets = <&cru SRST_SDMMC>; 306 reset-names = "reset"; 307 status = "disabled"; 308 }; 309 310 sdhci: sdhci@fe330000 { 311 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 312 reg = <0x0 0xfe330000 0x0 0x10000>; 313 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 314 arasan,soc-ctl-syscon = <&grf>; 315 assigned-clocks = <&cru SCLK_EMMC>; 316 assigned-clock-rates = <200000000>; 317 max-frequency = <150000000>; 318 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 319 clock-names = "clk_xin", "clk_ahb"; 320 clock-output-names = "emmc_cardclock"; 321 #clock-cells = <0>; 322 phys = <&emmc_phy>; 323 phy-names = "phy_arasan"; 324 power-domains = <&power RK3399_PD_EMMC>; 325 status = "disabled"; 326 }; 327 328 usb_host0_ehci: usb@fe380000 { 329 compatible = "generic-ehci"; 330 reg = <0x0 0xfe380000 0x0 0x20000>; 331 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 332 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 333 <&u2phy0>; 334 clock-names = "usbhost", "arbiter", 335 "utmi"; 336 phys = <&u2phy0_host>; 337 phy-names = "usb"; 338 power-domains = <&power RK3399_PD_PERIHP>; 339 status = "disabled"; 340 }; 341 342 usb_host0_ohci: usb@fe3a0000 { 343 compatible = "generic-ohci"; 344 reg = <0x0 0xfe3a0000 0x0 0x20000>; 345 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 346 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 347 <&u2phy0>; 348 clock-names = "usbhost", "arbiter", 349 "utmi"; 350 phys = <&u2phy0_host>; 351 phy-names = "usb"; 352 power-domains = <&power RK3399_PD_PERIHP>; 353 status = "disabled"; 354 }; 355 356 usb_host1_ehci: usb@fe3c0000 { 357 compatible = "generic-ehci"; 358 reg = <0x0 0xfe3c0000 0x0 0x20000>; 359 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 360 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 361 <&u2phy1>; 362 clock-names = "usbhost", "arbiter", 363 "utmi"; 364 phys = <&u2phy1_host>; 365 phy-names = "usb"; 366 power-domains = <&power RK3399_PD_PERIHP>; 367 status = "disabled"; 368 }; 369 370 usb_host1_ohci: usb@fe3e0000 { 371 compatible = "generic-ohci"; 372 reg = <0x0 0xfe3e0000 0x0 0x20000>; 373 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 374 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 375 <&u2phy1>; 376 clock-names = "usbhost", "arbiter", 377 "utmi"; 378 phys = <&u2phy1_host>; 379 phy-names = "usb"; 380 power-domains = <&power RK3399_PD_PERIHP>; 381 status = "disabled"; 382 }; 383 384 usbdrd3_0: usb0 { 385 compatible = "rockchip,rk3399-dwc3"; 386 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 387 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; 388 clock-names = "ref_clk", "suspend_clk", 389 "bus_clk", "grf_clk"; 390 power-domains = <&power RK3399_PD_USB3>; 391 resets = <&cru SRST_A_USB3_OTG0>; 392 reset-names = "usb3-otg"; 393 #address-cells = <2>; 394 #size-cells = <2>; 395 ranges; 396 status = "disabled"; 397 398 usbdrd_dwc3_0: dwc3@fe800000 { 399 compatible = "snps,dwc3"; 400 reg = <0x0 0xfe800000 0x0 0x100000>; 401 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 402 dr_mode = "otg"; 403 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 404 phy-names = "usb2-phy", "usb3-phy"; 405 phy_type = "utmi_wide"; 406 snps,dis_enblslpm_quirk; 407 snps,dis-u2-freeclk-exists-quirk; 408 snps,dis_u2_susphy_quirk; 409 snps,dis-del-phy-power-chg-quirk; 410 snps,tx-ipgap-linecheck-dis-quirk; 411 snps,xhci-slow-suspend-quirk; 412 snps,xhci-trb-ent-quirk; 413 snps,usb3-warm-reset-on-resume-quirk; 414 status = "disabled"; 415 }; 416 }; 417 418 usbdrd3_1: usb1 { 419 compatible = "rockchip,rk3399-dwc3"; 420 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 421 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>; 422 clock-names = "ref_clk", "suspend_clk", 423 "bus_clk", "grf_clk"; 424 power-domains = <&power RK3399_PD_USB3>; 425 resets = <&cru SRST_A_USB3_OTG1>; 426 reset-names = "usb3-otg"; 427 #address-cells = <2>; 428 #size-cells = <2>; 429 ranges; 430 status = "disabled"; 431 432 usbdrd_dwc3_1: dwc3@fe900000 { 433 compatible = "snps,dwc3"; 434 reg = <0x0 0xfe900000 0x0 0x100000>; 435 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 436 dr_mode = "host"; 437 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 438 phy-names = "usb2-phy", "usb3-phy"; 439 phy_type = "utmi_wide"; 440 snps,dis_enblslpm_quirk; 441 snps,dis-u2-freeclk-exists-quirk; 442 snps,dis_u2_susphy_quirk; 443 snps,dis-del-phy-power-chg-quirk; 444 snps,tx-ipgap-linecheck-dis-quirk; 445 snps,xhci-slow-suspend-quirk; 446 snps,xhci-trb-ent-quirk; 447 snps,usb3-warm-reset-on-resume-quirk; 448 status = "disabled"; 449 }; 450 }; 451 452 gic: interrupt-controller@fee00000 { 453 compatible = "arm,gic-v3"; 454 #interrupt-cells = <4>; 455 #address-cells = <2>; 456 #size-cells = <2>; 457 ranges; 458 interrupt-controller; 459 460 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 461 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 462 <0x0 0xfff00000 0 0x10000>, /* GICC */ 463 <0x0 0xfff10000 0 0x10000>, /* GICH */ 464 <0x0 0xfff20000 0 0x10000>; /* GICV */ 465 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 466 its: interrupt-controller@fee20000 { 467 compatible = "arm,gic-v3-its"; 468 msi-controller; 469 reg = <0x0 0xfee20000 0x0 0x20000>; 470 }; 471 472 ppi-partitions { 473 ppi_cluster0: interrupt-partition-0 { 474 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 475 }; 476 477 ppi_cluster1: interrupt-partition-1 { 478 affinity = <&cpu_b0 &cpu_b1>; 479 }; 480 }; 481 }; 482 483 saradc: saradc@ff100000 { 484 compatible = "rockchip,rk3399-saradc"; 485 reg = <0x0 0xff100000 0x0 0x100>; 486 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 487 #io-channel-cells = <1>; 488 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 489 clock-names = "saradc", "apb_pclk"; 490 resets = <&cru SRST_P_SARADC>; 491 reset-names = "saradc-apb"; 492 status = "disabled"; 493 }; 494 495 i2c1: i2c@ff110000 { 496 compatible = "rockchip,rk3399-i2c"; 497 reg = <0x0 0xff110000 0x0 0x1000>; 498 assigned-clocks = <&cru SCLK_I2C1>; 499 assigned-clock-rates = <200000000>; 500 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 501 clock-names = "i2c", "pclk"; 502 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 503 pinctrl-names = "default"; 504 pinctrl-0 = <&i2c1_xfer>; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 status = "disabled"; 508 }; 509 510 i2c2: i2c@ff120000 { 511 compatible = "rockchip,rk3399-i2c"; 512 reg = <0x0 0xff120000 0x0 0x1000>; 513 assigned-clocks = <&cru SCLK_I2C2>; 514 assigned-clock-rates = <200000000>; 515 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 516 clock-names = "i2c", "pclk"; 517 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 518 pinctrl-names = "default"; 519 pinctrl-0 = <&i2c2_xfer>; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 status = "disabled"; 523 }; 524 525 i2c3: i2c@ff130000 { 526 compatible = "rockchip,rk3399-i2c"; 527 reg = <0x0 0xff130000 0x0 0x1000>; 528 assigned-clocks = <&cru SCLK_I2C3>; 529 assigned-clock-rates = <200000000>; 530 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 531 clock-names = "i2c", "pclk"; 532 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 533 pinctrl-names = "default"; 534 pinctrl-0 = <&i2c3_xfer>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 status = "disabled"; 538 }; 539 540 i2c5: i2c@ff140000 { 541 compatible = "rockchip,rk3399-i2c"; 542 reg = <0x0 0xff140000 0x0 0x1000>; 543 assigned-clocks = <&cru SCLK_I2C5>; 544 assigned-clock-rates = <200000000>; 545 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 546 clock-names = "i2c", "pclk"; 547 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&i2c5_xfer>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 status = "disabled"; 553 }; 554 555 i2c6: i2c@ff150000 { 556 compatible = "rockchip,rk3399-i2c"; 557 reg = <0x0 0xff150000 0x0 0x1000>; 558 assigned-clocks = <&cru SCLK_I2C6>; 559 assigned-clock-rates = <200000000>; 560 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 561 clock-names = "i2c", "pclk"; 562 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 563 pinctrl-names = "default"; 564 pinctrl-0 = <&i2c6_xfer>; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 status = "disabled"; 568 }; 569 570 i2c7: i2c@ff160000 { 571 compatible = "rockchip,rk3399-i2c"; 572 reg = <0x0 0xff160000 0x0 0x1000>; 573 assigned-clocks = <&cru SCLK_I2C7>; 574 assigned-clock-rates = <200000000>; 575 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 576 clock-names = "i2c", "pclk"; 577 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 578 pinctrl-names = "default"; 579 pinctrl-0 = <&i2c7_xfer>; 580 #address-cells = <1>; 581 #size-cells = <0>; 582 status = "disabled"; 583 }; 584 585 uart0: serial@ff180000 { 586 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 587 reg = <0x0 0xff180000 0x0 0x100>; 588 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 589 clock-names = "baudclk", "apb_pclk"; 590 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 591 reg-shift = <2>; 592 reg-io-width = <4>; 593 pinctrl-names = "default"; 594 pinctrl-0 = <&uart0_xfer>; 595 status = "disabled"; 596 }; 597 598 uart1: serial@ff190000 { 599 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 600 reg = <0x0 0xff190000 0x0 0x100>; 601 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 602 clock-names = "baudclk", "apb_pclk"; 603 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 604 reg-shift = <2>; 605 reg-io-width = <4>; 606 pinctrl-names = "default"; 607 pinctrl-0 = <&uart1_xfer>; 608 status = "disabled"; 609 }; 610 611 uart2: serial@ff1a0000 { 612 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 613 reg = <0x0 0xff1a0000 0x0 0x100>; 614 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 615 clock-names = "baudclk", "apb_pclk"; 616 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 617 clock-frequency = <24000000>; 618 reg-shift = <2>; 619 reg-io-width = <4>; 620 pinctrl-names = "default"; 621 pinctrl-0 = <&uart2c_xfer>; 622 status = "disabled"; 623 }; 624 625 uart3: serial@ff1b0000 { 626 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 627 reg = <0x0 0xff1b0000 0x0 0x100>; 628 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 629 clock-names = "baudclk", "apb_pclk"; 630 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 631 reg-shift = <2>; 632 reg-io-width = <4>; 633 pinctrl-names = "default"; 634 pinctrl-0 = <&uart3_xfer>; 635 status = "disabled"; 636 }; 637 638 spi0: spi@ff1c0000 { 639 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 640 reg = <0x0 0xff1c0000 0x0 0x1000>; 641 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 642 clock-names = "spiclk", "apb_pclk"; 643 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 644 pinctrl-names = "default"; 645 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 status = "disabled"; 649 }; 650 651 spi1: spi@ff1d0000 { 652 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 653 reg = <0x0 0xff1d0000 0x0 0x1000>; 654 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 655 clock-names = "spiclk", "apb_pclk"; 656 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 657 pinctrl-names = "default"; 658 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 status = "disabled"; 662 }; 663 664 spi2: spi@ff1e0000 { 665 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 666 reg = <0x0 0xff1e0000 0x0 0x1000>; 667 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 668 clock-names = "spiclk", "apb_pclk"; 669 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 670 pinctrl-names = "default"; 671 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 status = "disabled"; 675 }; 676 677 spi4: spi@ff1f0000 { 678 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 679 reg = <0x0 0xff1f0000 0x0 0x1000>; 680 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 681 clock-names = "spiclk", "apb_pclk"; 682 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 683 pinctrl-names = "default"; 684 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 status = "disabled"; 688 }; 689 690 spi5: spi@ff200000 { 691 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 692 reg = <0x0 0xff200000 0x0 0x1000>; 693 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 694 clock-names = "spiclk", "apb_pclk"; 695 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 696 pinctrl-names = "default"; 697 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 status = "disabled"; 701 }; 702 703 thermal_zones: thermal-zones { 704 cpu_thermal: cpu { 705 polling-delay-passive = <100>; 706 polling-delay = <1000>; 707 708 thermal-sensors = <&tsadc 0>; 709 710 trips { 711 cpu_alert0: cpu_alert0 { 712 temperature = <70000>; 713 hysteresis = <2000>; 714 type = "passive"; 715 }; 716 cpu_alert1: cpu_alert1 { 717 temperature = <75000>; 718 hysteresis = <2000>; 719 type = "passive"; 720 }; 721 cpu_crit: cpu_crit { 722 temperature = <95000>; 723 hysteresis = <2000>; 724 type = "critical"; 725 }; 726 }; 727 728 cooling-maps { 729 map0 { 730 trip = <&cpu_alert0>; 731 cooling-device = 732 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 733 }; 734 map1 { 735 trip = <&cpu_alert1>; 736 cooling-device = 737 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 738 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 739 }; 740 }; 741 }; 742 743 gpu_thermal: gpu { 744 polling-delay-passive = <100>; 745 polling-delay = <1000>; 746 747 thermal-sensors = <&tsadc 1>; 748 749 trips { 750 gpu_alert0: gpu_alert0 { 751 temperature = <75000>; 752 hysteresis = <2000>; 753 type = "passive"; 754 }; 755 gpu_crit: gpu_crit { 756 temperature = <95000>; 757 hysteresis = <2000>; 758 type = "critical"; 759 }; 760 }; 761 762 cooling-maps { 763 map0 { 764 trip = <&gpu_alert0>; 765 cooling-device = 766 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 767 }; 768 }; 769 }; 770 }; 771 772 tsadc: tsadc@ff260000 { 773 compatible = "rockchip,rk3399-tsadc"; 774 reg = <0x0 0xff260000 0x0 0x100>; 775 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 776 assigned-clocks = <&cru SCLK_TSADC>; 777 assigned-clock-rates = <750000>; 778 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 779 clock-names = "tsadc", "apb_pclk"; 780 resets = <&cru SRST_TSADC>; 781 reset-names = "tsadc-apb"; 782 rockchip,grf = <&grf>; 783 rockchip,hw-tshut-temp = <95000>; 784 pinctrl-names = "init", "default", "sleep"; 785 pinctrl-0 = <&otp_gpio>; 786 pinctrl-1 = <&otp_out>; 787 pinctrl-2 = <&otp_gpio>; 788 #thermal-sensor-cells = <1>; 789 status = "disabled"; 790 }; 791 792 qos_emmc: qos@ffa58000 { 793 compatible = "syscon"; 794 reg = <0x0 0xffa58000 0x0 0x20>; 795 }; 796 797 qos_gmac: qos@ffa5c000 { 798 compatible = "syscon"; 799 reg = <0x0 0xffa5c000 0x0 0x20>; 800 }; 801 802 qos_pcie: qos@ffa60080 { 803 compatible = "syscon"; 804 reg = <0x0 0xffa60080 0x0 0x20>; 805 }; 806 807 qos_usb_host0: qos@ffa60100 { 808 compatible = "syscon"; 809 reg = <0x0 0xffa60100 0x0 0x20>; 810 }; 811 812 qos_usb_host1: qos@ffa60180 { 813 compatible = "syscon"; 814 reg = <0x0 0xffa60180 0x0 0x20>; 815 }; 816 817 qos_usb_otg0: qos@ffa70000 { 818 compatible = "syscon"; 819 reg = <0x0 0xffa70000 0x0 0x20>; 820 }; 821 822 qos_usb_otg1: qos@ffa70080 { 823 compatible = "syscon"; 824 reg = <0x0 0xffa70080 0x0 0x20>; 825 }; 826 827 qos_sd: qos@ffa74000 { 828 compatible = "syscon"; 829 reg = <0x0 0xffa74000 0x0 0x20>; 830 }; 831 832 qos_sdioaudio: qos@ffa76000 { 833 compatible = "syscon"; 834 reg = <0x0 0xffa76000 0x0 0x20>; 835 }; 836 837 qos_hdcp: qos@ffa90000 { 838 compatible = "syscon"; 839 reg = <0x0 0xffa90000 0x0 0x20>; 840 }; 841 842 qos_iep: qos@ffa98000 { 843 compatible = "syscon"; 844 reg = <0x0 0xffa98000 0x0 0x20>; 845 }; 846 847 qos_isp0_m0: qos@ffaa0000 { 848 compatible = "syscon"; 849 reg = <0x0 0xffaa0000 0x0 0x20>; 850 }; 851 852 qos_isp0_m1: qos@ffaa0080 { 853 compatible = "syscon"; 854 reg = <0x0 0xffaa0080 0x0 0x20>; 855 }; 856 857 qos_isp1_m0: qos@ffaa8000 { 858 compatible = "syscon"; 859 reg = <0x0 0xffaa8000 0x0 0x20>; 860 }; 861 862 qos_isp1_m1: qos@ffaa8080 { 863 compatible = "syscon"; 864 reg = <0x0 0xffaa8080 0x0 0x20>; 865 }; 866 867 qos_rga_r: qos@ffab0000 { 868 compatible = "syscon"; 869 reg = <0x0 0xffab0000 0x0 0x20>; 870 }; 871 872 qos_rga_w: qos@ffab0080 { 873 compatible = "syscon"; 874 reg = <0x0 0xffab0080 0x0 0x20>; 875 }; 876 877 qos_video_m0: qos@ffab8000 { 878 compatible = "syscon"; 879 reg = <0x0 0xffab8000 0x0 0x20>; 880 }; 881 882 qos_video_m1_r: qos@ffac0000 { 883 compatible = "syscon"; 884 reg = <0x0 0xffac0000 0x0 0x20>; 885 }; 886 887 qos_video_m1_w: qos@ffac0080 { 888 compatible = "syscon"; 889 reg = <0x0 0xffac0080 0x0 0x20>; 890 }; 891 892 qos_vop_big_r: qos@ffac8000 { 893 compatible = "syscon"; 894 reg = <0x0 0xffac8000 0x0 0x20>; 895 }; 896 897 qos_vop_big_w: qos@ffac8080 { 898 compatible = "syscon"; 899 reg = <0x0 0xffac8080 0x0 0x20>; 900 }; 901 902 qos_vop_little: qos@ffad0000 { 903 compatible = "syscon"; 904 reg = <0x0 0xffad0000 0x0 0x20>; 905 }; 906 907 qos_perihp: qos@ffad8080 { 908 compatible = "syscon"; 909 reg = <0x0 0xffad8080 0x0 0x20>; 910 }; 911 912 qos_gpu: qos@ffae0000 { 913 compatible = "syscon"; 914 reg = <0x0 0xffae0000 0x0 0x20>; 915 }; 916 917 pmu: power-management@ff310000 { 918 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 919 reg = <0x0 0xff310000 0x0 0x1000>; 920 921 /* 922 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 923 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 924 * Some of the power domains are grouped together for every 925 * voltage domain. 926 * The detail contents as below. 927 */ 928 power: power-controller { 929 compatible = "rockchip,rk3399-power-controller"; 930 #power-domain-cells = <1>; 931 #address-cells = <1>; 932 #size-cells = <0>; 933 934 /* These power domains are grouped by VD_CENTER */ 935 pd_iep@RK3399_PD_IEP { 936 reg = <RK3399_PD_IEP>; 937 clocks = <&cru ACLK_IEP>, 938 <&cru HCLK_IEP>; 939 pm_qos = <&qos_iep>; 940 }; 941 pd_rga@RK3399_PD_RGA { 942 reg = <RK3399_PD_RGA>; 943 clocks = <&cru ACLK_RGA>, 944 <&cru HCLK_RGA>; 945 pm_qos = <&qos_rga_r>, 946 <&qos_rga_w>; 947 }; 948 pd_vcodec@RK3399_PD_VCODEC { 949 reg = <RK3399_PD_VCODEC>; 950 clocks = <&cru ACLK_VCODEC>, 951 <&cru HCLK_VCODEC>; 952 pm_qos = <&qos_video_m0>; 953 }; 954 pd_vdu@RK3399_PD_VDU { 955 reg = <RK3399_PD_VDU>; 956 clocks = <&cru ACLK_VDU>, 957 <&cru HCLK_VDU>; 958 pm_qos = <&qos_video_m1_r>, 959 <&qos_video_m1_w>; 960 }; 961 962 /* These power domains are grouped by VD_GPU */ 963 pd_gpu@RK3399_PD_GPU { 964 reg = <RK3399_PD_GPU>; 965 clocks = <&cru ACLK_GPU>; 966 pm_qos = <&qos_gpu>; 967 }; 968 969 /* These power domains are grouped by VD_LOGIC */ 970 pd_edp@RK3399_PD_EDP { 971 reg = <RK3399_PD_EDP>; 972 clocks = <&cru PCLK_EDP_CTRL>; 973 }; 974 pd_emmc@RK3399_PD_EMMC { 975 reg = <RK3399_PD_EMMC>; 976 clocks = <&cru ACLK_EMMC>; 977 pm_qos = <&qos_emmc>; 978 }; 979 pd_gmac@RK3399_PD_GMAC { 980 reg = <RK3399_PD_GMAC>; 981 clocks = <&cru ACLK_GMAC>, 982 <&cru PCLK_GMAC>; 983 pm_qos = <&qos_gmac>; 984 }; 985 pd_perihp@RK3399_PD_PERIHP { 986 reg = <RK3399_PD_PERIHP>; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 clocks = <&cru ACLK_PERIHP>; 990 pm_qos = <&qos_perihp>, 991 <&qos_pcie>, 992 <&qos_usb_host0>, 993 <&qos_usb_host1>; 994 995 pd_sd@RK3399_PD_SD { 996 reg = <RK3399_PD_SD>; 997 clocks = <&cru HCLK_SDMMC>, 998 <&cru SCLK_SDMMC>; 999 pm_qos = <&qos_sd>; 1000 }; 1001 }; 1002 pd_sdioaudio@RK3399_PD_SDIOAUDIO { 1003 reg = <RK3399_PD_SDIOAUDIO>; 1004 clocks = <&cru HCLK_SDIO>; 1005 pm_qos = <&qos_sdioaudio>; 1006 }; 1007 pd_usb3@RK3399_PD_USB3 { 1008 reg = <RK3399_PD_USB3>; 1009 clocks = <&cru ACLK_USB3>; 1010 pm_qos = <&qos_usb_otg0>, 1011 <&qos_usb_otg1>; 1012 }; 1013 pd_vio@RK3399_PD_VIO { 1014 reg = <RK3399_PD_VIO>; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 1018 pd_hdcp@RK3399_PD_HDCP { 1019 reg = <RK3399_PD_HDCP>; 1020 clocks = <&cru ACLK_HDCP>, 1021 <&cru HCLK_HDCP>, 1022 <&cru PCLK_HDCP>; 1023 pm_qos = <&qos_hdcp>; 1024 }; 1025 pd_isp0@RK3399_PD_ISP0 { 1026 reg = <RK3399_PD_ISP0>; 1027 clocks = <&cru ACLK_ISP0>, 1028 <&cru HCLK_ISP0>; 1029 pm_qos = <&qos_isp0_m0>, 1030 <&qos_isp0_m1>; 1031 }; 1032 pd_isp1@RK3399_PD_ISP1 { 1033 reg = <RK3399_PD_ISP1>; 1034 clocks = <&cru ACLK_ISP1>, 1035 <&cru HCLK_ISP1>; 1036 pm_qos = <&qos_isp1_m0>, 1037 <&qos_isp1_m1>; 1038 }; 1039 pd_tcpc0@RK3399_PD_TCPC0 { 1040 reg = <RK3399_PD_TCPD0>; 1041 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1042 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1043 }; 1044 pd_tcpc1@RK3399_PD_TCPC1 { 1045 reg = <RK3399_PD_TCPD1>; 1046 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1047 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1048 }; 1049 pd_vo@RK3399_PD_VO { 1050 reg = <RK3399_PD_VO>; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 1054 pd_vopb@RK3399_PD_VOPB { 1055 reg = <RK3399_PD_VOPB>; 1056 clocks = <&cru ACLK_VOP0>, 1057 <&cru HCLK_VOP0>; 1058 pm_qos = <&qos_vop_big_r>, 1059 <&qos_vop_big_w>; 1060 }; 1061 pd_vopl@RK3399_PD_VOPL { 1062 reg = <RK3399_PD_VOPL>; 1063 clocks = <&cru ACLK_VOP1>, 1064 <&cru HCLK_VOP1>; 1065 pm_qos = <&qos_vop_little>; 1066 }; 1067 }; 1068 }; 1069 }; 1070 }; 1071 1072 pmugrf: syscon@ff320000 { 1073 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1074 reg = <0x0 0xff320000 0x0 0x1000>; 1075 #address-cells = <1>; 1076 #size-cells = <1>; 1077 1078 pmu_io_domains: io-domains { 1079 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1080 status = "disabled"; 1081 }; 1082 }; 1083 1084 pmusgrf: syscon@ff330000 { 1085 compatible = "rockchip,rk3399-pmusgrf", "syscon"; 1086 reg = <0x0 0xff330000 0x0 0xe3d4>; 1087 }; 1088 1089 spi3: spi@ff350000 { 1090 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1091 reg = <0x0 0xff350000 0x0 0x1000>; 1092 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1093 clock-names = "spiclk", "apb_pclk"; 1094 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1095 pinctrl-names = "default"; 1096 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1097 #address-cells = <1>; 1098 #size-cells = <0>; 1099 status = "disabled"; 1100 }; 1101 1102 uart4: serial@ff370000 { 1103 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1104 reg = <0x0 0xff370000 0x0 0x100>; 1105 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1106 clock-names = "baudclk", "apb_pclk"; 1107 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1108 reg-shift = <2>; 1109 reg-io-width = <4>; 1110 pinctrl-names = "default"; 1111 pinctrl-0 = <&uart4_xfer>; 1112 status = "disabled"; 1113 }; 1114 1115 i2c4: i2c@ff3d0000 { 1116 compatible = "rockchip,rk3399-i2c"; 1117 reg = <0x0 0xff3d0000 0x0 0x1000>; 1118 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1119 assigned-clock-rates = <200000000>; 1120 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1121 clock-names = "i2c", "pclk"; 1122 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1123 pinctrl-names = "default"; 1124 pinctrl-0 = <&i2c4_xfer>; 1125 #address-cells = <1>; 1126 #size-cells = <0>; 1127 status = "disabled"; 1128 }; 1129 1130 i2c8: i2c@ff3e0000 { 1131 compatible = "rockchip,rk3399-i2c"; 1132 reg = <0x0 0xff3e0000 0x0 0x1000>; 1133 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1134 assigned-clock-rates = <200000000>; 1135 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1136 clock-names = "i2c", "pclk"; 1137 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&i2c8_xfer>; 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 status = "disabled"; 1143 }; 1144 1145 pwm0: pwm@ff420000 { 1146 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1147 reg = <0x0 0xff420000 0x0 0x10>; 1148 #pwm-cells = <3>; 1149 pinctrl-names = "active"; 1150 pinctrl-0 = <&pwm0_pin>; 1151 clocks = <&pmucru PCLK_RKPWM_PMU>; 1152 clock-names = "pwm"; 1153 status = "disabled"; 1154 }; 1155 1156 pwm1: pwm@ff420010 { 1157 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1158 reg = <0x0 0xff420010 0x0 0x10>; 1159 #pwm-cells = <3>; 1160 pinctrl-names = "active"; 1161 pinctrl-0 = <&pwm1_pin>; 1162 clocks = <&pmucru PCLK_RKPWM_PMU>; 1163 clock-names = "pwm"; 1164 status = "disabled"; 1165 }; 1166 1167 pwm2: pwm@ff420020 { 1168 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1169 reg = <0x0 0xff420020 0x0 0x10>; 1170 #pwm-cells = <3>; 1171 pinctrl-names = "active"; 1172 pinctrl-0 = <&pwm2_pin>; 1173 clocks = <&pmucru PCLK_RKPWM_PMU>; 1174 clock-names = "pwm"; 1175 status = "disabled"; 1176 }; 1177 1178 pwm3: pwm@ff420030 { 1179 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1180 reg = <0x0 0xff420030 0x0 0x10>; 1181 #pwm-cells = <3>; 1182 pinctrl-names = "active"; 1183 pinctrl-0 = <&pwm3a_pin>; 1184 clocks = <&pmucru PCLK_RKPWM_PMU>; 1185 clock-names = "pwm"; 1186 status = "disabled"; 1187 }; 1188 1189 cic: syscon@ff620000 { 1190 compatible = "rockchip,rk3399-cic", "syscon"; 1191 reg = <0x0 0xff620000 0x0 0x100>; 1192 }; 1193 1194 dfi: dfi@ff630000 { 1195 reg = <0x00 0xff630000 0x00 0x4000>; 1196 compatible = "rockchip,rk3399-dfi"; 1197 rockchip,pmu = <&pmugrf>; 1198 clocks = <&cru PCLK_DDR_MON>; 1199 clock-names = "pclk_ddr_mon"; 1200 status = "disabled"; 1201 }; 1202 1203 dmc: dmc { 1204 compatible = "rockchip,rk3399-dmc"; 1205 devfreq-events = <&dfi>; 1206 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>; 1207 clocks = <&cru SCLK_DDRCLK>; 1208 clock-names = "dmc_clk"; 1209 reg = <0x0 0xffa80000 0x0 0x0800 1210 0x0 0xffa80800 0x0 0x1800 1211 0x0 0xffa82000 0x0 0x2000 1212 0x0 0xffa84000 0x0 0x1000 1213 0x0 0xffa88000 0x0 0x0800 1214 0x0 0xffa88800 0x0 0x1800 1215 0x0 0xffa8a000 0x0 0x2000 1216 0x0 0xffa8c000 0x0 0x1000>; 1217 }; 1218 1219 efuse0: efuse@ff690000 { 1220 compatible = "rockchip,rk3399-efuse"; 1221 reg = <0x0 0xff690000 0x0 0x80>; 1222 #address-cells = <1>; 1223 #size-cells = <1>; 1224 clocks = <&cru PCLK_EFUSE1024NS>; 1225 clock-names = "pclk_efuse"; 1226 1227 /* Data cells */ 1228 cpu_id: cpu-id@7 { 1229 reg = <0x07 0x10>; 1230 }; 1231 cpub_leakage: cpu-leakage@17 { 1232 reg = <0x17 0x1>; 1233 }; 1234 gpu_leakage: gpu-leakage@18 { 1235 reg = <0x18 0x1>; 1236 }; 1237 center_leakage: center-leakage@19 { 1238 reg = <0x19 0x1>; 1239 }; 1240 cpul_leakage: cpu-leakage@1a { 1241 reg = <0x1a 0x1>; 1242 }; 1243 logic_leakage: logic-leakage@1b { 1244 reg = <0x1b 0x1>; 1245 }; 1246 wafer_info: wafer-info@1c { 1247 reg = <0x1c 0x1>; 1248 }; 1249 }; 1250 1251 pmucru: pmu-clock-controller@ff750000 { 1252 compatible = "rockchip,rk3399-pmucru"; 1253 reg = <0x0 0xff750000 0x0 0x1000>; 1254 rockchip,grf = <&pmugrf>; 1255 #clock-cells = <1>; 1256 #reset-cells = <1>; 1257 assigned-clocks = <&pmucru PLL_PPLL>; 1258 assigned-clock-rates = <676000000>; 1259 }; 1260 1261 cru: clock-controller@ff760000 { 1262 compatible = "rockchip,rk3399-cru"; 1263 reg = <0x0 0xff760000 0x0 0x1000>; 1264 rockchip,grf = <&grf>; 1265 #clock-cells = <1>; 1266 #reset-cells = <1>; 1267 assigned-clocks = 1268 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1269 <&cru PLL_NPLL>, 1270 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1271 <&cru PCLK_PERIHP>, 1272 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1273 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1274 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; 1275 assigned-clock-rates = 1276 <594000000>, <800000000>, 1277 <1000000000>, 1278 <150000000>, <75000000>, 1279 <37500000>, 1280 <100000000>, <100000000>, 1281 <50000000>, <600000000>, 1282 <100000000>, <50000000>; 1283 }; 1284 1285 grf: syscon@ff770000 { 1286 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1287 reg = <0x0 0xff770000 0x0 0x10000>; 1288 #address-cells = <1>; 1289 #size-cells = <1>; 1290 1291 io_domains: io-domains { 1292 compatible = "rockchip,rk3399-io-voltage-domain"; 1293 status = "disabled"; 1294 }; 1295 1296 u2phy0: usb2-phy@e450 { 1297 compatible = "rockchip,rk3399-usb2phy"; 1298 reg = <0xe450 0x10>; 1299 clocks = <&cru SCLK_USB2PHY0_REF>; 1300 clock-names = "phyclk"; 1301 #clock-cells = <0>; 1302 clock-output-names = "clk_usbphy0_480m"; 1303 status = "disabled"; 1304 1305 u2phy0_host: host-port { 1306 #phy-cells = <0>; 1307 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1308 interrupt-names = "linestate"; 1309 status = "disabled"; 1310 }; 1311 1312 u2phy0_otg: otg-port { 1313 #phy-cells = <0>; 1314 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1315 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1316 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1317 interrupt-names = "otg-bvalid", "otg-id", 1318 "linestate"; 1319 status = "disabled"; 1320 }; 1321 }; 1322 1323 u2phy1: usb2-phy@e460 { 1324 compatible = "rockchip,rk3399-usb2phy"; 1325 reg = <0xe460 0x10>; 1326 clocks = <&cru SCLK_USB2PHY1_REF>; 1327 clock-names = "phyclk"; 1328 #clock-cells = <0>; 1329 clock-output-names = "clk_usbphy1_480m"; 1330 status = "disabled"; 1331 1332 u2phy1_host: host-port { 1333 #phy-cells = <0>; 1334 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1335 interrupt-names = "linestate"; 1336 status = "disabled"; 1337 }; 1338 1339 u2phy1_otg: otg-port { 1340 #phy-cells = <0>; 1341 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1342 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1343 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1344 interrupt-names = "otg-bvalid", "otg-id", 1345 "linestate"; 1346 status = "disabled"; 1347 }; 1348 }; 1349 1350 emmc_phy: phy@f780 { 1351 compatible = "rockchip,rk3399-emmc-phy"; 1352 reg = <0xf780 0x24>; 1353 clocks = <&sdhci>; 1354 clock-names = "emmcclk"; 1355 #phy-cells = <0>; 1356 status = "disabled"; 1357 }; 1358 1359 pcie_phy: pcie-phy { 1360 compatible = "rockchip,rk3399-pcie-phy"; 1361 clocks = <&cru SCLK_PCIEPHY_REF>; 1362 clock-names = "refclk"; 1363 #phy-cells = <0>; 1364 resets = <&cru SRST_PCIEPHY>; 1365 reset-names = "phy"; 1366 status = "disabled"; 1367 }; 1368 }; 1369 1370 tcphy0: phy@ff7c0000 { 1371 compatible = "rockchip,rk3399-typec-phy"; 1372 reg = <0x0 0xff7c0000 0x0 0x40000>; 1373 #phy-cells = <1>; 1374 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1375 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1376 clock-names = "tcpdcore", "tcpdphy-ref"; 1377 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1378 assigned-clock-rates = <50000000>; 1379 power-domains = <&power RK3399_PD_TCPD0>; 1380 resets = <&cru SRST_UPHY0>, 1381 <&cru SRST_UPHY0_PIPE_L00>, 1382 <&cru SRST_P_UPHY0_TCPHY>; 1383 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1384 rockchip,grf = <&grf>; 1385 rockchip,typec-conn-dir = <0xe580 0 16>; 1386 rockchip,usb3tousb2-en = <0xe580 3 19>; 1387 rockchip,usb3-host-disable = <0x2434 0 16>; 1388 rockchip,usb3-host-port = <0x2434 12 28>; 1389 rockchip,external-psm = <0xe588 14 30>; 1390 rockchip,pipe-status = <0xe5c0 0 0>; 1391 rockchip,uphy-dp-sel = <0x6268 19 19>; 1392 status = "disabled"; 1393 1394 tcphy0_dp: dp-port { 1395 #phy-cells = <0>; 1396 }; 1397 1398 tcphy0_usb3: usb3-port { 1399 #phy-cells = <0>; 1400 }; 1401 }; 1402 1403 tcphy1: phy@ff800000 { 1404 compatible = "rockchip,rk3399-typec-phy"; 1405 reg = <0x0 0xff800000 0x0 0x40000>; 1406 #phy-cells = <1>; 1407 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1408 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1409 clock-names = "tcpdcore", "tcpdphy-ref"; 1410 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1411 assigned-clock-rates = <50000000>; 1412 power-domains = <&power RK3399_PD_TCPD1>; 1413 resets = <&cru SRST_UPHY1>, 1414 <&cru SRST_UPHY1_PIPE_L00>, 1415 <&cru SRST_P_UPHY1_TCPHY>; 1416 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1417 rockchip,grf = <&grf>; 1418 rockchip,typec-conn-dir = <0xe58c 0 16>; 1419 rockchip,usb3tousb2-en = <0xe58c 3 19>; 1420 rockchip,usb3-host-disable = <0x2444 0 16>; 1421 rockchip,usb3-host-port = <0x2444 12 28>; 1422 rockchip,external-psm = <0xe594 14 30>; 1423 rockchip,pipe-status = <0xe5c0 16 16>; 1424 rockchip,uphy-dp-sel = <0x6268 3 19>; 1425 status = "disabled"; 1426 1427 tcphy1_dp: dp-port { 1428 #phy-cells = <0>; 1429 }; 1430 1431 tcphy1_usb3: usb3-port { 1432 #phy-cells = <0>; 1433 }; 1434 }; 1435 1436 watchdog@ff848000 { 1437 compatible = "snps,dw-wdt"; 1438 reg = <0x0 0xff848000 0x0 0x100>; 1439 clocks = <&cru PCLK_WDT>; 1440 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1441 }; 1442 1443 rktimer: rktimer@ff850000 { 1444 compatible = "rockchip,rk3399-timer"; 1445 reg = <0x0 0xff850000 0x0 0x1000>; 1446 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1447 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1448 clock-names = "pclk", "timer"; 1449 }; 1450 1451 spdif: spdif@ff870000 { 1452 compatible = "rockchip,rk3399-spdif"; 1453 reg = <0x0 0xff870000 0x0 0x1000>; 1454 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1455 dmas = <&dmac_bus 7>; 1456 dma-names = "tx"; 1457 clock-names = "mclk", "hclk"; 1458 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1459 pinctrl-names = "default"; 1460 pinctrl-0 = <&spdif_bus>; 1461 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1462 status = "disabled"; 1463 }; 1464 1465 i2s0: i2s@ff880000 { 1466 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1467 reg = <0x0 0xff880000 0x0 0x1000>; 1468 rockchip,grf = <&grf>; 1469 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1470 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1471 dma-names = "tx", "rx"; 1472 clock-names = "i2s_clk", "i2s_hclk"; 1473 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1474 pinctrl-names = "default"; 1475 pinctrl-0 = <&i2s0_8ch_bus>; 1476 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1477 status = "disabled"; 1478 }; 1479 1480 i2s1: i2s@ff890000 { 1481 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1482 reg = <0x0 0xff890000 0x0 0x1000>; 1483 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1484 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1485 dma-names = "tx", "rx"; 1486 clock-names = "i2s_clk", "i2s_hclk"; 1487 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1488 pinctrl-names = "default"; 1489 pinctrl-0 = <&i2s1_2ch_bus>; 1490 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1491 status = "disabled"; 1492 }; 1493 1494 i2s2: i2s@ff8a0000 { 1495 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1496 reg = <0x0 0xff8a0000 0x0 0x1000>; 1497 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1498 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1499 dma-names = "tx", "rx"; 1500 clock-names = "i2s_clk", "i2s_hclk"; 1501 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1502 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1503 status = "disabled"; 1504 }; 1505 1506 i2c0: i2c@ff3c0000 { 1507 compatible = "rockchip,rk3399-i2c"; 1508 reg = <0x0 0xff3c0000 0x0 0x1000>; 1509 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1510 assigned-clock-rates = <200000000>; 1511 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1512 clock-names = "i2c", "pclk"; 1513 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1514 pinctrl-names = "default"; 1515 pinctrl-0 = <&i2c0_xfer>; 1516 #address-cells = <1>; 1517 #size-cells = <0>; 1518 status = "disabled"; 1519 }; 1520 1521 vopl: vop@ff8f0000 { 1522 compatible = "rockchip,rk3399-vop-lit"; 1523 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1524 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1525 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1526 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1527 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1528 reset-names = "axi", "ahb", "dclk"; 1529 status = "disabled"; 1530 vopl_out: port { 1531 #address-cells = <1>; 1532 #size-cells = <0>; 1533 vopl_out_mipi: endpoint@0 { 1534 reg = <0>; 1535 remote-endpoint = <&mipi_in_vopl>; 1536 }; 1537 1538 vopl_out_hdmi: endpoint@1 { 1539 reg = <1>; 1540 remote-endpoint = <&hdmi_in_vopl>; 1541 }; 1542 1543 vopl_out_edp: endpoint@2 { 1544 reg = <2>; 1545 remote-endpoint = <&edp_in_vopl>; 1546 }; 1547 }; 1548 }; 1549 1550 vopb: vop@ff900000 { 1551 compatible = "rockchip,rk3399-vop-big"; 1552 reg = <0x0 0xff900000 0x0 0x3efc>; 1553 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1554 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1555 #clock-cells = <0>; 1556 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1557 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1558 reset-names = "axi", "ahb", "dclk"; 1559 status = "disabled"; 1560 vopb_out: port { 1561 #address-cells = <1>; 1562 #size-cells = <0>; 1563 vopb_out_mipi: endpoint@0 { 1564 reg = <0>; 1565 remote-endpoint = <&mipi_in_vopb>; 1566 }; 1567 1568 vopb_out_hdmi: endpoint@1 { 1569 reg = <1>; 1570 remote-endpoint = <&hdmi_in_vopb>; 1571 }; 1572 1573 vopb_out_edp: endpoint@2 { 1574 reg = <2>; 1575 remote-endpoint = <&edp_in_vopb>; 1576 }; 1577 }; 1578 }; 1579 1580 hdmi: hdmi@ff940000 { 1581 compatible = "rockchip,rk3399-dw-hdmi"; 1582 reg = <0x0 0xff940000 0x0 0x20000>; 1583 reg-io-width = <4>; 1584 rockchip,grf = <&grf>; 1585 pinctrl-names = "default"; 1586 pinctrl-0 = <&hdmi_i2c_xfer>; 1587 power-domains = <&power RK3399_PD_HDCP>; 1588 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1589 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>; 1590 clock-names = "iahb", "isfr", "vpll", "grf"; 1591 status = "okay"; 1592 1593 ports { 1594 hdmi_in: port { 1595 #address-cells = <1>; 1596 #size-cells = <0>; 1597 hdmi_in_vopb: endpoint@0 { 1598 reg = <0>; 1599 remote-endpoint = <&vopb_out_hdmi>; 1600 }; 1601 hdmi_in_vopl: endpoint@1 { 1602 reg = <1>; 1603 remote-endpoint = <&vopl_out_hdmi>; 1604 }; 1605 }; 1606 }; 1607 }; 1608 1609 mipi_dsi: mipi@ff960000 { 1610 compatible = "rockchip,rk3399_mipi_dsi"; 1611 reg = <0x0 0xff960000 0x0 0x8000>; 1612 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1613 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, 1614 <&cru SCLK_DPHY_TX0_CFG>; 1615 clock-names = "ref", "pclk", "phy_cfg"; 1616 rockchip,grf = <&grf>; 1617 #address-cells = <1>; 1618 #size-cells = <0>; 1619 status = "disabled"; 1620 ports { 1621 #address-cells = <1>; 1622 #size-cells = <0>; 1623 reg = <1>; 1624 mipi_in: port { 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 mipi_in_vopb: endpoint@0 { 1628 reg = <0>; 1629 remote-endpoint = <&vopb_out_mipi>; 1630 }; 1631 mipi_in_vopl: endpoint@1 { 1632 reg = <1>; 1633 remote-endpoint = <&vopl_out_mipi>; 1634 }; 1635 }; 1636 }; 1637 }; 1638 1639 edp: edp@ff970000 { 1640 compatible = "rockchip,rk3399-edp"; 1641 reg = <0x0 0xff970000 0x0 0x8000>; 1642 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1643 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>; 1644 clock-names = "dp", "pclk"; 1645 power-domains = <&power RK3399_PD_EDP>; 1646 resets = <&cru SRST_P_EDP_CTRL>; 1647 reset-names = "dp"; 1648 rockchip,grf = <&grf>; 1649 status = "disabled"; 1650 pinctrl-names = "default"; 1651 pinctrl-0 = <&edp_hpd>; 1652 1653 ports { 1654 #address-cells = <1>; 1655 #size-cells = <0>; 1656 1657 edp_in: port@0 { 1658 reg = <0>; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 1662 edp_in_vopb: endpoint@0 { 1663 reg = <0>; 1664 remote-endpoint = <&vopb_out_edp>; 1665 }; 1666 1667 edp_in_vopl: endpoint@1 { 1668 reg = <1>; 1669 remote-endpoint = <&vopl_out_edp>; 1670 }; 1671 }; 1672 }; 1673 }; 1674 1675 pinctrl: pinctrl { 1676 compatible = "rockchip,rk3399-pinctrl"; 1677 rockchip,grf = <&grf>; 1678 rockchip,pmu = <&pmugrf>; 1679 #address-cells = <2>; 1680 #size-cells = <2>; 1681 ranges; 1682 1683 gpio0: gpio0@ff720000 { 1684 compatible = "rockchip,gpio-bank"; 1685 reg = <0x0 0xff720000 0x0 0x100>; 1686 clocks = <&pmucru PCLK_GPIO0_PMU>; 1687 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1688 1689 gpio-controller; 1690 #gpio-cells = <0x2>; 1691 1692 interrupt-controller; 1693 #interrupt-cells = <0x2>; 1694 }; 1695 1696 gpio1: gpio1@ff730000 { 1697 compatible = "rockchip,gpio-bank"; 1698 reg = <0x0 0xff730000 0x0 0x100>; 1699 clocks = <&pmucru PCLK_GPIO1_PMU>; 1700 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1701 1702 gpio-controller; 1703 #gpio-cells = <0x2>; 1704 1705 interrupt-controller; 1706 #interrupt-cells = <0x2>; 1707 }; 1708 1709 gpio2: gpio2@ff780000 { 1710 compatible = "rockchip,gpio-bank"; 1711 reg = <0x0 0xff780000 0x0 0x100>; 1712 clocks = <&cru PCLK_GPIO2>; 1713 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1714 1715 gpio-controller; 1716 #gpio-cells = <0x2>; 1717 1718 interrupt-controller; 1719 #interrupt-cells = <0x2>; 1720 }; 1721 1722 gpio3: gpio3@ff788000 { 1723 compatible = "rockchip,gpio-bank"; 1724 reg = <0x0 0xff788000 0x0 0x100>; 1725 clocks = <&cru PCLK_GPIO3>; 1726 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1727 1728 gpio-controller; 1729 #gpio-cells = <0x2>; 1730 1731 interrupt-controller; 1732 #interrupt-cells = <0x2>; 1733 }; 1734 1735 gpio4: gpio4@ff790000 { 1736 compatible = "rockchip,gpio-bank"; 1737 reg = <0x0 0xff790000 0x0 0x100>; 1738 clocks = <&cru PCLK_GPIO4>; 1739 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1740 1741 gpio-controller; 1742 #gpio-cells = <0x2>; 1743 1744 interrupt-controller; 1745 #interrupt-cells = <0x2>; 1746 }; 1747 1748 pcfg_pull_up: pcfg-pull-up { 1749 bias-pull-up; 1750 }; 1751 1752 pcfg_pull_down: pcfg-pull-down { 1753 bias-pull-down; 1754 }; 1755 1756 pcfg_pull_none: pcfg-pull-none { 1757 bias-disable; 1758 }; 1759 1760 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1761 bias-disable; 1762 drive-strength = <12>; 1763 }; 1764 1765 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1766 bias-pull-up; 1767 drive-strength = <8>; 1768 }; 1769 1770 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1771 bias-pull-down; 1772 drive-strength = <4>; 1773 }; 1774 1775 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1776 bias-pull-up; 1777 drive-strength = <2>; 1778 }; 1779 1780 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 1781 bias-pull-down; 1782 drive-strength = <12>; 1783 }; 1784 1785 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1786 bias-disable; 1787 drive-strength = <13>; 1788 }; 1789 1790 clock { 1791 clk_32k: clk-32k { 1792 rockchip,pins = <0 RK_PA0 RK_FUNC_2 &pcfg_pull_none>; 1793 }; 1794 }; 1795 1796 edp { 1797 edp_hpd: edp-hpd { 1798 rockchip,pins = 1799 <4 RK_PC7 RK_FUNC_2 &pcfg_pull_none>; 1800 }; 1801 }; 1802 1803 gmac { 1804 rgmii_pins: rgmii-pins { 1805 rockchip,pins = 1806 /* mac_txclk */ 1807 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_13ma>, 1808 /* mac_rxclk */ 1809 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 1810 /* mac_mdio */ 1811 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1812 /* mac_txen */ 1813 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1814 /* mac_clk */ 1815 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1816 /* mac_rxdv */ 1817 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1818 /* mac_mdc */ 1819 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1820 /* mac_rxd1 */ 1821 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1822 /* mac_rxd0 */ 1823 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1824 /* mac_txd1 */ 1825 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1826 /* mac_txd0 */ 1827 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1828 /* mac_rxd3 */ 1829 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1830 /* mac_rxd2 */ 1831 <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1832 /* mac_txd3 */ 1833 <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_13ma>, 1834 /* mac_txd2 */ 1835 <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_13ma>; 1836 }; 1837 1838 rmii_pins: rmii-pins { 1839 rockchip,pins = 1840 /* mac_mdio */ 1841 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1842 /* mac_txen */ 1843 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1844 /* mac_clk */ 1845 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1846 /* mac_rxer */ 1847 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, 1848 /* mac_rxdv */ 1849 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1850 /* mac_mdc */ 1851 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1852 /* mac_rxd1 */ 1853 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1854 /* mac_rxd0 */ 1855 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1856 /* mac_txd1 */ 1857 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1858 /* mac_txd0 */ 1859 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>; 1860 }; 1861 }; 1862 1863 i2c0 { 1864 i2c0_xfer: i2c0-xfer { 1865 rockchip,pins = 1866 <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, 1867 <1 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; 1868 }; 1869 }; 1870 1871 i2c1 { 1872 i2c1_xfer: i2c1-xfer { 1873 rockchip,pins = 1874 <4 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1875 <4 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 1876 }; 1877 }; 1878 1879 i2c2 { 1880 i2c2_xfer: i2c2-xfer { 1881 rockchip,pins = 1882 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>, 1883 <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>; 1884 }; 1885 }; 1886 1887 i2c3 { 1888 i2c3_xfer: i2c3-xfer { 1889 rockchip,pins = 1890 <4 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 1891 <4 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 1892 }; 1893 }; 1894 1895 i2c4 { 1896 i2c4_xfer: i2c4-xfer { 1897 rockchip,pins = 1898 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 1899 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1900 }; 1901 }; 1902 1903 i2c5 { 1904 i2c5_xfer: i2c5-xfer { 1905 rockchip,pins = 1906 <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>, 1907 <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>; 1908 }; 1909 }; 1910 1911 i2c6 { 1912 i2c6_xfer: i2c6-xfer { 1913 rockchip,pins = 1914 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>, 1915 <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 1916 }; 1917 }; 1918 1919 i2c7 { 1920 i2c7_xfer: i2c7-xfer { 1921 rockchip,pins = 1922 <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>, 1923 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 1924 }; 1925 }; 1926 1927 i2c8 { 1928 i2c8_xfer: i2c8-xfer { 1929 rockchip,pins = 1930 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, 1931 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 1932 }; 1933 }; 1934 1935 i2s0 { 1936 i2s0_8ch_bus: i2s0-8ch-bus { 1937 rockchip,pins = 1938 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>, 1939 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 1940 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, 1941 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, 1942 <3 RK_PD4 RK_FUNC_1 &pcfg_pull_none>, 1943 <3 RK_PD5 RK_FUNC_1 &pcfg_pull_none>, 1944 <3 RK_PD6 RK_FUNC_1 &pcfg_pull_none>, 1945 <3 RK_PD7 RK_FUNC_1 &pcfg_pull_none>, 1946 <4 RK_PA0 RK_FUNC_1 &pcfg_pull_none>; 1947 }; 1948 }; 1949 1950 i2s1 { 1951 i2s1_2ch_bus: i2s1-2ch-bus { 1952 rockchip,pins = 1953 <4 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1954 <4 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 1955 <4 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, 1956 <4 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1957 <4 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; 1958 }; 1959 }; 1960 1961 sdio0 { 1962 sdio0_bus1: sdio0-bus1 { 1963 rockchip,pins = 1964 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 1965 }; 1966 1967 sdio0_bus4: sdio0-bus4 { 1968 rockchip,pins = 1969 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>, 1970 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>, 1971 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 1972 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>; 1973 }; 1974 1975 sdio0_cmd: sdio0-cmd { 1976 rockchip,pins = 1977 <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>; 1978 }; 1979 1980 sdio0_clk: sdio0-clk { 1981 rockchip,pins = 1982 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 1983 }; 1984 1985 sdio0_cd: sdio0-cd { 1986 rockchip,pins = 1987 <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>; 1988 }; 1989 1990 sdio0_pwr: sdio0-pwr { 1991 rockchip,pins = 1992 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>; 1993 }; 1994 1995 sdio0_bkpwr: sdio0-bkpwr { 1996 rockchip,pins = 1997 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; 1998 }; 1999 2000 sdio0_wp: sdio0-wp { 2001 rockchip,pins = 2002 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>; 2003 }; 2004 2005 sdio0_int: sdio0-int { 2006 rockchip,pins = 2007 <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>; 2008 }; 2009 }; 2010 2011 sdmmc { 2012 sdmmc_bus1: sdmmc-bus1 { 2013 rockchip,pins = 2014 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 2015 }; 2016 2017 sdmmc_bus4: sdmmc-bus4 { 2018 rockchip,pins = 2019 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>, 2020 <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>, 2021 <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 2022 <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 2023 }; 2024 2025 sdmmc_clk: sdmmc-clk { 2026 rockchip,pins = 2027 <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 2028 }; 2029 2030 sdmmc_cmd: sdmmc-cmd { 2031 rockchip,pins = 2032 <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>; 2033 }; 2034 2035 sdmmc_cd: sdmcc-cd { 2036 rockchip,pins = 2037 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; 2038 }; 2039 2040 sdmmc_wp: sdmmc-wp { 2041 rockchip,pins = 2042 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 2043 }; 2044 }; 2045 2046 sleep { 2047 ap_pwroff: ap-pwroff { 2048 rockchip,pins = <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 2049 }; 2050 2051 ddrio_pwroff: ddrio-pwroff { 2052 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 2053 }; 2054 }; 2055 2056 spdif { 2057 spdif_bus: spdif-bus { 2058 rockchip,pins = 2059 <4 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 2060 }; 2061 2062 spdif_bus_1: spdif-bus-1 { 2063 rockchip,pins = 2064 <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2065 }; 2066 }; 2067 2068 spi0 { 2069 spi0_clk: spi0-clk { 2070 rockchip,pins = 2071 <3 RK_PA6 RK_FUNC_2 &pcfg_pull_up>; 2072 }; 2073 spi0_cs0: spi0-cs0 { 2074 rockchip,pins = 2075 <3 RK_PA7 RK_FUNC_2 &pcfg_pull_up>; 2076 }; 2077 spi0_cs1: spi0-cs1 { 2078 rockchip,pins = 2079 <3 RK_PB0 RK_FUNC_2 &pcfg_pull_up>; 2080 }; 2081 spi0_tx: spi0-tx { 2082 rockchip,pins = 2083 <3 RK_PA5 RK_FUNC_2 &pcfg_pull_up>; 2084 }; 2085 spi0_rx: spi0-rx { 2086 rockchip,pins = 2087 <3 RK_PA4 RK_FUNC_2 &pcfg_pull_up>; 2088 }; 2089 }; 2090 2091 spi1 { 2092 spi1_clk: spi1-clk { 2093 rockchip,pins = 2094 <1 RK_PB1 RK_FUNC_2 &pcfg_pull_up>; 2095 }; 2096 spi1_cs0: spi1-cs0 { 2097 rockchip,pins = 2098 <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up>; 2099 }; 2100 spi1_rx: spi1-rx { 2101 rockchip,pins = 2102 <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up>; 2103 }; 2104 spi1_tx: spi1-tx { 2105 rockchip,pins = 2106 <1 RK_PB0 RK_FUNC_2 &pcfg_pull_up>; 2107 }; 2108 }; 2109 2110 spi2 { 2111 spi2_clk: spi2-clk { 2112 rockchip,pins = 2113 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 2114 }; 2115 spi2_cs0: spi2-cs0 { 2116 rockchip,pins = 2117 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>; 2118 }; 2119 spi2_rx: spi2-rx { 2120 rockchip,pins = 2121 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>; 2122 }; 2123 spi2_tx: spi2-tx { 2124 rockchip,pins = 2125 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>; 2126 }; 2127 }; 2128 2129 spi3 { 2130 spi3_clk: spi3-clk { 2131 rockchip,pins = 2132 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>; 2133 }; 2134 spi3_cs0: spi3-cs0 { 2135 rockchip,pins = 2136 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_up>; 2137 }; 2138 spi3_rx: spi3-rx { 2139 rockchip,pins = 2140 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_up>; 2141 }; 2142 spi3_tx: spi3-tx { 2143 rockchip,pins = 2144 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up>; 2145 }; 2146 }; 2147 2148 spi4 { 2149 spi4_clk: spi4-clk { 2150 rockchip,pins = 2151 <3 RK_PA2 RK_FUNC_2 &pcfg_pull_up>; 2152 }; 2153 spi4_cs0: spi4-cs0 { 2154 rockchip,pins = 2155 <3 RK_PA3 RK_FUNC_2 &pcfg_pull_up>; 2156 }; 2157 spi4_rx: spi4-rx { 2158 rockchip,pins = 2159 <3 RK_PA0 RK_FUNC_2 &pcfg_pull_up>; 2160 }; 2161 spi4_tx: spi4-tx { 2162 rockchip,pins = 2163 <3 RK_PA1 RK_FUNC_2 &pcfg_pull_up>; 2164 }; 2165 }; 2166 2167 spi5 { 2168 spi5_clk: spi5-clk { 2169 rockchip,pins = 2170 <2 RK_PC6 RK_FUNC_2 &pcfg_pull_up>; 2171 }; 2172 spi5_cs0: spi5-cs0 { 2173 rockchip,pins = 2174 <2 RK_PC7 RK_FUNC_2 &pcfg_pull_up>; 2175 }; 2176 spi5_rx: spi5-rx { 2177 rockchip,pins = 2178 <2 RK_PC4 RK_FUNC_2 &pcfg_pull_up>; 2179 }; 2180 spi5_tx: spi5-tx { 2181 rockchip,pins = 2182 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_up>; 2183 }; 2184 }; 2185 2186 tsadc { 2187 otp_gpio: otp-gpio { 2188 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2189 }; 2190 2191 otp_out: otp-out { 2192 rockchip,pins = <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 2193 }; 2194 }; 2195 2196 uart0 { 2197 uart0_xfer: uart0-xfer { 2198 rockchip,pins = 2199 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_up>, 2200 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 2201 }; 2202 2203 uart0_cts: uart0-cts { 2204 rockchip,pins = 2205 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 2206 }; 2207 2208 uart0_rts: uart0-rts { 2209 rockchip,pins = 2210 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 2211 }; 2212 }; 2213 2214 uart1 { 2215 uart1_xfer: uart1-xfer { 2216 rockchip,pins = 2217 <3 RK_PB4 RK_FUNC_2 &pcfg_pull_up>, 2218 <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 2219 }; 2220 }; 2221 2222 uart2a { 2223 uart2a_xfer: uart2a-xfer { 2224 rockchip,pins = 2225 <4 RK_PB0 RK_FUNC_2 &pcfg_pull_up>, 2226 <4 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 2227 }; 2228 }; 2229 2230 uart2b { 2231 uart2b_xfer: uart2b-xfer { 2232 rockchip,pins = 2233 <4 RK_PC0 RK_FUNC_2 &pcfg_pull_up>, 2234 <4 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 2235 }; 2236 }; 2237 2238 uart2c { 2239 uart2c_xfer: uart2c-xfer { 2240 rockchip,pins = 2241 <4 RK_PC3 RK_FUNC_1 &pcfg_pull_up>, 2242 <4 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 2243 }; 2244 }; 2245 2246 uart3 { 2247 uart3_xfer: uart3-xfer { 2248 rockchip,pins = 2249 <3 RK_PB6 RK_FUNC_2 &pcfg_pull_up>, 2250 <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 2251 }; 2252 2253 uart3_cts: uart3-cts { 2254 rockchip,pins = 2255 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 2256 }; 2257 2258 uart3_rts: uart3-rts { 2259 rockchip,pins = 2260 <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 2261 }; 2262 }; 2263 2264 uart4 { 2265 uart4_xfer: uart4-xfer { 2266 rockchip,pins = 2267 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up>, 2268 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 2269 }; 2270 }; 2271 2272 uarthdcp { 2273 uarthdcp_xfer: uarthdcp-xfer { 2274 rockchip,pins = 2275 <4 RK_PC5 RK_FUNC_2 &pcfg_pull_up>, 2276 <4 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 2277 }; 2278 }; 2279 2280 pwm0 { 2281 pwm0_pin: pwm0-pin { 2282 rockchip,pins = 2283 <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 2284 }; 2285 2286 vop0_pwm_pin: vop0-pwm-pin { 2287 rockchip,pins = 2288 <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 2289 }; 2290 }; 2291 2292 pwm1 { 2293 pwm1_pin: pwm1-pin { 2294 rockchip,pins = 2295 <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; 2296 }; 2297 2298 vop1_pwm_pin: vop1-pwm-pin { 2299 rockchip,pins = 2300 <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 2301 }; 2302 }; 2303 2304 pwm2 { 2305 pwm2_pin: pwm2-pin { 2306 rockchip,pins = 2307 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 2308 }; 2309 }; 2310 2311 pwm3a { 2312 pwm3a_pin: pwm3a-pin { 2313 rockchip,pins = 2314 <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 2315 }; 2316 }; 2317 2318 pwm3b { 2319 pwm3b_pin: pwm3b-pin { 2320 rockchip,pins = 2321 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; 2322 }; 2323 }; 2324 2325 hdmi { 2326 hdmi_i2c_xfer: hdmi-i2c-xfer { 2327 rockchip,pins = 2328 <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>, 2329 <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2330 }; 2331 2332 hdmi_cec: hdmi-cec { 2333 rockchip,pins = 2334 <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>; 2335 }; 2336 }; 2337 2338 pcie { 2339 pcie_clkreqn: pci-clkreqn { 2340 rockchip,pins = 2341 <2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>; 2342 }; 2343 2344 pcie_clkreqnb: pci-clkreqnb { 2345 rockchip,pins = 2346 <4 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 2347 }; 2348 2349 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2350 rockchip,pins = 2351 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2352 }; 2353 2354 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2355 rockchip,pins = 2356 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2357 }; 2358 }; 2359 2360 }; 2361}; 2362
