bindings/clock/rockchip%2Crk3399-cru.txt

1 * Rockchip RK3399 Clock and Reset Unit
3 The RK3399 clock controller generates and supplies clock to various
9 - compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
10 - compatible: CRU should be "rockchip,rk3399-cru"
11 - reg: physical base address of the controller and length of memory mapped
13 - #clock-cells: should be 1.
14 - #reset-cells: should be 1.
18 - rockchip,grf: phandle to the syscon managing the "general register files".
19   It is used for GRF muxes, if missing any muxes present in the GRF will not
24 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
32 clock-output-names:
33  - "xin24m" - crystal input - required,
34  - "xin32k" - rtc clock - optional,
35  - "clkin_gmac" - external GMAC clock - optional,
36  - "clkin_i2s" - external I2S clock - optional,
37  - "pclkin_cif" - external ISP clock - optional,
38  - "clk_usbphy0_480m" - output clock of the pll in the usbphy0
39  - "clk_usbphy1_480m" - output clock of the pll in the usbphy1
43 	pmucru: pmu-clock-controller@ff750000 {
44 		compatible = "rockchip,rk3399-pmucru";
46 		#clock-cells = <1>;
47 		#reset-cells = <1>;
50 	cru: clock-controller@ff760000 {
51 		compatible = "rockchip,rk3399-cru";
53 		#clock-cells = <1>;
54 		#reset-cells = <1>;
61 		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
64 		clock-names = "baudclk", "apb_pclk";
66 		reg-shift = <2>;
67 		reg-io-width = <4>;