1*4882a593SmuzhiyunRockchip RK3399 specific extensions to the cdn Display Port with rkfb 2*4882a593Smuzhiyun================================ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible: must be "rockchip,rk3399-cdn-dp-fb" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun- reg: physical base address of the controller and length 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- clocks: from common clock binding: handle to dp clock. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun- clock-names: from common clock binding: 12*4882a593Smuzhiyun Required elements: "core-clk" "pclk" "spdif" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun- resets : a list of phandle + reset specifier pairs 15*4882a593Smuzhiyun- reset-names : string reset name, must be: 16*4882a593Smuzhiyun "spdif" 17*4882a593Smuzhiyun- power-domains : power-domain property defined with a phandle 18*4882a593Smuzhiyun to respective power domain. 19*4882a593Smuzhiyun- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE> 20*4882a593Smuzhiyun- assigned-clock-rates : the DP core clk frequency, shall be: 100000000 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun- rockchip,grf: this soc should set GRF regs, so need get grf here. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun- phys: from general PHY binding: the phandle for the PHY device. 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun- extcon: extcon specifier for the Power Delivery 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun------------------------------------------------------------------------------- 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunExample: 33*4882a593Smuzhiyun cdn_dp_fb: dp-fb@fec00000 { 34*4882a593Smuzhiyun compatible = "rockchip,rk3399-cdn-dp-fb"; 35*4882a593Smuzhiyun reg = <0x0 0xfec00000 0x0 0x100000>; 36*4882a593Smuzhiyun interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 37*4882a593Smuzhiyun clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 38*4882a593Smuzhiyun <&cru SCLK_SPDIF_REC_DPTX>; 39*4882a593Smuzhiyun clock-names = "core-clk", "pclk", "spdif"; 40*4882a593Smuzhiyun assigned-clocks = <&cru SCLK_DP_CORE>; 41*4882a593Smuzhiyun assigned-clock-rates = <100000000>; 42*4882a593Smuzhiyun power-domains = <&power RK3399_PD_HDCP>; 43*4882a593Smuzhiyun phys = <&tcphy0 0>, <&tcphy1 0>; 44*4882a593Smuzhiyun resets = <&cru SRST_DPTX_SPDIF_REC>; 45*4882a593Smuzhiyun reset-names = "spdif"; 46*4882a593Smuzhiyun rockchip,grf = <&grf>; 47*4882a593Smuzhiyun #address-cells = <1>; 48*4882a593Smuzhiyun #size-cells = <0>; 49*4882a593Smuzhiyun #sound-dai-cells = <1>; 50*4882a593Smuzhiyun }; 51