1*4882a593Smuzhiyun* Rockchip RK3399 Clock and Reset Unit 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe RK3399 clock controller generates and supplies clock to various 4*4882a593Smuzhiyuncontrollers within the SoC and also implements a reset controller for SoC 5*4882a593Smuzhiyunperipherals. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired Properties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible: PMU for CRU should be "rockchip,rk3399-pmucru" 10*4882a593Smuzhiyun- compatible: CRU should be "rockchip,rk3399-cru" 11*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory mapped 12*4882a593Smuzhiyun region. 13*4882a593Smuzhiyun- #clock-cells: should be 1. 14*4882a593Smuzhiyun- #reset-cells: should be 1. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunOptional Properties: 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- rockchip,grf: phandle to the syscon managing the "general register files". 19*4882a593Smuzhiyun It is used for GRF muxes, if missing any muxes present in the GRF will not 20*4882a593Smuzhiyun be available. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunEach clock is assigned an identifier and client nodes can use this identifier 23*4882a593Smuzhiyunto specify the clock which they consume. All available clocks are defined as 24*4882a593Smuzhiyunpreprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be 25*4882a593Smuzhiyunused in device tree sources. Similar macros exist for the reset sources in 26*4882a593Smuzhiyunthese files. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunExternal clocks: 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunThere are several clocks that are generated outside the SoC. It is expected 31*4882a593Smuzhiyunthat they are defined using standard clock bindings with following 32*4882a593Smuzhiyunclock-output-names: 33*4882a593Smuzhiyun - "xin24m" - crystal input - required, 34*4882a593Smuzhiyun - "xin32k" - rtc clock - optional, 35*4882a593Smuzhiyun - "clkin_gmac" - external GMAC clock - optional, 36*4882a593Smuzhiyun - "clkin_i2s" - external I2S clock - optional, 37*4882a593Smuzhiyun - "pclkin_cif" - external ISP clock - optional, 38*4882a593Smuzhiyun - "clk_usbphy0_480m" - output clock of the pll in the usbphy0 39*4882a593Smuzhiyun - "clk_usbphy1_480m" - output clock of the pll in the usbphy1 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunExample: Clock controller node: 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun pmucru: pmu-clock-controller@ff750000 { 44*4882a593Smuzhiyun compatible = "rockchip,rk3399-pmucru"; 45*4882a593Smuzhiyun reg = <0x0 0xff750000 0x0 0x1000>; 46*4882a593Smuzhiyun #clock-cells = <1>; 47*4882a593Smuzhiyun #reset-cells = <1>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun cru: clock-controller@ff760000 { 51*4882a593Smuzhiyun compatible = "rockchip,rk3399-cru"; 52*4882a593Smuzhiyun reg = <0x0 0xff760000 0x0 0x1000>; 53*4882a593Smuzhiyun #clock-cells = <1>; 54*4882a593Smuzhiyun #reset-cells = <1>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593SmuzhiyunExample: UART controller node that consumes the clock generated by the clock 58*4882a593Smuzhiyun controller: 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun uart0: serial@ff1a0000 { 61*4882a593Smuzhiyun compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 62*4882a593Smuzhiyun reg = <0x0 0xff180000 0x0 0x100>; 63*4882a593Smuzhiyun clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 64*4882a593Smuzhiyun clock-names = "baudclk", "apb_pclk"; 65*4882a593Smuzhiyun interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 66*4882a593Smuzhiyun reg-shift = <2>; 67*4882a593Smuzhiyun reg-io-width = <4>; 68*4882a593Smuzhiyun }; 69