1Rockchip pvtm device tree bindings 2---------------------------------- 3 4The Process-Voltage-Temperature Monitor (PVTM) is used to monitor the chip 5performance variance caused by chip process, voltage and temperature. 6 7 8Required properties: 9- compatible: Should be one of the following. 10 - "rockchip,px30-pvtm" - for PX30 SoCs. 11 - "rockchip,px30-pmu-pvtm" - for PX30 SoCs. 12 - "rockchip,rk1808-pvtm" - for RK1808 SoCs. 13 - "rockchip,rk1808-pmu-pvtm" - for RK1808 SoCs. 14 - "rockchip,rk1808-npu-pvtm" - for RK1808 SoCs. 15 - "rockchip,rk3288-pvtm" - for RK3288 SoCs. 16 - "rockchip,rk3308-pvtm" - for RK3308 SoCs. 17 - "rockchip,rk3308-pmu-pvtm" - for RK3308 SoCs. 18 - "rockchip,rk3399-pvtm" - for RK3399 SoCs. 19 - "rockchip,rk3399-pmu-pvtm" - for RK3399 SoCs. 20 - "rockchip,rk3568-core-pvtm" - for RK3568 SoCs. 21 - "rockchip,rk3568-gpu-pvtm" - for RK3568 SoCs. 22 - "rockchip,rk3568-npu-pvtm" - for RK3568 SoCs. 23 - "rockchip,rk3588-bigcore0-pvtm" - for RK3588 SoCs. 24 - "rockchip,rk3588-bigcore1-pvtm" - for RK3588 SoCs. 25 - "rockchip,rk3588-litcore-pvtm" - for RK3588 SoCs. 26 - "rockchip,rk3588-gpu-pvtm" - for RK3588 SoCs. 27 - "rockchip,rk3588-npu-pvtm" - for RK3588 SoCs. 28 - "rockchip,rk3588-pmu-pvtm" - for RK3588 SoCs. 29 - "rockchip,rv1126-cpu-pvtm" - for RV1126 SoCs. 30 - "rockchip,rv1126-npu-pvtm" - for RV1126 SoCs. 31 - "rockchip,rv1126-pmu-pvtm" - for RV1126 SoCs. 32- clocks: Must contain an entry for each entry in clock-names. 33 See ../../clocks/clock-bindings.txt for details. 34- clock-names: Should be "clk", "pclk". 35 36Optional properties: 37- resets: Must contain an entry for each entry in reset-names. 38 See ../../reset/reset.txt for details. 39- reset-names: Should be "rst", "rst-p". 40 41 42Example: 43 44grf: syscon@ff770000 { 45 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 46 reg = <0x0 0xff770000 0x0 0x10000>; 47 #address-cells = <1>; 48 #size-cells = <1>; 49 50... 51 52 pvtm: pvtm { 53 compatible = "rockchip,rk3399-pvtm"; 54 #address-cells = <1>; 55 #size-cells = <0>; 56 status = "disabled"; 57 58 pvtm@0 { 59 reg = <0>; 60 clocks = <&cru SCLK_PVTM_CORE_L>; 61 clock-names = "clk"; 62 resets = <&cru SRST_PVTM_CORE_L>; 63 reset-names = "rst"; 64 }; 65 pvtm@1 { 66 reg = <1>; 67 clocks = <&cru SCLK_PVTM_CORE_B>; 68 clock-names = "clk"; 69 resets = <&cru SRST_PVTM_CORE_B>; 70 reset-names = "rst"; 71 }; 72 pvtm@2 { 73 reg = <2>; 74 clocks = <&cru SCLK_PVTM_DDR>; 75 clock-names = "clk"; 76 resets = <&cru SRST_PVTM_DDR>; 77 reset-names = "rst"; 78 }; 79 pvtm@3 { 80 reg = <3>; 81 clocks = <&cru SCLK_PVTM_GPU>; 82 clock-names = "clk"; 83 resets = <&cru SRST_PVTM_GPU>; 84 reset-names = "rst"; 85 }; 86 }; 87} 88