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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dspear3xx.dtsi14 #address-cells = <0>;
15 #size-cells = <0>;
25 reg = <0 0x40000000>;
32 ranges = <0xd0000000 0xd0000000 0x30000000>;
37 reg = <0xf1100000 0x1000>;
43 reg = <0xfc400000 0x1000>;
51 reg = <0xe0800000 0x8000>;
62 reg = <0xfc000000 0x1000>;
69 reg = <0xd0100000 0x1000>;
72 #size-cells = <0>;
[all …]
H A Dspear300.dtsi15 ranges = <0x60000000 0x60000000 0x50000000
16 0xd0000000 0xd0000000 0x30000000>;
20 reg = <0x99000000 0x1000>;
25 reg = <0x60000000 0x1000>;
34 reg = <0x94000000 0x1000 /* FSMC Register */
35 0x80000000 0x0010 /* NAND Base DATA */
36 0x80020000 0x0010 /* NAND Base ADDR */
37 0x80010000 0x0010>; /* NAND Base CMD */
44 reg = <0x70000000 0x100>;
49 shirq: interrupt-controller@0x50000000 {
[all …]
H A Dspear310.dtsi15 ranges = <0x40000000 0x40000000 0x10000000
16 0xb0000000 0xb0000000 0x10000000
17 0xd0000000 0xd0000000 0x30000000>;
21 reg = <0xb4000000 0x1000>;
29 reg = <0x44000000 0x1000 /* FSMC Register */
30 0x40000000 0x0010 /* NAND Base DATA */
31 0x40020000 0x0010 /* NAND Base ADDR */
32 0x40010000 0x0010>; /* NAND Base CMD */
37 shirq: interrupt-controller@0xb4000000 {
39 reg = <0xb4000000 0x1000>;
[all …]
H A Dspear600.dtsi12 #address-cells = <0>;
13 #size-cells = <0>;
23 reg = <0 0x40000000>;
30 ranges = <0xd0000000 0xd0000000 0x30000000>;
35 reg = <0xf1100000 0x1000>;
42 reg = <0xf1000000 0x1000>;
48 reg = <0xfc200000 0x1000>;
56 reg = <0xfc400000 0x1000>;
64 reg = <0xe0800000 0x8000>;
76 reg = <0xd1800000 0x1000 /* FSMC Register */
[all …]
H A Dspear320.dtsi15 ranges = <0x40000000 0x40000000 0x80000000
16 0xd0000000 0xd0000000 0x30000000>;
20 reg = <0xb3000000 0x1000>;
26 reg = <0x90000000 0x1000>;
36 reg = <0x4c000000 0x1000 /* FSMC Register */
37 0x50000000 0x0010 /* NAND Base DATA */
38 0x50020000 0x0010 /* NAND Base ADDR */
39 0x50010000 0x0010>; /* NAND Base CMD */
46 reg = <0x70000000 0x100>;
52 shirq: interrupt-controller@0xb3000000 {
[all …]
H A Dmeson6.dtsi14 #size-cells = <0>;
20 reg = <0x200>;
27 reg = <0x201>;
33 reg = <0xd0000000 0x40000>;
36 ranges = <0x0 0xd0000000 0x40000>;
39 clk81: clk@0 {
40 #clock-cells = <0>;
H A Darmada-xp-db-dxbc2.dts10 * internal registers to 0xf1000000 (instead of the default
11 * 0xd0000000). The 0xf1000000 is the default used by the recent,
14 * left internal registers mapped at 0xd0000000. If you are in this
32 reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
45 devbus,badr-skew-ps = <0>;
48 devbus,rd-setup-ps = <0>;
49 devbus,rd-hold-ps = <0>;
52 devbus,sync-enable = <0>;
74 nand@0 {
75 reg = <0>;
[all …]
H A Darmada-xp-db-xc3-24g4xg.dts10 * internal registers to 0xf1000000 (instead of the default
11 * 0xd0000000). The 0xf1000000 is the default used by the recent,
14 * left internal registers mapped at 0xd0000000. If you are in this
32 reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
49 devbus,badr-skew-ps = <0>;
52 devbus,rd-setup-ps = <0>;
53 devbus,rd-hold-ps = <0>;
56 devbus,sync-enable = <0>;
78 nand@0 {
79 reg = <0>;
[all …]
H A Darmada-370-synology-ds213j.dts8 * internal registers to 0xf1000000 (instead of the old 0xd0000000).
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
13 * registers mapped at 0xd0000000. If you have such a device you will
18 * (s/0xf1000000/0xd0000000/ in 'ranges' below).
36 memory@0 {
38 reg = <0x00000000 0x20000000>; /* 512 MB */
42 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
43 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
44 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
55 pinctrl-0 = <&i2c0_pins>;
[all …]
H A Darmada-xp-synology-ds414.dts8 * internal registers to 0xf1000000 (instead of the old 0xd0000000).
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
13 * registers mapped at 0xd0000000. If you have such a device you will
18 * (s/0xf1000000/0xd0000000/ in 'ranges' below).
36 memory@0 {
38 reg = <0 0x00000000 0 0x40000000>; /* 1GB */
42 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
43 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
44 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
45 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
[all …]
H A Dintegratorap.dts17 #size-cells = <0>;
19 cpu@0 {
28 reg = <0>;
37 operating-points = <71000 0
38 66000 0
39 60000 0
40 48000 0
41 36000 0
42 24000 0
43 12000 0>;
[all …]
/OK3568_Linux_fs/u-boot/arch/x86/dts/
H A Dbroadwell_som-6896.dts18 silent_console = <0>;
30 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
31 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
32 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
34 pch@1f,0 {
35 reg = <0x0000f800 0 0 0 0>;
40 #size-cells = <0>;
42 spi-flash@0 {
43 reg = <0>;
45 memory-map = <0xff000000 0x01000000>;
H A Dqemu-x86_i440fx.dts22 silent_console = <0>;
31 #size-cells = <0>;
34 cpu@0 {
38 reg = <0>;
39 intel,apic-id = <0>;
52 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
53 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
54 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
56 pch@1,0 {
57 reg = <0x00000800 0 0 0 0>;
[all …]
H A Dchromebox_panther.dts18 silent-console = <0>;
31 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
32 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
33 0x01000000 0x0 0x1000 0x1000 0 0xf000>;
35 pch@1f,0 {
36 reg = <0x0000f800 0 0 0 0>;
43 #size-cells = <0>;
45 spi-flash@0 {
48 reg = <0>;
51 memory-map = <0xff800000 0x00800000>;
[all …]
H A Dcougarcanyon2.dts24 silent_console = <0>;
32 update@0 {
59 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
60 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
61 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
63 pch@1f,0 {
64 reg = <0x0000f800 0 0 0 0>;
72 #size-cells = <0>;
74 spi-flash@0 {
75 reg = <0>;
[all …]
H A Dqemu-x86_q35.dts32 silent_console = <0>;
42 #size-cells = <0>;
45 cpu@0 {
49 reg = <0>;
50 intel,apic-id = <0>;
63 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
64 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
65 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
67 pch@1f,0 {
68 reg = <0x0000f800 0 0 0 0>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/bus/
H A Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
H A Dnvidia,tegra20-gmi.txt54 Programming 0 means 1 clock cycle: actual cycle = programmed cycle + 1
57 bus. Valid values are 0-15, default is 1
60 (in case of MASTER Request). Valid values are 0-15, default is 1
62 Valid values are 0-15, default is 1.
64 Valid values are 0-15, default is 4
66 Valid values are 0-15, default is 1
68 Valid values are 0-255, default is 1
70 Valid values are 0-255, default is 3
78 reg = <0x70009000 0x1000>;
85 ranges = <4 0 0xd0000000 0xfffffff>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-spear/include/mach/
H A Dspear.h21 #define SPEAR_ICM1_2_BASE UL(0xD0000000)
22 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
23 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)
25 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
28 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
29 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
32 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
33 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
34 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
35 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Ddesignware-pcie.txt46 0x00-0xff is assumed if not present)
55 reg = <0xdfc00000 0x0001000>, /* IP registers */
56 <0xd0000000 0x0002000>; /* Configuration space */
61 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000
62 0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
70 reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
71 <0xdfc01000 0x0001000>, /* IP registers 2 */
72 <0xd0000000 0x2000000>; /* Configuration space */
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Darmada-xp-synology-ds414.dts12 * internal registers to 0xf1000000 (instead of the old 0xd0000000).
13 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
17 * registers mapped at 0xd0000000. If you have such a device you will
22 * (s/0xf1000000/0xd0000000/ in 'ranges' below).
47 reg = <0 0x00000000 0 0x40000000>; /* 1GB */
51 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
52 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
61 pcie@1,0 {
62 /* Port 0, Lane 0 */
70 pcie@5,0 {
[all …]
H A Darmada-xp-theadorable.dts49 * internal registers to 0xf1000000 (instead of the default
50 * 0xd0000000). The 0xf1000000 is the default used by the recent,
53 * left internal registers mapped at 0xd0000000. If you are in this
78 reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
82 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
83 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
84 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
110 phy0: ethernet-phy@0 {
111 reg = <0>;
133 spi-flash@0 {
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A DP1010RDB.h21 #define CONFIG_SYS_TEXT_BASE 0x11001000
22 #define CONFIG_SPL_TEXT_BASE 0xD0001000
23 #define CONFIG_SPL_PAD_TO 0x18000
26 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
27 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
40 #define CONFIG_SYS_TEXT_BASE 0x11000000
41 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
46 #define CONFIG_SYS_TEXT_BASE 0x11001000
47 #define CONFIG_SPL_TEXT_BASE 0xD0001000
48 #define CONFIG_SPL_PAD_TO 0x18000
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/include/mach/
H A Dsoc.h14 #define SOC_MV78230_ID 0x7823
15 #define SOC_MV78260_ID 0x7826
16 #define SOC_MV78460_ID 0x7846
17 #define SOC_88F6720_ID 0x6720
18 #define SOC_88F6810_ID 0x6810
19 #define SOC_88F6820_ID 0x6820
20 #define SOC_88F6828_ID 0x6828
23 #define MV_88F67XX_A0_ID 0x3
26 #define MV_88F68XX_Z1_ID 0x0
27 #define MV_88F68XX_A0_ID 0x4
[all …]
/OK3568_Linux_fs/kernel/arch/m68k/include/asm/
H A Dpgtable_mm.h33 } while(0)
75 #define FIRST_USER_ADDRESS 0UL
79 #define KMAP_START 0x0dc00000
80 #define KMAP_END 0x0e000000
82 #define KMAP_START 0xe0000000
83 #define KMAP_END 0xf0000000
85 #define KMAP_START 0xd0000000
86 #define KMAP_END 0xf0000000
91 #define VMALLOC_START 0x0f800000
94 #define VMALLOC_START 0xd0000000
[all …]

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