1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * DTS file for SPEAr300 SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2012 Viresh Kumar <vireshk@kernel.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/include/ "spear3xx.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun ahb { 12*4882a593Smuzhiyun #address-cells = <1>; 13*4882a593Smuzhiyun #size-cells = <1>; 14*4882a593Smuzhiyun compatible = "simple-bus"; 15*4882a593Smuzhiyun ranges = <0x60000000 0x60000000 0x50000000 16*4882a593Smuzhiyun 0xd0000000 0xd0000000 0x30000000>; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun pinmux@99000000 { 19*4882a593Smuzhiyun compatible = "st,spear300-pinmux"; 20*4882a593Smuzhiyun reg = <0x99000000 0x1000>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun clcd@60000000 { 24*4882a593Smuzhiyun compatible = "arm,pl110", "arm,primecell"; 25*4882a593Smuzhiyun reg = <0x60000000 0x1000>; 26*4882a593Smuzhiyun interrupts = <30>; 27*4882a593Smuzhiyun status = "disabled"; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun fsmc: flash@94000000 { 31*4882a593Smuzhiyun compatible = "st,spear600-fsmc-nand"; 32*4882a593Smuzhiyun #address-cells = <1>; 33*4882a593Smuzhiyun #size-cells = <1>; 34*4882a593Smuzhiyun reg = <0x94000000 0x1000 /* FSMC Register */ 35*4882a593Smuzhiyun 0x80000000 0x0010 /* NAND Base DATA */ 36*4882a593Smuzhiyun 0x80020000 0x0010 /* NAND Base ADDR */ 37*4882a593Smuzhiyun 0x80010000 0x0010>; /* NAND Base CMD */ 38*4882a593Smuzhiyun reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; 39*4882a593Smuzhiyun status = "disabled"; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun sdhci@70000000 { 43*4882a593Smuzhiyun compatible = "st,sdhci-spear"; 44*4882a593Smuzhiyun reg = <0x70000000 0x100>; 45*4882a593Smuzhiyun interrupts = <1>; 46*4882a593Smuzhiyun status = "disabled"; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun shirq: interrupt-controller@0x50000000 { 50*4882a593Smuzhiyun compatible = "st,spear300-shirq"; 51*4882a593Smuzhiyun reg = <0x50000000 0x1000>; 52*4882a593Smuzhiyun interrupts = <28>; 53*4882a593Smuzhiyun #interrupt-cells = <1>; 54*4882a593Smuzhiyun interrupt-controller; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun apb { 58*4882a593Smuzhiyun #address-cells = <1>; 59*4882a593Smuzhiyun #size-cells = <1>; 60*4882a593Smuzhiyun compatible = "simple-bus"; 61*4882a593Smuzhiyun ranges = <0xa0000000 0xa0000000 0x10000000 62*4882a593Smuzhiyun 0xd0000000 0xd0000000 0x30000000>; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun gpio1: gpio@a9000000 { 65*4882a593Smuzhiyun #gpio-cells = <2>; 66*4882a593Smuzhiyun compatible = "arm,pl061", "arm,primecell"; 67*4882a593Smuzhiyun gpio-controller; 68*4882a593Smuzhiyun reg = <0xa9000000 0x1000>; 69*4882a593Smuzhiyun interrupts = <8>; 70*4882a593Smuzhiyun interrupt-parent = <&shirq>; 71*4882a593Smuzhiyun status = "disabled"; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun kbd@a0000000 { 75*4882a593Smuzhiyun compatible = "st,spear300-kbd"; 76*4882a593Smuzhiyun reg = <0xa0000000 0x1000>; 77*4882a593Smuzhiyun interrupts = <7>; 78*4882a593Smuzhiyun interrupt-parent = <&shirq>; 79*4882a593Smuzhiyun status = "disabled"; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun}; 84