1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Device Tree file for Marvell Armada XP theadorable board 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2013-2014 Marvell 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Lior Amsalem <alior@marvell.com> 7*4882a593Smuzhiyun * Gregory CLEMENT <gregory.clement@free-electrons.com> 8*4882a593Smuzhiyun * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms 11*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual 12*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a 13*4882a593Smuzhiyun * whole. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * a) This file is free software; you can redistribute it and/or 16*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 17*4882a593Smuzhiyun * published by the Free Software Foundation; either version 2 of the 18*4882a593Smuzhiyun * License, or (at your option) any later version. 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * This file is distributed in the hope that it will be useful 21*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 22*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23*4882a593Smuzhiyun * GNU General Public License for more details. 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * Or, alternatively 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * b) Permission is hereby granted, free of charge, to any person 28*4882a593Smuzhiyun * obtaining a copy of this software and associated documentation 29*4882a593Smuzhiyun * files (the "Software"), to deal in the Software without 30*4882a593Smuzhiyun * restriction, including without limitation the rights to use 31*4882a593Smuzhiyun * copy, modify, merge, publish, distribute, sublicense, and/or 32*4882a593Smuzhiyun * sell copies of the Software, and to permit persons to whom the 33*4882a593Smuzhiyun * Software is furnished to do so, subject to the following 34*4882a593Smuzhiyun * conditions: 35*4882a593Smuzhiyun * 36*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be 37*4882a593Smuzhiyun * included in all copies or substantial portions of the Software. 38*4882a593Smuzhiyun * 39*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 40*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 41*4882a593Smuzhiyun * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 42*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 43*4882a593Smuzhiyun * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 44*4882a593Smuzhiyun * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 45*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 46*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 47*4882a593Smuzhiyun * 48*4882a593Smuzhiyun * Note: this Device Tree assumes that the bootloader has remapped the 49*4882a593Smuzhiyun * internal registers to 0xf1000000 (instead of the default 50*4882a593Smuzhiyun * 0xd0000000). The 0xf1000000 is the default used by the recent, 51*4882a593Smuzhiyun * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier 52*4882a593Smuzhiyun * boards were delivered with an older version of the bootloader that 53*4882a593Smuzhiyun * left internal registers mapped at 0xd0000000. If you are in this 54*4882a593Smuzhiyun * situation, you should either update your bootloader (preferred 55*4882a593Smuzhiyun * solution) or the below Device Tree should be adjusted. 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun/dts-v1/; 59*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 60*4882a593Smuzhiyun#include "armada-xp-mv78260.dtsi" 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun/ { 63*4882a593Smuzhiyun model = "Marvell Armada XP theadorable"; 64*4882a593Smuzhiyun compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun chosen { 67*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun aliases { 71*4882a593Smuzhiyun spi0 = &spi0; 72*4882a593Smuzhiyun spi1 = &spi1; 73*4882a593Smuzhiyun ethernet0 = ð0; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun memory { 77*4882a593Smuzhiyun device_type = "memory"; 78*4882a593Smuzhiyun reg = <0x00000000 0x00000000 0x00000000 0x80000000>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun soc { 82*4882a593Smuzhiyun ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 83*4882a593Smuzhiyun MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 84*4882a593Smuzhiyun MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun internal-regs { 87*4882a593Smuzhiyun serial@12000 { 88*4882a593Smuzhiyun status = "okay"; 89*4882a593Smuzhiyun u-boot,dm-pre-reloc; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun serial@12100 { 93*4882a593Smuzhiyun status = "okay"; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun serial@12200 { 97*4882a593Smuzhiyun status = "okay"; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun serial@12300 { 101*4882a593Smuzhiyun status = "okay"; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun sata@a0000 { 105*4882a593Smuzhiyun nr-ports = <2>; 106*4882a593Smuzhiyun status = "okay"; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun mdio { 110*4882a593Smuzhiyun phy0: ethernet-phy@0 { 111*4882a593Smuzhiyun reg = <0>; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun ethernet@70000 { 116*4882a593Smuzhiyun status = "okay"; 117*4882a593Smuzhiyun phy = <&phy0>; 118*4882a593Smuzhiyun phy-mode = "sgmii"; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun usb@50000 { 122*4882a593Smuzhiyun status = "okay"; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun usb@51000 { 126*4882a593Smuzhiyun status = "okay"; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun spi0: spi@10600 { 130*4882a593Smuzhiyun status = "okay"; 131*4882a593Smuzhiyun u-boot,dm-pre-reloc; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun spi-flash@0 { 134*4882a593Smuzhiyun u-boot,dm-pre-reloc; 135*4882a593Smuzhiyun #address-cells = <1>; 136*4882a593Smuzhiyun #size-cells = <1>; 137*4882a593Smuzhiyun compatible = "n25q128a13", "jedec,spi-nor"; 138*4882a593Smuzhiyun reg = <0>; /* Chip select 0 */ 139*4882a593Smuzhiyun spi-max-frequency = <27777777>; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun fpga@1 { 143*4882a593Smuzhiyun #address-cells = <1>; 144*4882a593Smuzhiyun #size-cells = <1>; 145*4882a593Smuzhiyun compatible = "spi-generic-device"; 146*4882a593Smuzhiyun reg = <1>; /* Chip select 1 */ 147*4882a593Smuzhiyun spi-max-frequency = <27777777>; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun spi1: spi@10680 { 152*4882a593Smuzhiyun status = "okay"; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun fpga@2 { 155*4882a593Smuzhiyun #address-cells = <1>; 156*4882a593Smuzhiyun #size-cells = <1>; 157*4882a593Smuzhiyun compatible = "spi-generic-device"; 158*4882a593Smuzhiyun reg = <2>; /* Chip select 2 */ 159*4882a593Smuzhiyun spi-max-frequency = <27777777>; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun}; 165