1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * SPEAr3xx/6xx Machine family specific definition 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2009,2012 ST Microelectronics 5*4882a593Smuzhiyun * Rajeev Kumar<rajeev-dlh.kumar@st.com> 6*4882a593Smuzhiyun * Viresh Kumar <vireshk@kernel.org> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 9*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any 10*4882a593Smuzhiyun * warranty of any kind, whether express or implied. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef __MACH_SPEAR_H 14*4882a593Smuzhiyun #define __MACH_SPEAR_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include <asm/memory.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #if defined(CONFIG_ARCH_SPEAR3XX) || defined (CONFIG_ARCH_SPEAR6XX) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* ICM1 - Low speed connection */ 21*4882a593Smuzhiyun #define SPEAR_ICM1_2_BASE UL(0xD0000000) 22*4882a593Smuzhiyun #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000) 23*4882a593Smuzhiyun #define SPEAR_ICM1_UART_BASE UL(0xD0000000) 24*4882a593Smuzhiyun #define VA_SPEAR_ICM1_UART_BASE (VA_SPEAR_ICM1_2_BASE - SPEAR_ICM1_2_BASE + SPEAR_ICM1_UART_BASE) 25*4882a593Smuzhiyun #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* ML-1, 2 - Multi Layer CPU Subsystem */ 28*4882a593Smuzhiyun #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000) 29*4882a593Smuzhiyun #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* ICM3 - Basic Subsystem */ 32*4882a593Smuzhiyun #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) 33*4882a593Smuzhiyun #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000) 34*4882a593Smuzhiyun #define SPEAR_ICM3_DMA_BASE UL(0xFC400000) 35*4882a593Smuzhiyun #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000) 36*4882a593Smuzhiyun #define VA_SPEAR_ICM3_SYS_CTRL_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE - SPEAR_ICM3_SMI_CTRL_BASE + SPEAR_ICM3_SYS_CTRL_BASE) 37*4882a593Smuzhiyun #define SPEAR_ICM3_MISC_REG_BASE UL(0xFCA80000) 38*4882a593Smuzhiyun #define VA_SPEAR_ICM3_MISC_REG_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE - SPEAR_ICM3_SMI_CTRL_BASE + SPEAR_ICM3_MISC_REG_BASE) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* Debug uart for linux, will be used for debug and uncompress messages */ 41*4882a593Smuzhiyun #define SPEAR_DBG_UART_BASE SPEAR_ICM1_UART_BASE 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Sysctl base for spear platform */ 44*4882a593Smuzhiyun #define SPEAR_SYS_CTRL_BASE SPEAR_ICM3_SYS_CTRL_BASE 45*4882a593Smuzhiyun #define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR_ICM3_SYS_CTRL_BASE 46*4882a593Smuzhiyun #endif /* SPEAR3xx || SPEAR6XX */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* SPEAr320 Macros */ 49*4882a593Smuzhiyun #define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) 50*4882a593Smuzhiyun #define VA_SPEAR320_SOC_CONFIG_BASE IOMEM(0xFE000000) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #ifdef CONFIG_ARCH_SPEAR13XX 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define PERIP_GRP2_BASE UL(0xB3000000) 55*4882a593Smuzhiyun #define VA_PERIP_GRP2_BASE IOMEM(0xF9000000) 56*4882a593Smuzhiyun #define MCIF_SDHCI_BASE UL(0xB3000000) 57*4882a593Smuzhiyun #define SYSRAM0_BASE UL(0xB3800000) 58*4882a593Smuzhiyun #define VA_SYSRAM0_BASE IOMEM(0xF9800000) 59*4882a593Smuzhiyun #define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define PERIP_GRP1_BASE UL(0xE0000000) 62*4882a593Smuzhiyun #define VA_PERIP_GRP1_BASE IOMEM(0xFD000000) 63*4882a593Smuzhiyun #define UART_BASE UL(0xE0000000) 64*4882a593Smuzhiyun #define VA_UART_BASE IOMEM(0xFD000000) 65*4882a593Smuzhiyun #define SSP_BASE UL(0xE0100000) 66*4882a593Smuzhiyun #define MISC_BASE UL(0xE0700000) 67*4882a593Smuzhiyun #define VA_MISC_BASE IOMEM(0xFD700000) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define A9SM_AND_MPMC_BASE UL(0xEC000000) 70*4882a593Smuzhiyun #define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define SPEAR1310_RAS_BASE UL(0xD8400000) 73*4882a593Smuzhiyun #define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000)) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* A9SM peripheral offsets */ 76*4882a593Smuzhiyun #define A9SM_PERIP_BASE UL(0xEC800000) 77*4882a593Smuzhiyun #define VA_A9SM_PERIP_BASE IOMEM(0xFC800000) 78*4882a593Smuzhiyun #define VA_SCU_BASE (VA_A9SM_PERIP_BASE + 0x00) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define L2CC_BASE UL(0xED000000) 81*4882a593Smuzhiyun #define VA_L2CC_BASE IOMEM(UL(0xFB000000)) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* others */ 84*4882a593Smuzhiyun #define MCIF_CF_BASE UL(0xB2800000) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* Debug uart for linux, will be used for debug and uncompress messages */ 87*4882a593Smuzhiyun #define SPEAR_DBG_UART_BASE UART_BASE 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #endif /* SPEAR13XX */ 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #endif /* __MACH_SPEAR_H */ 92