1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree file for Synology DS414 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Note: this Device Tree assumes that the bootloader has remapped the 8*4882a593Smuzhiyun * internal registers to 0xf1000000 (instead of the old 0xd0000000). 9*4882a593Smuzhiyun * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot 10*4882a593Smuzhiyun * bootloaders provided by Marvell. It is used in recent versions of 11*4882a593Smuzhiyun * DSM software provided by Synology. Nonetheless, some earlier boards 12*4882a593Smuzhiyun * were delivered with an older version of u-boot that left internal 13*4882a593Smuzhiyun * registers mapped at 0xd0000000. If you have such a device you will 14*4882a593Smuzhiyun * not be able to directly boot a kernel based on this Device Tree. In 15*4882a593Smuzhiyun * that case, the preferred solution is to update your bootloader (e.g. 16*4882a593Smuzhiyun * by upgrading to latest version of DSM, or building a new one and 17*4882a593Smuzhiyun * installing it from u-boot prompt) or adjust the Devive Tree 18*4882a593Smuzhiyun * (s/0xf1000000/0xd0000000/ in 'ranges' below). 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun/dts-v1/; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 24*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 25*4882a593Smuzhiyun#include "armada-xp-mv78230.dtsi" 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun/ { 28*4882a593Smuzhiyun model = "Synology DS414"; 29*4882a593Smuzhiyun compatible = "synology,ds414", "marvell,armadaxp-mv78230", 30*4882a593Smuzhiyun "marvell,armadaxp", "marvell,armada-370-xp"; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun chosen { 33*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun memory@0 { 37*4882a593Smuzhiyun device_type = "memory"; 38*4882a593Smuzhiyun reg = <0 0x00000000 0 0x40000000>; /* 1GB */ 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun soc { 42*4882a593Smuzhiyun ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 43*4882a593Smuzhiyun MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 44*4882a593Smuzhiyun MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 45*4882a593Smuzhiyun MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun internal-regs { 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* RTC is provided by Seiko S-35390A below */ 50*4882a593Smuzhiyun rtc@10300 { 51*4882a593Smuzhiyun status = "disabled"; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun i2c@11000 { 55*4882a593Smuzhiyun clock-frequency = <400000>; 56*4882a593Smuzhiyun status = "okay"; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun s35390a: s35390a@30 { 59*4882a593Smuzhiyun compatible = "sii,s35390a"; 60*4882a593Smuzhiyun reg = <0x30>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Connected to a header on device's PCB. This 65*4882a593Smuzhiyun * provides the main console for the device. 66*4882a593Smuzhiyun * 67*4882a593Smuzhiyun * Warning: the device may not boot with a 3.3V 68*4882a593Smuzhiyun * USB-serial converter connected when the power 69*4882a593Smuzhiyun * button is pressed. The converter needs to be 70*4882a593Smuzhiyun * connected a few seconds after pressing the 71*4882a593Smuzhiyun * power button. This is possibly due to UART0_TXD 72*4882a593Smuzhiyun * pin being sampled at reset (bit 0 of SAR). 73*4882a593Smuzhiyun */ 74*4882a593Smuzhiyun serial@12000 { 75*4882a593Smuzhiyun status = "okay"; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* Connected to a Microchip PIC16F883 for power control */ 79*4882a593Smuzhiyun serial@12100 { 80*4882a593Smuzhiyun status = "okay"; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun poweroff@12100 { 84*4882a593Smuzhiyun compatible = "synology,power-off"; 85*4882a593Smuzhiyun reg = <0x12100 0x100>; 86*4882a593Smuzhiyun clocks = <&coreclk 0>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* Front USB 2.0 port */ 90*4882a593Smuzhiyun usb@50000 { 91*4882a593Smuzhiyun status = "okay"; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun ethernet@70000 { 95*4882a593Smuzhiyun status = "okay"; 96*4882a593Smuzhiyun pinctrl-0 = <&ge0_rgmii_pins>; 97*4882a593Smuzhiyun pinctrl-names = "default"; 98*4882a593Smuzhiyun phy = <&phy1>; 99*4882a593Smuzhiyun phy-mode = "rgmii-id"; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun ethernet@74000 { 103*4882a593Smuzhiyun pinctrl-0 = <&ge1_rgmii_pins>; 104*4882a593Smuzhiyun pinctrl-names = "default"; 105*4882a593Smuzhiyun status = "okay"; 106*4882a593Smuzhiyun phy = <&phy0>; 107*4882a593Smuzhiyun phy-mode = "rgmii-id"; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun regulators { 113*4882a593Smuzhiyun compatible = "simple-bus"; 114*4882a593Smuzhiyun #address-cells = <1>; 115*4882a593Smuzhiyun #size-cells = <0>; 116*4882a593Smuzhiyun pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin 117*4882a593Smuzhiyun &sata3_pwr_pin &sata4_pwr_pin>; 118*4882a593Smuzhiyun pinctrl-names = "default"; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun sata1_regulator: sata1-regulator@1 { 121*4882a593Smuzhiyun compatible = "regulator-fixed"; 122*4882a593Smuzhiyun reg = <1>; 123*4882a593Smuzhiyun regulator-name = "SATA1 Power"; 124*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 125*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 126*4882a593Smuzhiyun startup-delay-us = <2000000>; 127*4882a593Smuzhiyun enable-active-high; 128*4882a593Smuzhiyun regulator-always-on; 129*4882a593Smuzhiyun regulator-boot-on; 130*4882a593Smuzhiyun gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun sata2_regulator: sata2-regulator@2 { 134*4882a593Smuzhiyun compatible = "regulator-fixed"; 135*4882a593Smuzhiyun reg = <2>; 136*4882a593Smuzhiyun regulator-name = "SATA2 Power"; 137*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 138*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 139*4882a593Smuzhiyun startup-delay-us = <4000000>; 140*4882a593Smuzhiyun enable-active-high; 141*4882a593Smuzhiyun regulator-always-on; 142*4882a593Smuzhiyun regulator-boot-on; 143*4882a593Smuzhiyun gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun sata3_regulator: sata3-regulator@3 { 147*4882a593Smuzhiyun compatible = "regulator-fixed"; 148*4882a593Smuzhiyun reg = <3>; 149*4882a593Smuzhiyun regulator-name = "SATA3 Power"; 150*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 151*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 152*4882a593Smuzhiyun startup-delay-us = <6000000>; 153*4882a593Smuzhiyun enable-active-high; 154*4882a593Smuzhiyun regulator-always-on; 155*4882a593Smuzhiyun regulator-boot-on; 156*4882a593Smuzhiyun gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun sata4_regulator: sata4-regulator@4 { 160*4882a593Smuzhiyun compatible = "regulator-fixed"; 161*4882a593Smuzhiyun reg = <4>; 162*4882a593Smuzhiyun regulator-name = "SATA4 Power"; 163*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 164*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 165*4882a593Smuzhiyun startup-delay-us = <8000000>; 166*4882a593Smuzhiyun enable-active-high; 167*4882a593Smuzhiyun regulator-always-on; 168*4882a593Smuzhiyun regulator-boot-on; 169*4882a593Smuzhiyun gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun}; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun&pciec { 175*4882a593Smuzhiyun status = "okay"; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun /* 178*4882a593Smuzhiyun * Connected to Marvell 88SX7042 SATA-II controller 179*4882a593Smuzhiyun * handling the four disks. 180*4882a593Smuzhiyun */ 181*4882a593Smuzhiyun pcie@1,0 { 182*4882a593Smuzhiyun /* Port 0, Lane 0 */ 183*4882a593Smuzhiyun status = "okay"; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun /* 187*4882a593Smuzhiyun * Connected to EtronTech EJ168A XHCI controller 188*4882a593Smuzhiyun * providing the two rear USB 3.0 ports. 189*4882a593Smuzhiyun */ 190*4882a593Smuzhiyun pcie@5,0 { 191*4882a593Smuzhiyun /* Port 1, Lane 0 */ 192*4882a593Smuzhiyun status = "okay"; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun}; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun&mdio { 198*4882a593Smuzhiyun phy0: ethernet-phy@0 { /* Marvell 88E1512 */ 199*4882a593Smuzhiyun reg = <0>; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun phy1: ethernet-phy@1 { /* Marvell 88E1512 */ 203*4882a593Smuzhiyun reg = <1>; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun}; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun&pinctrl { 208*4882a593Smuzhiyun sata1_pwr_pin: sata1-pwr-pin { 209*4882a593Smuzhiyun marvell,pins = "mpp42"; 210*4882a593Smuzhiyun marvell,function = "gpio"; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun sata2_pwr_pin: sata2-pwr-pin { 214*4882a593Smuzhiyun marvell,pins = "mpp44"; 215*4882a593Smuzhiyun marvell,function = "gpio"; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun sata3_pwr_pin: sata3-pwr-pin { 219*4882a593Smuzhiyun marvell,pins = "mpp45"; 220*4882a593Smuzhiyun marvell,function = "gpio"; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun sata4_pwr_pin: sata4-pwr-pin { 224*4882a593Smuzhiyun marvell,pins = "mpp46"; 225*4882a593Smuzhiyun marvell,function = "gpio"; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun sata1_pres_pin: sata1-pres-pin { 229*4882a593Smuzhiyun marvell,pins = "mpp34"; 230*4882a593Smuzhiyun marvell,function = "gpio"; 231*4882a593Smuzhiyun }; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun sata2_pres_pin: sata2-pres-pin { 234*4882a593Smuzhiyun marvell,pins = "mpp35"; 235*4882a593Smuzhiyun marvell,function = "gpio"; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun sata3_pres_pin: sata3-pres-pin { 239*4882a593Smuzhiyun marvell,pins = "mpp40"; 240*4882a593Smuzhiyun marvell,function = "gpio"; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun sata4_pres_pin: sata4-pres-pin { 244*4882a593Smuzhiyun marvell,pins = "mpp41"; 245*4882a593Smuzhiyun marvell,function = "gpio"; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun syno_id_bit0_pin: syno-id-bit0-pin { 249*4882a593Smuzhiyun marvell,pins = "mpp26"; 250*4882a593Smuzhiyun marvell,function = "gpio"; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun syno_id_bit1_pin: syno-id-bit1-pin { 254*4882a593Smuzhiyun marvell,pins = "mpp28"; 255*4882a593Smuzhiyun marvell,function = "gpio"; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun syno_id_bit2_pin: syno-id-bit2-pin { 259*4882a593Smuzhiyun marvell,pins = "mpp29"; 260*4882a593Smuzhiyun marvell,function = "gpio"; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun fan1_alarm_pin: fan1-alarm-pin { 264*4882a593Smuzhiyun marvell,pins = "mpp33"; 265*4882a593Smuzhiyun marvell,function = "gpio"; 266*4882a593Smuzhiyun }; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun fan2_alarm_pin: fan2-alarm-pin { 269*4882a593Smuzhiyun marvell,pins = "mpp32"; 270*4882a593Smuzhiyun marvell,function = "gpio"; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun}; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun&spi0 { 275*4882a593Smuzhiyun status = "okay"; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun spi-flash@0 { 278*4882a593Smuzhiyun #address-cells = <1>; 279*4882a593Smuzhiyun #size-cells = <1>; 280*4882a593Smuzhiyun compatible = "micron,n25q064", "jedec,spi-nor"; 281*4882a593Smuzhiyun reg = <0>; /* Chip select 0 */ 282*4882a593Smuzhiyun spi-max-frequency = <20000000>; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun /* 285*4882a593Smuzhiyun * Warning! 286*4882a593Smuzhiyun * 287*4882a593Smuzhiyun * Synology u-boot uses its compiled-in environment 288*4882a593Smuzhiyun * and it seems Synology did not care to change u-boot 289*4882a593Smuzhiyun * default configuration in order to allow saving a 290*4882a593Smuzhiyun * modified environment at a sensible location. So, 291*4882a593Smuzhiyun * if you do a 'saveenv' under u-boot, your modified 292*4882a593Smuzhiyun * environment will be saved at 1MB after the start 293*4882a593Smuzhiyun * of the flash, i.e. in the middle of the uImage. 294*4882a593Smuzhiyun * For that reason, it is strongly advised not to 295*4882a593Smuzhiyun * change the default environment, unless you know 296*4882a593Smuzhiyun * what you are doing. 297*4882a593Smuzhiyun */ 298*4882a593Smuzhiyun partition@0 { /* u-boot */ 299*4882a593Smuzhiyun label = "RedBoot"; 300*4882a593Smuzhiyun reg = <0x00000000 0x000d0000>; /* 832KB */ 301*4882a593Smuzhiyun }; 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun partition@c0000 { /* uImage */ 304*4882a593Smuzhiyun label = "zImage"; 305*4882a593Smuzhiyun reg = <0x000d0000 0x002d0000>; /* 2880KB */ 306*4882a593Smuzhiyun }; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun partition@3a0000 { /* uInitramfs */ 309*4882a593Smuzhiyun label = "rd.gz"; 310*4882a593Smuzhiyun reg = <0x003a0000 0x00430000>; /* 4250KB */ 311*4882a593Smuzhiyun }; 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun partition@7d0000 { /* MAC address and serial number */ 314*4882a593Smuzhiyun label = "vendor"; 315*4882a593Smuzhiyun reg = <0x007d0000 0x00010000>; /* 64KB */ 316*4882a593Smuzhiyun }; 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun partition@7e0000 { 319*4882a593Smuzhiyun label = "RedBoot config"; 320*4882a593Smuzhiyun reg = <0x007e0000 0x00010000>; /* 64KB */ 321*4882a593Smuzhiyun }; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun partition@7f0000 { 324*4882a593Smuzhiyun label = "FIS directory"; 325*4882a593Smuzhiyun reg = <0x007f0000 0x00010000>; /* 64KB */ 326*4882a593Smuzhiyun }; 327*4882a593Smuzhiyun }; 328*4882a593Smuzhiyun}; 329