1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * DTS file for SPEAr310 SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2012 Viresh Kumar <vireshk@kernel.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/include/ "spear3xx.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun ahb { 12*4882a593Smuzhiyun #address-cells = <1>; 13*4882a593Smuzhiyun #size-cells = <1>; 14*4882a593Smuzhiyun compatible = "simple-bus"; 15*4882a593Smuzhiyun ranges = <0x40000000 0x40000000 0x10000000 16*4882a593Smuzhiyun 0xb0000000 0xb0000000 0x10000000 17*4882a593Smuzhiyun 0xd0000000 0xd0000000 0x30000000>; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun pinmux: pinmux@b4000000 { 20*4882a593Smuzhiyun compatible = "st,spear310-pinmux"; 21*4882a593Smuzhiyun reg = <0xb4000000 0x1000>; 22*4882a593Smuzhiyun #gpio-range-cells = <3>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun fsmc: flash@44000000 { 26*4882a593Smuzhiyun compatible = "st,spear600-fsmc-nand"; 27*4882a593Smuzhiyun #address-cells = <1>; 28*4882a593Smuzhiyun #size-cells = <1>; 29*4882a593Smuzhiyun reg = <0x44000000 0x1000 /* FSMC Register */ 30*4882a593Smuzhiyun 0x40000000 0x0010 /* NAND Base DATA */ 31*4882a593Smuzhiyun 0x40020000 0x0010 /* NAND Base ADDR */ 32*4882a593Smuzhiyun 0x40010000 0x0010>; /* NAND Base CMD */ 33*4882a593Smuzhiyun reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; 34*4882a593Smuzhiyun status = "disabled"; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun shirq: interrupt-controller@0xb4000000 { 38*4882a593Smuzhiyun compatible = "st,spear310-shirq"; 39*4882a593Smuzhiyun reg = <0xb4000000 0x1000>; 40*4882a593Smuzhiyun interrupts = <28 29 30 1>; 41*4882a593Smuzhiyun #interrupt-cells = <1>; 42*4882a593Smuzhiyun interrupt-controller; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun apb { 46*4882a593Smuzhiyun #address-cells = <1>; 47*4882a593Smuzhiyun #size-cells = <1>; 48*4882a593Smuzhiyun compatible = "simple-bus"; 49*4882a593Smuzhiyun ranges = <0xb0000000 0xb0000000 0x10000000 50*4882a593Smuzhiyun 0xd0000000 0xd0000000 0x30000000>; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun serial@b2000000 { 53*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 54*4882a593Smuzhiyun reg = <0xb2000000 0x1000>; 55*4882a593Smuzhiyun interrupts = <8>; 56*4882a593Smuzhiyun interrupt-parent = <&shirq>; 57*4882a593Smuzhiyun status = "disabled"; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun serial@b2080000 { 61*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 62*4882a593Smuzhiyun reg = <0xb2080000 0x1000>; 63*4882a593Smuzhiyun interrupts = <9>; 64*4882a593Smuzhiyun interrupt-parent = <&shirq>; 65*4882a593Smuzhiyun status = "disabled"; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun serial@b2100000 { 69*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 70*4882a593Smuzhiyun reg = <0xb2100000 0x1000>; 71*4882a593Smuzhiyun interrupts = <10>; 72*4882a593Smuzhiyun interrupt-parent = <&shirq>; 73*4882a593Smuzhiyun status = "disabled"; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun serial@b2180000 { 77*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 78*4882a593Smuzhiyun reg = <0xb2180000 0x1000>; 79*4882a593Smuzhiyun interrupts = <11>; 80*4882a593Smuzhiyun interrupt-parent = <&shirq>; 81*4882a593Smuzhiyun status = "disabled"; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun serial@b2200000 { 85*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 86*4882a593Smuzhiyun reg = <0xb2200000 0x1000>; 87*4882a593Smuzhiyun interrupts = <12>; 88*4882a593Smuzhiyun interrupt-parent = <&shirq>; 89*4882a593Smuzhiyun status = "disabled"; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun gpiopinctrl: gpio@b4000000 { 93*4882a593Smuzhiyun compatible = "st,spear-plgpio"; 94*4882a593Smuzhiyun reg = <0xb4000000 0x1000>; 95*4882a593Smuzhiyun #interrupt-cells = <1>; 96*4882a593Smuzhiyun interrupt-controller; 97*4882a593Smuzhiyun gpio-controller; 98*4882a593Smuzhiyun #gpio-cells = <2>; 99*4882a593Smuzhiyun gpio-ranges = <&pinmux 0 0 102>; 100*4882a593Smuzhiyun status = "disabled"; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun st-plgpio,ngpio = <102>; 103*4882a593Smuzhiyun st-plgpio,enb-reg = <0x10>; 104*4882a593Smuzhiyun st-plgpio,wdata-reg = <0x20>; 105*4882a593Smuzhiyun st-plgpio,dir-reg = <0x30>; 106*4882a593Smuzhiyun st-plgpio,ie-reg = <0x50>; 107*4882a593Smuzhiyun st-plgpio,rdata-reg = <0x40>; 108*4882a593Smuzhiyun st-plgpio,mis-reg = <0x60>; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun}; 113